US007464240B2
`
`(12) United States Patent
`Caulkins et a].
`
`(10) Patent N0.2
`(45) Date of Patent:
`
`US 7,464,240 B2
`*Dec. 9, 2008
`
`(54) HYBRID SOLID STATE DISK DRIVE WITH
`CONTROLLER
`
`(75) Inventors: Jason Caulkins, Redding, CA (US);
`Michael Richard Beyer, Redding, CA
`(Us)
`
`(52) US. Cl. ............................. .. 711/165; 711/3; 711/4;
`7ll/l03;711/113;711/162
`(58) Field of Classi?cation Search ............... .. 711/102,
`711/103, 105, 111, 154, 165, 4, 5, 100, 101,
`711/104, 170
`See application ?le for complete search history.
`
`(73) Assignee: Data Ram, Inc., West Windsor, N] (U S)
`
`(56)
`
`References Clted
`
`'
`
`~
`
`~
`
`~
`
`'
`
`U.S. PATENT DOCUMENTS
`
`( * ) Nome:
`
`subleclto any dlsclalmer>_ the term Ofthls
`Pate/I1t 1S mended Or a(busted under 35
`U.S.C. 15403) by 240 days.
`
`7/1996 Blitz et a1. ................... .. 714/6
`5,535,399 A *
`2004/0117586 Al* 6/2004 Estakhri et a1. ........... .. 711/203
`2005/0185496 A1 *
`8/2005 Kaler .................. .. 365/23006
`
`.
`_
`_
`_
`_
`This patent is subject to a terminal d1s
`claimer.
`
`(21) Appl. No.: 11/439,619
`
`(22) Filed:
`
`May 23, 2006
`_
`_
`_
`Pnor Pubhcatlon Data
`Us 2007/0276995 A1
`NOV_ 29, 2007
`
`(65)
`
`(51) Int, Cl,
`G06F 12/00
`G06F 12/16
`
`(2006.01)
`(2006.01)
`
`.
`Write to
`
`RAM
`L
`
`* cited by examiner
`
`Primary Examinerilack A Lane
`(74) Attorney, Agent, or FirmiCentral Coast Patent Agency,
`Inc.
`
`ABSTRACT
`(57)
`A solid-state disk drive includes a ?rst ortion of solid-state
`memory of a volatile nature, a second gortion of solid-state
`memory of a non-volatile nature, a controller for managing
`the memories, and a poWer subsystem for protecting data in
`volatile memory in the event of loss of poWer.
`
`8 Claims, 10 Drawing Sheets
`
`500
`
`J
`
`Compare
`[(EP)-(SP)]
`to FULL Value
`
`Exceed
`
`Identify
`Oldest data
`
`Advance MM
`(SP) next LBA
`
`513
`
`[(EP)-(5P)]
`t0 MIN Value
`
`‘ Advance RAM 4
`(SP) next LBA
`
`Set RLBA
`to 0
`
`HPE, Exh. 1018, p. 1
`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 1 0f 10
`
`US 7,464,240 B2
`
`[- 102 Solid State Disk
`Volatile Memogl
`""" 'iié'A' """ —:|'>
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`
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`
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`
`HPE, Exh. 1018, p. 2
`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 2 0f 10
`
`US 7,464,240 B2
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`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 3 0f 10
`
`US 7,464,240 B2
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`

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`US. Patent
`
`Dec. 9, 2008
`
`Sheet 4 0f 10
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`US 7,464,240 B2
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`

`

`U.S. Patent
`
`Dec. 9, 2008
`
`Sheet 5 of 10
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`US 7,464,240 B2
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`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 6 0f 10
`
`US 7,464,240 B2
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`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 7 0f 10
`
`US 7,464,240 B2
`
`I
`
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`
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`in RAM table
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`HPE, Exh. 1018, p. 8
`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 8 0f 10
`
`US 7,464,240 B2
`
`f 800
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`
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`
`Fig. 8
`
`HPE, Exh. 1018, p. 9
`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 9 0f 10
`
`US 7,464,240 B2
`
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`
`

`

`US. Patent
`
`Dec. 9, 2008
`
`Sheet 10 0f 10
`
`US 7,464,240 B2
`
`SP
`
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`
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`HPE, Exh. 1018, p. 11
`
`

`

`US 7,464,240 B2
`
`1
`HYBRID SOLID STATE DISK DRIVE WITH
`CONTROLLER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`NA
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention is in the ?eld of computer data stor
`age devices and pertains particularly to a system including
`methods and apparatus for high-speed data storage and access
`from a computing device.
`2. Discussion of the State of the Art
`In the ?eld of data storage, non-volatile mechanical disk
`drives have long been relied upon for non-volatile short and
`long-term data storage. More recently, solid-state non-vola
`tile memory has been implemented for data storage needs,
`especially in small portable electronic computing devices
`such as cellular telephones, video cameras and the like. Vola
`tile memory is a solid-state memory typically only used as a
`high-speed temporary memory such as random access
`memory (RAM) of Which there are many variations knoWn.
`Common versions of RAM include Dynamic RandomAccess
`Memory (DRAM) and Static Random Access Memory
`(SRAM). Flash memory is a solid-state high-speed data stor
`age solution used primarily in handheld devices or Universal
`Serial Bus (U SB) peripheral devices. Flash memory provides
`a non-volatile memory for storing data With read speeds
`approaching that of RAM. However, Writing to ?ash memory
`is comparatively much sloWer than RAM.
`Flash memory has practical uses in cell phones, video
`cameras, plug-in cards and USB memory devices and the like.
`Disadvantages of using ?ash as permanent storage in high
`input/output systems, such as transaction servers for
`example, include the fact that a number of Writes performed
`on the memory de?nes the life or Mean Time before Failure
`(MTBF) of a ?ash memory chip. Another disadvantage is that
`access to data, While random for reads and Writes is still
`sloWer than RAM.
`It has occurred to the inventor that there is a need for faster
`data management speeds in the computing industry in general
`and in particular in the area of data intensive servers and other
`business machines. Further, it is desired to provide a pure
`solid-state disk drive that may be implemented as a normal
`hard drive package that is recogniZed and read by a host
`system as a single non-volatile storage disk, Which is sWap
`pable With existing mechanical hard disk drives used in many
`computing systems including desktop computers, data serv
`ers, and in mass storage systems using multiple disks
`deployed in custom or standard array. A system and method
`for implementing the same Would provide much greater data
`access speeds for computing systems in general.
`
`20
`
`25
`
`30
`
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`
`40
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`
`According to an embodiment of the present invention, a
`solid-state disk drive is provided and includes a ?rst portion of
`solid-state memory of a volatile nature, a second portion of
`solid-state memory of a non-volatile nature, a controller for
`managing the memories, and a poWer subsystem for protect
`ing data in volatile memory in the event of loss of poWer. In
`one embodiment, the solid-state disk drive is adapted for use
`With SCSI protocol or variations thereof. In one embodiment,
`the solid-state disk drive is adapted for use With integrated
`
`60
`
`65
`
`2
`drive electronics protocol or variations thereof. In another
`embodiment, the solid-state disk drive is adapted for use With
`serial advanced technology attachment (SATA) or parallel
`advanced technology attachment (PATA) protocols or varia
`tions thereof. In still another embodiment, the solid-state disk
`drive is adapted for use With Fibre Channel netWork protocols
`or variations thereof.
`In one embodiment, the ?rst portion of memory is random
`access memory (RAM) or a variation thereof and the second
`portion of memory is Flash memory. In one embodiment, the
`second portion of memory is one of Magnetoresistive Ran
`domAccess Memory, Ferroelectric RandomAccess Memory,
`or Nano Random Access Memory. In one embodiment, the
`controller has an input and output port to the ?rst memory
`portion, the second memory portion, to a host system, and to
`the poWer subsystem.
`In one embodiment, the controller is a controller board
`With at least one ?eld programmable gate array (FPGA)
`mounted thereon. In another embodiment, the controller is a
`controller board With at least one application speci?c inte
`grated circuit (ASIC) mounted thereon. In one embodiment,
`the poWer subsystem contains a sWitch capable of detecting
`loss of poWer from a host system and sWitching to battery
`poWer.
`According to another aspect of the present invention in a
`solid-state disk having a ?rst portion of solid-state memory of
`a volatile nature and a second portion of solid-state memory
`of a non-volatile nature, a controller for managing the
`memory portions as a single non-volatile memory is pro
`vided. The controller includes at least one integrated circuit
`supporting one or more sets of machine-readable instruc
`tions, a ?rst data port and buffer circuitry for bi-directional
`communication of data betWeen the controller and a host
`system, a second data port and buffer circuitry for bi-direc
`tional communication of data betWeen the controller and the
`volatile memory, and a third data port and buffer circuitry for
`bi-directional communication of data betWeen the controller
`and the non-volatile memory.
`In one embodiment, the integrated circuit is one of an
`FPGA or an ASIC. In one embodiment, the controller is
`con?gured for SCSI or a variation thereof. In another embodi
`ment, the controller is con?gured for IDE or a variation
`thereof. In a preferred embodiment, the integrated circuit is an
`FPGA and the one or more sets of machine-readable instruc
`tions are ?ashed onto a programmable memory in the FPGA.
`According to one embodiment, the controller further
`includes one or more onboard memory chips of a volatile
`nature, and a fourth data port and circuitry for bi-directional
`communication of data With the onboard memory. In this
`aspect, the onboard memory is RAM or a variation thereof.
`According to one embodiment, the controller further
`includes a data path to a poWer subsystem for receiving noti
`?cation of loss of poWer from the host. In one embodiment,
`the memories are addressed using a logical block addressing
`system and the controller is integral to the motherboard of the
`disk drive. In this embodiment, sequential tables for each
`memory space are maintained in the onboard memory and are
`cross-linked per entry to facilitate direct memory address
`mapping betWeen volatile and non-volatile memories.
`In still another embodiment, the controller further includes
`one or more onboard memory chips of a non-volatile nature,
`and a data port and circuitry for bi-directional communication
`of data With a reserved portion of non-volatile memory to
`re-construct data state and maintain counters at startup.
`
`HPE, Exh. 1018, p. 12
`
`

`

`3
`BRIEF DESCRIPTION OF THE DRAWING
`FIGURES
`
`US 7,464,240 B2
`
`4
`voltage differential (LVD) U320 disk. In this exemplary
`embodiment, interface 108 is a standard SCSI SCA 80-pin
`connector, hoWever one With skill in the art Will recogniZe that
`other connectors might be used depending on SCSI version.
`Disk 100 includes a volatile memory 102. Memory 102
`may, in one embodiment, be a version of RAM knoWn as
`synchronous dynamic RAM or SDRAM. In this embodiment
`SDRAM 102 may include an enhancement knoWn as double
`data rate (DDR) Which transfers data both on the rising and
`falling edge of the computer processing unit (CPU) clock
`unit. Other types of RAM are knoWn in the art and are avail
`able to the inventor and might be provided to disk 1 00 Without
`departing from the spirit and scope of the present invention.
`Volatile memory 102 may hold up to 8 gigabytes (GB) or
`more of data including an extra GB reserved for error correct
`ing code (ECC) data. One With skill in the art Will recogniZe
`that volatile memory 102 may be more than or less than 8 GB
`Without departing from the spirit and scope of the present
`invention.
`Disk 100 includes at least one non-volatile memory 103a
`and may include additional non-volatile memories such as a
`non-volatile memory 103!) illustrated herein as an alternate
`memory block, Which may be accessed in place of, or in
`addition to block 10311. In one embodiment, memory 10311 is
`Flash memory. In this embodiment, memory 103!) is also
`Flash memory. Flash memory blocks 103a and 1031) may be
`one of or a combination of NOR Flash or NAND Flash
`Without departing from the spirit and scope of the present
`invention. In one preferred embodiment, NAND Flash is used
`because of a higher density of data storage capacity. HoWever,
`the use of NAND or NOR Flash should not be construed as a
`limitation as future implementations of non-volatile memory
`may also be contemplated and applied Without departing
`from the spirit and scope of the present invention. One
`example is Magnetoresistive Random Access Memory
`(MRAM), Which is currently being developed. Another
`example is Ferroelectric Random Access Memory (FRAM).
`Still another example of non-volatile RAM (N VRAM) is
`Nano Random Access Memory (N RAM).
`In one embodiment, non-volatile memory 10311 is provided
`as a plug-in memory card, sometimes referred to in this speci
`?cation as a daughter card. As such, memory 103!) may be
`thought of as an optional daughter card. There may be more
`than tWo non-volatile memories plugged into disk 100 With
`out departing from the spirit and scope of the present inven
`tion. For purpose of discussion only, the inventor provides up
`to 3 Flash cards or daughter cards that may be shipped With
`disk 100, each card Written to in isolation from the other cards
`according to a unique “Write balancing” technique that Will be
`described later in this speci?cation. In a preferred implemen
`tation a minimum of 8 GB of non-volatile memory is pro
`vided, but up to 128 GB of non-volatile memory may be
`conveniently provided on a single disk 100 Within the stan
`dard form factor boundaries.
`Disk 100 has an onboard poWer supply or subsystem 105
`provided thereto and adapted in one embodiment, to receive
`direct current (DC) poWer from the host system. This is illus
`trated herein by a logical arroW labeled “Host DC” from
`controller 109 to poWer supply 105. Disk 100 also includes an
`onboard chargeable poWer source 106. PoWer source 106 may
`be a rechargeable cell or battery or a bank of those arrayed and
`adapted to provide backup poWer to disk 100 in the event that
`poWer from a connected host system is interrupted. PoWer
`supply 105 has connection to poWer source 106 via at least a
`signal port if not a logical bus structure labeled herein, data.
`PoWer source 106 automatically detects Whenever there is an
`interruption or lack of poWer coming in from the host and
`
`FIG. 1 is a block diagram of a high-speed solid-state non
`volatile disk according to an embodiment of the present
`invention.
`FIG. 2 is a block diagram illustrating use of volatile and
`non-volatile memory in combination for storing and access
`ing data on a disk analogous to the disk of FIG. 1 according to
`an embodiment of the present invention.
`FIG. 3 is a block diagram illustrating a disk controller for
`managing disk function according to an embodiment of the
`present invention.
`FIG. 4 is a How chart illustrating acts for managing Writes
`to a combination RAM and Flash disk according to an
`embodiment of the present invention.
`FIG. 5 is a How chart illustrating acts for managing data in
`RAM according to an embodiment of the present invention.
`FIG. 6 is a How chart illustrating acts for protecting against
`RAM data over?oW according to an embodiment of the
`present invention.
`FIG. 7 is a How chart illustrating acts for optimiZing RAM
`space according to an embodiment of the present invention.
`FIG. 8 is a How chart illustrating acts for Write balancing
`Flash memory according to an embodiment of the present
`invention.
`FIG. 9 is a process How chart illustrating acts for reading
`data from a solid-state non-volatile disk according to an
`embodiment of the present invention.
`FIG. 10 is a logical memory map illustrating mapping of
`memory space according to an embodiment of the present
`invention.
`
`20
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`
`DETAILED DESCRIPTION
`
`FIG. 1 is a block diagram of a hybrid solid-state storage
`device 100 according to an embodiment of the present inven
`tion. Device 100 is adapted as a solid-state storage disk drive
`that may be recogniZed by any standard operating system as
`a standard data storage disk. Device 100 includes a host
`interface 108, Which may be a Small Computer System Inter
`face (SCSI) or one of many knoWn variations thereof. Known
`variations include SCSI l, 2, and 3, Wide SCSI, Fast SCSI,
`Ultra SCSI, Fast Wide SCSI, Ultra Wide SCSI, and so on. It
`may be assumed in this embodiment and throughout this
`speci?cation that disk 100 is adapted for SCSI input/output
`from the host system exemplary of one embodiment. HoW
`ever this should not be construed as a limitation as disk 100,
`With slight modi?cations, may readily be adapted to be rec
`ogniZed using a Integrated Drive Electronic s/Advanced Tech
`nology Attachment (IDE/ATA) interface, an Enhanced Small
`Device Interface (ESDI), a Serial Advanced Technology
`Attachment, SATA), or a Parallel Advanced Technology
`Attachment (PATA) interface. Disk 100 may also be adapted
`to Work With enterprise Fibre Channel data storage netWorks
`and serial attached SCSI (SAS) netWorks. In this particular
`embodiment, disk 100 may be thought of as a SCSI “hot
`sWappable” drive using the appropriate form factor and inter
`faces. With the addition of an onboard disk controller func
`tionality (described beloW) the system may be adapted to an
`expansion bus embodiment.
`In one embodiment, disk 100 is packaged according to
`standard dimensions for disk drives conforming substantially
`to a 4 inch by 1 inch by 5 and 3A inch form factor or other
`standard form factors. Disk 100, in this exemplary embodi
`ment, reports to a host system storage controller illustrated
`herein as host system storage controller 108 as a SCSI loW
`
`35
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`HPE, Exh. 1018, p. 13
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`US 7,464,240 B2
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`thereafter provides the power needed to protect against loss of
`RAM data and to provide component power for ongoing tasks
`being performed on the disk at the time of primary power loss,
`including the task of moving data from RAM into Flash. It is
`important to note herein that disk 100 may be provided as a
`hot swappable storage disk.
`Disk 100 has an onboard controller 104 provided thereto
`and adapted to perform all of the onboard tasks related to data
`management and protection of data written to disk 100 by one
`or more host systems. It is noted herein that disk 100 may be
`adapted in one embodiment as a shared data storage disk
`drive. Controller 1 04, among other tasks, is adapted primarily
`to manage data writes and reads incoming from a host to both
`volatile memory 102 and to non-volatile memory 103a. Con
`troller 104 is provided in an electronics board form factor that
`includes an onboard controller chip (CTL. Chip) 112. CTL
`chip 112 may be a ?eld programmable gate array (FPGA) or
`it may be an application speci?c integrated circuit (ASIC). In
`this embodiment, an FPGA is the preferred implementation
`because of its programmable nature.
`Controller 104 has logical data bus connection to memory
`blocks 102 and 10311 and 10319 in this example and logical bus
`communication (SCSI) through interface 108 to a host system
`controller 109 of a host system. The bus structures are logi
`cally illustrated herein as block arrows labeled “Data”. In this
`exemplary implementation, CTL chip 112 is a FPGA and has
`?rmware (FW) 110 provided thereto and adapted as “control
`ler intelligence” for managing RAM cache and for determin
`ing which memory type to read and write from. FW 110 is a
`compilation of instruction sets that cause the machine (con
`troller) to perform tasks of writing to RAM, reading from
`RAM, moving data from RAM to ?ash, writing directly to
`?ash, and reading from ?ash. FW 112 also contains special
`instructions for managing RAM cache according to certain
`pre-speci?ed conditions, which may exist at any given point
`in time during the operation of disk 100.
`Disk 100 has one or more visual indicators illustrated
`herein as 10711 and 10719 that are connected to CTL chip 112
`via signal lines and that are visible from the outside of disk
`100. In one embodiment, visual indicators 107a and 10719 are
`light emitting diodes (LEDs). LED 107a may indicate on/off
`status of disk 100. LED 1071) may indicate read/write status
`of controller 104.
`Controller 104 makes use of one or more tables to facilitate
`management of data and data tasks with regard to data being
`stored in and written to or read from volatile and non-volatile
`memories 102 and 10311 respectively. In this regard, some
`portion of volatile memory 102 may be reserved within block
`102 to contain one or more software tables. In one embodi
`ment, Local Block Address (LBA) access tables 11111 are
`provided to reside in a reserved portion of volatile memory
`102. Tables 111a may include one table for containing LBAs
`used for writing data to or reading data from volatile memory
`102 and one table for containing LBAs used for writing data
`to and reading data from non-volatile memory 103a and/or
`any other connected cards such as 10319.
`In another embodiment, the LBA table or tables may be
`provided as local tables 111!) accessible to CTL chip 112
`onboard controller 104 using one or more additional RAM
`chips mounted to the controller board and bussed to CTL chip
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`112. In still another embodiment, a predetermined amount of
`non-volatile memory may also be reserved for storing a ?ash
`LBA table. In this case, reserved non-volatile ?ash may be
`provided locally to controller 104 or reserved on each useable
`?ash daughter card installed in disk 100.
`Controller 104 has a unique relationship with volatile
`memory 102 and non-volatile memories 103a and 10319 in
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`that it attempts to utiliZe volatile memory 102 as much as is
`possible for data writing and data reading while isolating
`non-volatile memory from data writes as much as is possible.
`Controller 104 accomplishes memory management and
`access using LBA access tables and updates those tables with
`the most current data storage sates recorded. More detail
`regarding LBA tables and the purposes of those tables will be
`provided later in this speci?cation.
`In general, controller 109 views disk 100 has a single SCSI
`non-volatile disk drive. Write and read requests coming in
`from host controller 109 are carried out by onboard controller
`104 according to unique data management methods that con
`sider available volatile and non-volatile memory on disk 100
`as a hybrid of RAM and Flash for smart data caching and data
`access from cache or Flash and for permanent data storage to
`non-volatile memory at appropriate but, optimally, infrequent
`times.
`Non-volatile memory blocks 103a and 10319 (alternate
`block) are provided in one embodiment, in the form of mul
`tiple high-density Flash chips strategically mounted to a plug
`in daughter card and connected in parallel for data commu
`nication with controller 104. In one embodiment, there is a
`256-bit data path created for Flash communication, however
`128-bit or 64-bit data paths may be used in some embodi
`ments. Volatile memory, in one example, SDRAM DDR-2 is,
`in a preferred embodiment, provided up to a storage capacity
`that rivals the non-volatile data storage capacity of the drive.
`A unique write-balancing technique is provided for reducing
`wear to ?ash memory caused by writing to ?ash. Write bal
`ancing involves designating at least one ?ash unit as a spare
`unit then rotating that unit into service after a number of
`writes to ?ash have occurred and designating a next spare unit
`for the next rotation. More detail on ?ash write balancing will
`be provided later in this speci?cation.
`A host reading and writing to disk 100 sees LBAs as LBAs
`of memory in a single (non-volatile) memory disk. However,
`controller 104 distinguishes between RAM (volatile) LBAs
`and corresponding Flash (non-volatile) LBAs when writing
`and reading data on behalf of the host system. Tables 11111 or
`1111) local to controller 104 may include a Flash table and a
`RAM table viewable only by the local controller (104). Each
`LBA representing a unit of volatile memory corresponds to
`and is cross-referenceable in at least one table to a LBA
`representing a like unit of non-volatile memory.
`The LBA access table for volatile memory incorporates a
`sliding start point and end point that together de?ne a valid
`range of useable volatile memory. When data is moved from
`volatile to non-volatile memory, the start point for that moved
`data referencing an LBA where the data is stored is incre
`mented up in the table to the next LBA in the table. Likewise,
`the end point is incremented to a next LBA entry every time
`data is written to volatile memory. The use of both volatile and
`non-volatile storage in the hybrid solid-state storage disk of
`the present invention is mitigated by controller 104 such that
`data writes to the non-volatile memory are minimized as
`much as is possible, the bulk of which occur only at power
`down of the ho st system at which time all valid data stored in
`volatile memory is moved into non-volatile memory. Addi
`tionally, rotating between designated blocks of non-volatile
`memory based on total writes to that memory further
`enhances the MTBF of the non-volatile memory portion of
`the disk. More about management of volatile and non-volatile
`memory of disk 100 is discussed in enabling detail further
`below.
`FIG. 2 is a block diagram 200 illustrating use of volatile
`memory and non-volatile memory in combination as a single
`hybrid non-volatile memory for storing and accessing data on
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`HPE, Exh. 1018, p. 14
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`a disk analogous to the disk of FIG. 1 according to an embodi
`ment of the present invention. Diagram 200 is logically rep
`resented herein and should be considered exemplary of one
`possible embodiment for managing two or more memories of
`mixed type as a single non-volatile memory space.
`For the purpose of illustration memory 102, which in this
`example, is SDRAM is logically divided into units of memory
`20111. In one embodiment, units 201a each hold 512 bytes of
`data although any suitable unit of measure may be used. Each
`cluster 20111 is represented in a RAM table illustrated herein
`as a RAM table 205 stored in a reserved portion of SDRAM
`207. As discussed above, the reserved portion of RAM may
`be partitioned from SDRAM 102 or it may be separate RAM
`chips mounted to the controller board and accessible to the
`controller chip.
`Non-volatile memory 103, in this case, Flash memory, is
`also logically divided into memory units 2011). Units 2011)
`may be 512 bytes large or of some other block siZe than units
`201a without departing from the spirit and scope of the
`present invention. Each unit 2011) in Flash memory may be
`represented by a LBA that is stored in a Flash table illustrated
`herein as Flash table 206 stored, in this case, in reserved
`SDRAM 207. It is noted herein that in one embodiment, Flash
`table 206 may instead be stored in a reserved portion of Flash
`memory without departing from the spirit and scope of the
`present invention. In the latter case, a reserved portion of
`Flash memory may be partitioned from active Flash blocks, or
`may be provided as a set of Flash chips mounted onboard
`controller 104 described further above.
`Controller 104 described further above is logically repre
`sented in this example by FPGA 202, which includes FW 110
`described above with respect to FIG. 1. In this case FPGA 202
`and loaded FW provides all of the controller function. FPGA
`202 has a data channel (HOST) to a host controller of a host
`system. FPGA 202 also has a data channel to reserved
`SDRAM 207. FPGA 202 has a data channel to Flash memory
`103 through a read/write interface 204 and a data channel to
`SDRAM 102 through a read/write interface 203. One with
`skill in the art will understand that the functions described
`above may be distributed over more than one chip or to a
`combination of chips and a microcontrollers without depart
`ing from the spirit and scope of the present invention.
`Firmware loaded onto FPGA 202 includes an ECC utility,
`logic for managing data stored on the hybrid solid state disk,
`and a cache compacting algorithm for further optimiZing
`isolation of Flash memory 103 from writes during normal
`operation. FPGA 202 contains at least three programmable
`values that are predetermined and are used in conjunction
`with management of RAM LBA table 205. These values are
`a RAM minimum (RAM_MIN) value (a); a (RAM_FULL)
`value (b); and a RAM maximum (RAM_MAX) value (c)
`(optional). The just described values are used by FW loaded
`on FPGA 202 to manage the current capacity of SDRAM 102
`during operation.
`RAM LBA table 205 lists all of the logical LBAs repre
`senting units 20111 in SDRAM 102. Each LBA appears
`sequentially from LBA-1 to LBA-N. FPGA 202 utiliZes at
`least three LBA pointers when consulting RAM LBA table
`205 for determining at least one SDRAM memory range
`logically in the table that will hold valid data and at least one
`buffer Zone where data should not be written except as a last
`resort. For example, table 205 has a RAM start pointer (RAM
`SP) and a RAM end pointer (RAM EP). RAM (SP) points to
`the current beginning LBA of a de?ned range of LBAs, the
`current end of which is pointed to by the RAM (EP). It is
`important to note herein that this range is ?exible in that it
`never equals the total SDRAM memory space in units and
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`that it expands accordingly with writes of new data into
`SDRAM and retracts accordingly when data is compacted or
`if it is moved to Flash memory.
`The exact range of LBAs in SDRAM cache at any given
`point in time during runtime is expressed as the value of RAM
`(EP)-RAM (SP) taken against a reference point such as
`LBA-0 for example. Another pointer may be provided as an
`option within FPGA 202 as described above. A RAM maxi
`mum pointer RAM (MP) may be provided in one embodi
`ment to point to a LBA that is one LBA behind the RAM (SP)
`at any given point in time to determine a buffer Zone. There
`fore, a buffer Zone in RAM may be de?ned as RAM SP-1. The
`RAM (MP) may be one LBA behind the RAM (SP) and is
`incremented each time the RAM (SP) is incremented in the
`table. In this example, RAM (MP) points to LBA-n. It is noted
`herein that each RLBA-1 through n corresponds to a Flash