(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2007/0276995 A1
`Caulkins et al.
`(43) Pub. Date:
`Nov. 29, 2007
`
`US 20070276995A1
`
`(54) HYBRID SOLID STATE DISK DRIVE WITH
`CONTROLLER
`(76) Inventors:
`Jason Caulkins, Redding, CA
`(US); Michael Richard Beyer,
`Redding, CA (US)
`Correspondence Address:
`CENTRAL COAST PATENT AGENCY, INC
`3 HANGAR WAY SUITED
`WATSONVILLE CA 95.076
`9
`11/439,619
`
`(21) Appl. No.:
`
`(22) Filed:
`
`May 23, 2006
`
`Publication Classification
`
`(51) Int. Cl.
`G06F 3/00
`
`(2006.01)
`
`(52) U.S. Cl. ....................................................... 711/113
`
`ABSTRACT
`(57)
`A solid-state disk drive includes a first portion of solid-state
`memory of a volatile nature, a second portion of Solid-state
`memory of a non-volatile nature, a controller for managing
`the memories, and a power Subsystem for protecting data in
`volatile memory in the event of loss of power.
`
`401
`
`402
`
`403
`
`404
`
`405
`
`400
`
`-
`
`H-SYS
`Boot
`
`Recognize
`Drive
`
`
`
`
`
`Controller
`Initialize
`Drive
`
`411
`
`
`
`
`
`Invalidate Old FLBA
`in RAM table: add new
`s
`FLBA to RAM table
`
`
`
`
`
`
`
`Update Flash table
`with new RLBA
`
`SYS
`READY
`
`407
`CTL Lookup
`LBA in
`Flash Table
`
`408
`
`409
`
`Data In
`RAM?
`
`NO Update RAM
`Table with
`the FLBA entry
`
`410
`
`Update Flash
`Table with
`RLBA entry
`
`HPE, Exh. 1021, p. 1
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 1 of 10
`
`US 2007/0276995 A1
`
`e
`
`
`
`102 Solid State Disk
`Volatile Memory
`111a :
`
`-1
`LED 2
`Data
`112
`“AcceSS Tables; Controller
`- 107b
`104
`
`Host System Storage Controller
`
`Fig. 1
`
`HPE, Exh. 1021, p. 2
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 2 of 10
`
`US 2007/0276995 A1
`
`
`
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`HPE, Exh. 1021, p. 3
`
`HPE, Exh. 1021, p. 3
`
`
`
`
`
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 3 of 10
`
`US 2007/0276995 A1
`
`
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`HPE, Exh. 1021, p. 4
`
`

`

`Patent Application Publication
`
`US 2007/0276995 A1
`
`
`
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`HPE, Exh. 1021, p. 5
`
`

`

`Patent Application Publication
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`
`HPE, Exh. 1021, p. 6
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 6 of 10
`
`US 2007/0276995 A1
`
`009
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`909
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`HPE, Exh. 1021, p. 7
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 7 of 10
`
`US 2007/0276995 A1
`
`700
`
`701
`
`Advance (SP)
`in RAM table
`
`702
`
`VALID
`
`704
`
`NO
`
`707
`
`708
`
`
`
`LBA in
`Valid Range?
`
`YES
`
`Select
`Newest
`RLBA
`
`
`
`
`
`
`
`Move Data to
`Selected LBA
`
`INVALID
`
`703
`
`
`
`Advance (SP)
`to next LBA
`
`Move Data to
`Flash
`
`
`
`
`
`705
`
`706
`
`Fig. 7
`
`HPE, Exh. 1021, p. 8
`
`

`

`Patent Application Publication Nov. 29, 2007 Sheet 8 of 10
`
`US 2007/0276995 A1
`
`/ 800
`
`Move data
`to Flash
`
`Increment
`Counter
`
`Compare Total
`to Preset i
`Writes
`
`801
`
`802
`
`
`
`803
`
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`
`Isolate Block
`Activate
`Spare Block
`
`
`
`Increment
`Block Rotation
`Counter
`
`Fig. 8
`
`HPE, Exh. 1021, p. 9
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 9 of 10
`
`US 2007/0276995 A1
`
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`HPE, Exh. 1021, p. 10
`
`

`

`Patent Application Publication
`
`Nov. 29, 2007 Sheet 10 of 10 US 2007/0276995 A1
`
`
`
`1004
`
`002 Y
`
`X
`
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`S aC
`
`RAM LBA
`Table
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`
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`
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`FLBA-2
`FLBA-3
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`Table
`
`Fig. 10
`
`HPE, Exh. 1021, p. 11
`
`

`

`US 2007/0276995 A1
`
`Nov. 29, 2007
`
`HYBRD SOLID STATE DISK DRIVE WITH
`CONTROLLER
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`0001 NA
`
`BACKGROUND OF THE INVENTION
`0002 1. Field of the Invention
`0003. The present invention is in the field of computer
`data storage devices and pertains particularly to a system
`including methods and apparatus for high-speed data storage
`and access from a computing device.
`0004 2. Discussion of the State of the Art
`0005. In the field of data storage, non-volatile mechanical
`disk drives have long been relied upon for non-volatile short
`and long-term data storage. More recently, Solid-state non
`Volatile memory has been implemented for data storage
`needs, especially in Small portable electronic computing
`devices such as cellular telephones, video cameras and the
`like. Volatile memory is a solid-state memory typically only
`used as a high-speed temporary memory Such as random
`access memory (RAM) of which there are many variations
`known. Common versions of RAM include Dynamic Ran
`dom. Access Memory (DRAM) and Static Random Access
`Memory (SRAM). Flash memory is a solid-state high-speed
`data storage Solution used primarily in handheld devices or
`Universal Serial Bus (USB) peripheral devices. Flash
`memory provides a non-volatile memory for storing data
`with read speeds approaching that of RAM. However,
`writing to flash memory is comparatively much slower than
`RAM.
`0006 Flash memory has practical uses in cell phones,
`Video cameras, plug-in cards and USB memory devices and
`the like. Disadvantages of using flash as permanent storage
`in high input/output systems, such as transaction servers for
`example, include the fact that a number of writes performed
`on the memory defines the life or Mean Time before Failure
`(MTBF) of a flash memory chip. Another disadvantage is
`that access to data, while random for reads and writes is still
`slower than RAM.
`0007. It has occurred to the inventor that there is a need
`for faster data management speeds in the computing industry
`in general and in particular in the area of data intensive
`servers and other business machines. Further, it is desired to
`provide a pure solid-state disk drive that may be imple
`mented as a normal hard drive package that is recognized
`and read by a host system as a single non-volatile storage
`disk, which is Swappable with existing mechanical hard disk
`drives used in many computing systems including desktop
`computers, data servers, and in mass storage systems using
`multiple disks deployed in custom or standard array. A
`system and method for implementing the same would pro
`vide much greater data access speeds for computing systems
`in general.
`
`SUMMARY OF THE INVENTION
`0008 According to an embodiment of the present inven
`tion, a solid-state disk drive is provided and includes a first
`portion of Solid-state memory of a volatile nature, a second
`portion of Solid-state memory of a non-volatile nature, a
`controller for managing the memories, and a power Sub
`system for protecting data in Volatile memory in the event of
`
`loss of power. In one embodiment, the solid-state disk drive
`is adapted for use with SCSI protocol or variations thereof.
`In one embodiment, the solid-state disk drive is adapted for
`use with integrated drive electronics protocol or variations
`thereof. In another embodiment, the solid-state disk drive is
`adapted for use with serial advanced technology attachment
`(SATA) or parallel advanced technology attachment (PATA)
`protocols or variations thereof. In still another embodiment,
`the solid-state disk drive is adapted for use with Fibre
`Channel network protocols or variations thereof.
`0009. In one embodiment, the first portion of memory is
`random access memory (RAM) or a variation thereof and
`the second portion of memory is Flash memory. In one
`embodiment, the second portion of memory is one of
`Magnetoresistive Random Access Memory, Ferroelectric
`Random Access Memory, or Nano Random Access Memory.
`In one embodiment, the controller has an input and output
`port to the first memory portion, the second memory portion,
`to a host system, and to the power Subsystem.
`0010. In one embodiment, the controller is a controller
`board with at least one field programmable gate array
`(FPGA) mounted thereon. In another embodiment, the con
`troller is a controller board with at least one application
`specific integrated circuit (ASIC) mounted thereon. In one
`embodiment, the power Subsystem contains a Switch capable
`of detecting loss of power from a host system and Switching
`to battery power.
`0011. According to another aspect of the present inven
`tion in a solid-state disk having a first portion of Solid-state
`memory of a Volatile nature and a second portion of Solid
`state memory of a non-volatile nature, a controller for
`managing the memory portions as a single non-volatile
`memory is provided. The controller includes at least one
`integrated circuit Supporting one or more sets of machine
`readable instructions, a first data port and buffer circuitry for
`bi-directional communication of data between the controller
`and a host system, a second data port and buffer circuitry for
`bi-directional communication of data between the controller
`and the volatile memory, and a third data port and buffer
`circuitry for bi-directional communication of data between
`the controller and the non-volatile memory.
`0012. In one embodiment, the integrated circuit is one of
`an FPGA or an ASIC. In one embodiment, the controller is
`configured for SCSI or a variation thereof. In another
`embodiment, the controller is configured for IDE or a
`variation thereof. In a preferred embodiment, the integrated
`circuit is an FPGA and the one or more sets of machine
`readable instructions are flashed onto a programmable
`memory in the FPGA.
`0013. According to one embodiment, the controller fur
`ther includes one or more onboard memory chips of a
`volatile nature, and a fourth data port and circuitry for
`bi-directional communication of data with the onboard
`memory. In this aspect, the onboard memory is RAM or a
`variation thereof.
`0014. According to one embodiment, the controller fur
`ther includes a data path to a power Subsystem for receiving
`notification of loss of power from the host. In one embodi
`ment, the memories are addressed using a logical block
`addressing system and the controller is integral to the
`motherboard of the disk drive. In this embodiment, sequen
`tial tables for each memory space are maintained in the
`
`HPE, Exh. 1021, p. 12
`
`

`

`US 2007/0276995 A1
`
`Nov. 29, 2007
`
`onboard memory and are cross-linked per entry to facilitate
`direct memory address mapping between volatile and non
`Volatile memories.
`0.015. In still another embodiment, the controller further
`includes one or more onboard memory chips of a non
`Volatile nature, and a data port and circuitry for bi-direc
`tional communication of data with a reserved portion of
`non-volatile memory to re-construct data state and maintain
`counters at startup.
`
`BRIEF DESCRIPTION OF THE DRAWING
`FIGURES
`0016 FIG. 1 is a block diagram of a high-speed solid
`state non-volatile disk according to an embodiment of the
`present invention.
`0017 FIG. 2 is a block diagram illustrating use of volatile
`and non-volatile memory in combination for storing and
`accessing data on a disk analogous to the disk of FIG. 1
`according to an embodiment of the present invention.
`0018 FIG. 3 is a block diagram illustrating a disk con
`troller for managing disk function according to an embodi
`ment of the present invention.
`0019 FIG. 4 is a flow chart illustrating acts for managing
`writes to a combination RAM and Flash disk according to an
`embodiment of the present invention.
`0020 FIG. 5 is a flow chart illustrating acts for managing
`data in RAM according to an embodiment of the present
`invention.
`0021
`FIG. 6 is a flow chart illustrating acts for protecting
`against RAM data overflow according to an embodiment of
`the present invention.
`0022 FIG. 7 is a flow chart illustrating acts for optimiz
`ing RAM space according to an embodiment of the present
`invention.
`0023 FIG. 8 is a flow chart illustrating acts for write
`balancing Flash memory according to an embodiment of the
`present invention.
`0024 FIG. 9 is a process flow chart illustrating acts for
`reading data from a solid-state non-volatile disk according to
`an embodiment of the present invention.
`0025 FIG. 10 is a logical memory map illustrating map
`ping of memory space according to an embodiment of the
`present invention.
`
`DETAILED DESCRIPTION
`0026 FIG. 1 is a block diagram of a hybrid solid-state
`storage device 100 according to an embodiment of the
`present invention. Device 100 is adapted as a solid-state
`storage disk drive that may be recognized by any standard
`operating system as a standard data storage disk. Device 100
`includes a host interface 108, which may be a Small Com
`puter System Interface (SCSI) or one of many known
`variations thereof. Known variations include SCSI 1, 2, and
`3, Wide SCSI, Fast SCSI, Ultra SCSI, Fast Wide SCSI, Ultra
`Wide SCSI, and so on. It may be assumed in this embodi
`ment and throughout this specification that disk 100 is
`adapted for SCSI input/output from the host system exem
`plary of one embodiment. However this should not be
`construed as a limitation as disk 100, with slight modifica
`tions, may readily be adapted to be recognized using a
`Integrated Drive Electronics/Advanced Technology Attach
`ment (IDE/ATA) interface, an Enhanced Small Device Inter
`face (ESDI), a Serial Advanced Technology Attachment,
`
`SATA), or a Parallel Advanced Technology Attachment
`(PATA) interface. Disk 100 may also be adapted to work
`with enterprise Fibre Channel data storage networks and
`serial attached SCSI (SAS) networks. In this particular
`embodiment, disk 100 may be thought of as a SCSI "hot
`Swappable' drive using the appropriate form factor and
`interfaces. With the addition of an onboard disk controller
`functionality (described below) the system may be adapted
`to an expansion bus embodiment.
`0027. In one embodiment, disk 100 is packaged accord
`ing to standard dimensions for disk drives conforming
`substantially to a 4 inch by 1 inch by 5 and 34 inch form
`factor or other standard form factors. Disk 100, in this
`exemplary embodiment, reports to a host system storage
`controller illustrated herein as host system storage controller
`108 as a SCSI low voltage differential (LVD) U320 disk. In
`this exemplary embodiment, interface 108 is a standard
`SCSI SCA 80-pin connector, however one with skill in the
`art will recognize that other connectors might be used
`depending on SCSI version.
`(0028. Disk 100 includes a volatile memory 102. Memory
`102 may, in one embodiment, be a version of RAM known
`as synchronous dynamic RAM or SDRAM. In this embodi
`ment SDRAM 102 may include an enhancement known as
`double data rate (DDR) which transfers data both on the
`rising and falling edge of the computer processing unit
`(CPU) clock unit. Other types of RAM are known in the art
`and are available to the inventor and might be provided to
`disk 100 without departing from the spirit and scope of the
`present invention. Volatile memory 102 may hold up to 8
`gigabytes (GB) or more of data including an extra GB
`reserved for error correcting code (ECC) data. One with skill
`in the art will recognize that volatile memory 102 may be
`more than or less than 8 GB without departing from the spirit
`and scope of the present invention.
`0029 Disk 100 includes at least one non-volatile memory
`103a and may include additional non-volatile memories
`such as a non-volatile memory 103b illustrated herein as an
`alternate memory block, which may be accessed in place of
`or in addition to block 103a. In one embodiment, memory
`103a is Flash memory. In this embodiment, memory 103b is
`also Flash memory. Flash memory blocks 103a and 103b
`may be one of or a combination of NOR Flash or NAND
`Flash without departing from the spirit and scope of the
`present invention. In one preferred embodiment, NAND
`Flash is used because of a higher density of data storage
`capacity. However, the use of NAND or NOR Flash should
`not be construed as a limitation as future implementations of
`non-volatile memory may also be contemplated and applied
`without departing from the spirit and scope of the present
`invention. One example is Magnetoresistive Random Access
`Memory (MRAM), which is currently being developed.
`Another example is Ferroelectric Random Access Memory
`(FRAM). Still another example of non-volatile RAM
`(NVRAM) is Nano Random Access Memory (NRAM).
`0030. In one embodiment, non-volatile memory 103a is
`provided as a plug-in memory card, Sometimes referred to in
`this specification as a daughter card. As such, memory 103b
`may be thought of as an optional daughter card. There may
`be more than two non-volatile memories plugged into disk
`100 without departing from the spirit and scope of the
`present invention. For purpose of discussion only, the inven
`tor provides up to 3 Flash cards or daughter cards that may
`be shipped with disk 100, each card written to in isolation
`
`HPE, Exh. 1021, p. 13
`
`

`

`US 2007/0276995 A1
`
`Nov. 29, 2007
`
`from the other cards according to a unique “write balancing
`technique that will be described later in this specification. In
`a preferred implementation a minimum of 8 GB of non
`volatile memory is provided, but up to 128 GB of non
`Volatile memory may be conveniently provided on a single
`disk 100 within the standard form factor boundaries.
`0031
`Disk 100 has an onboard power supply or sub
`system 105 provided thereto and adapted in one embodi
`ment, to receive direct current (DC) power from the host
`system. This is illustrated herein by a logical arrow labeled
`“Host DC” from controller 109 to power supply 105. Disk
`100 also includes an onboard chargeable power source 106.
`Power source 106 may be a rechargeable cell or battery or
`a bank of those arrayed and adapted to provide backup
`power to disk 100 in the event that power from a connected
`host system is interrupted. Power supply 105 has connection
`to power source 106 via at least a signal port if not a logical
`bus structure labeled herein, data. Power source 106 auto
`matically detects whenever there is an interruption or lack of
`power coming in from the host and thereafter provides the
`power needed to protect against loss of RAM data and to
`provide component power for ongoing tasks being per
`formed on the disk at the time of primary power loss,
`including the task of moving data from RAM into Flash. It
`is important to note herein that disk 100 may be provided as
`a hot swappable storage disk.
`0032. Disk 100 has an onboard controller 104 provided
`thereto and adapted to perform all of the onboard tasks
`related to data management and protection of data written to
`disk 100 by one or more host systems. It is noted herein that
`disk 100 may be adapted in one embodiment as a shared data
`storage disk drive. Controller 104, among other tasks, is
`adapted primarily to manage data writes and reads incoming
`from a host to both volatile memory 102 and to non-volatile
`memory 103a. Controller 104 is provided in an electronics
`board form factor that includes an onboard controller chip
`(CTL. Chip) 112. CTL chip 112 may be a field program
`mable gate array (FPGA) or it may be an application specific
`integrated circuit (ASIC). In this embodiment, an FPGA is
`the preferred implementation because of its programmable
`nature.
`0033 Controller 104 has logical data bus connection to
`memory blocks 102 and 103a and 103b in this example and
`logical bus communication (SCSI) through interface 108 to
`a host system controller 109 of a host system. The bus
`structures are logically illustrated herein as block arrows
`labeled “Data'. In this exemplary implementation, CTL chip
`112 is a FPGA and has firmware (FW) 110 provided thereto
`and adapted as “controller intelligence' for managing RAM
`cache and for determining which memory type to read and
`write from. FW 110 is a compilation of instruction sets that
`cause the machine (controller) to perform tasks of writing to
`RAM, reading from RAM, moving data from RAM to flash,
`writing directly to flash, and reading from flash. FW 112 also
`contains special instructions for managing RAM cache
`according to certain pre-specified conditions, which may
`exist at any given point in time during the operation of disk
`1OO.
`0034 Disk 100 has one or more visual indicators illus
`trated herein as 107a and 107b that are connected to CTL
`chip 112 via signal lines and that are visible from the outside
`of disk 100. In one embodiment, visual indicators 107a and
`107b are light emitting diodes (LEDs). LED 107a may
`
`indicate on/off status of disk 100. LED 107b may indicate
`read/write status of controller 104.
`0035 Controller 104 makes use of one or more tables to
`facilitate management of data and data tasks with regard to
`data being stored in and written to or read from volatile and
`non-volatile memories 102 and 103a respectively. In this
`regard, some portion of volatile memory 102 may be
`reserved within block 102 to contain one or more software
`tables. In one embodiment, Local Block Address (LBA)
`access tables 111a are provided to reside in a reserved
`portion of volatile memory 102. Tables 111a may include
`one table for containing LBAS used for writing data to or
`reading data from volatile memory 102 and one table for
`containing LBAS used for writing data to and reading data
`from non-volatile memory 103a and/or any other connected
`cards such as 103b.
`0036. In another embodiment, the LBA table or tables
`may be provided as local tables 111b accessible to CTL chip
`112 onboard controller 104 using one or more additional
`RAM chips mounted to the controller board and bussed to
`CTL chip 112. In still another embodiment, a predetermined
`amount of non-volatile memory may also be reserved for
`storing a flash LBA table. In this case, reserved non-volatile
`flash may be provided locally to controller 104 or reserved
`on each useable flash daughter card installed in disk 100.
`0037 Controller 104 has a unique relationship with vola
`tile memory 102 and non-volatile memories 103a and 103b
`in that it attempts to utilize volatile memory 102 as much as
`is possible for data writing and data reading while isolating
`non-volatile memory from data writes as much as is pos
`sible. Controller 104 accomplishes memory management
`and access using LBA access tables and updates those tables
`with the most current data storage sates recorded. More
`detail regarding LBA tables and the purposes of those tables
`will be provided later in this specification.
`0038. In general, controller 109 views disk 100 has a
`single SCSI non-volatile disk drive. Write and read requests
`coming in from host controller 109 are carried out by
`onboard controller 104 according to unique data manage
`ment methods that consider available volatile and non
`volatile memory on disk 100 as a hybrid of RAM and Flash
`for Smart data caching and data access from cache or Flash
`and for permanent data storage to non-volatile memory at
`appropriate but, optimally, infrequent times.
`0039. Non-volatile memory blocks 103a and 103b (alter
`nate block) are provided in one embodiment, in the form of
`multiple high-density Flash chips strategically mounted to a
`plug-in daughter card and connected in parallel for data
`communication with controller 104. In one embodiment,
`there is a 256-bit data path created for Flash communication,
`however 128-bit or 64-bit data paths may be used in some
`embodiments. Volatile memory, in one example, SDRAM
`DDR-2 is, in a preferred embodiment, provided up to a
`storage capacity that rivals the non-volatile data storage
`capacity of the drive. A unique write-balancing technique is
`provided for reducing wear to flash memory caused by
`writing to flash. Write balancing involves designating at
`least one flash unit as a spare unit then rotating that unit into
`service after a number of writes to flash have occurred and
`designating a next spare unit for the next rotation. More
`detail on flash write balancing will be provided later in this
`specification.
`0040. A host reading and writing to disk 100 sees LBAs
`as LBAS of memory in a single (non-volatile) memory disk.
`
`HPE, Exh. 1021, p. 14
`
`

`

`US 2007/0276995 A1
`
`Nov. 29, 2007
`
`However, controller 104 distinguishes between RAM (vola
`tile) LBAs and corresponding Flash (non-volatile) LBAs
`when writing and reading data on behalf of the host system.
`Tables 111a or 111b local to controller 104 may include a
`Flash table and a RAM table viewable only by the local
`controller (104). Each LBA representing a unit of volatile
`memory corresponds to and is cross-referenceable in at least
`one table to a LBA representing a like unit of non-volatile
`memory.
`0041. The LBA access table for volatile memory incor
`porates a sliding start point and end point that together define
`a valid range of useable volatile memory. When data is
`moved from volatile to non-volatile memory, the start point
`for that moved data referencing an LBA where the data is
`stored is incremented up in the table to the next LBA in the
`table. Likewise, the end point is incremented to a next LBA
`entry every time data is written to volatile memory. The use
`of both volatile and non-volatile storage in the hybrid
`Solid-state storage disk of the present invention is mitigated
`by controller 104 such that data writes to the non-volatile
`memory are minimized as much as is possible, the bulk of
`which occur only at power down of the host system at which
`time all valid data stored in volatile memory is moved into
`non-volatile memory. Additionally, rotating between desig
`nated blocks of non-volatile memory based on total writes to
`that memory further enhances the MTBF of the non-volatile
`memory portion of the disk. More about management of
`volatile and non-volatile memory of disk 100 is discussed in
`enabling detail further below.
`0042 FIG. 2 is a block diagram 200 illustrating use of
`Volatile memory and non-volatile memory in combination as
`a single hybrid non-volatile memory for storing and access
`ing data on a disk analogous to the disk of FIG. 1 according
`to an embodiment of the present invention. Diagram 200 is
`logically represented herein and should be considered exem
`plary of one possible embodiment for managing two or more
`memories of mixed type as a single non-volatile memory
`Space.
`0043. For the purpose of illustration memory 102, which
`in this example, is SDRAM is logically divided into units of
`memory 201a. In one embodiment, units 201a each hold 512
`bytes of data although any Suitable unit of measure may be
`used. Each cluster 201a is represented in a RAM table
`illustrated herein as a RAM table 205 stored in a reserved
`portion of SDRAM 207. As discussed above, the reserved
`portion of RAM may be partitioned from SDRAM 102 or it
`may be separate RAM chips mounted to the controller board
`and accessible to the controller chip.
`0044) Non-volatile memory 103, in this case, Flash
`memory, is also logically divided into memory units 201b.
`Units 201b may be 512 bytes large or of some other block
`size than units 201a without departing from the spirit and
`scope of the present invention. Each unit 201b in Flash
`memory may be represented by a LBA that is stored in a
`Flash table illustrated herein as Flash table 206 stored, in this
`case, in reserved SDRAM 207. It is noted herein that in one
`embodiment, Flash table 206 may instead be stored in a
`reserved portion of Flash memory without departing from
`the spirit and scope of the present invention. In the latter
`case, a reserved portion of Flash memory may be partitioned
`from active Flash blocks, or may be provided as a set of
`Flash chips mounted onboard controller 104 described fur
`ther above.
`
`0045 Controller 104 described further above is logically
`represented in this example by FPGA 202, which includes
`FW 110 described above with respect to FIG. 1. In this case
`FPGA 202 and loaded FW provides all of the controller
`function. FPGA 202 has a data channel (HOST) to a host
`controller of a host system. FPGA 202 also has a data
`channel to reserved SDRAM 207. FPGA 202 has a data
`channel to Flash memory 103 through a read/write interface
`204 and a data channel to SDRAM 102 through a read/write
`interface 203. One with skill in the art will understand that
`the functions described above may be distributed over more
`than one chip or to a combination of chips and a microcon
`trollers without departing from the spirit and scope of the
`present invention.
`0046 Firmware loaded onto FPGA 202 includes an ECC
`utility, logic for managing data stored on the hybrid solid
`state disk, and a cache compacting algorithm for further
`optimizing isolation of Flash memory 103 from writes
`during normal operation. FPGA 202 contains at least three
`programmable values that are predetermined and are used in
`conjunction with management of RAM LBA table 205.
`These values are a RAM minimum (RAM MIN) value (a):
`a (RAM FULL) value (b); and a RAM maximum (RAM
`MAX) value (c) (optional). The just described values are
`used by FW loaded on FPGA 202 to manage the current
`capacity of SDRAM 102 during operation.
`0047 RAM LBA table 205 lists all of the logical LBAs
`representing units 201a in SDRAM 102. Each LBA appears
`sequentially from LBA-1 to LBA-N. FPGA 202 utilizes at
`least three LBA pointers when consulting RAM LBA table
`205 for determining at least one SDRAM memory range
`logically in the table that will hold valid data and at least one
`buffer Zone where data should not be written except as a last
`resort. For example, table 205 has a RAM start pointer
`(RAMSP) and a RAM end pointer (RAM EP). RAM (SP)
`points to the current beginning LBA of a defined range of
`LBAs, the current end of which is pointed to by the RAM
`(EP). It is important to note herein that this range is flexible
`in that it never equals the total SDRAM memory space in
`units and that it expands accordingly with writes of new data
`into SDRAM and retracts accordingly when data is com
`pacted or if it is moved to Flash memory.
`0048. The exact range of LBAs in SDRAM cache at any
`given point in time during runtime is expressed as the value
`of RAM (EP)-RAM (SP) taken against a reference point
`such as LBA-0 for example. Another pointer may be pro
`vided as an option within FPGA 202 as described above. A
`RAM maximum pointer RAM (MP) may be provided in one
`embodiment to point to a LBA that is one LBA behind the
`RAM (SP) at any given point in time to determine a buffer
`Zone. Therefore, a buffer Zone in RAM may be defined as
`RAM SP-1. The RAM (MP) may be one LBA behind the
`RAM (SP) and is incremented each time the RAM (SP) is
`incremented in the table. In this example, RAM (MP) points
`to LBA-n. It is noted herein that each RLBA-1 through in
`corresponds to a Flash LBA (FLBA), the aggregation illus
`trated herein as FLBA-1 through FLBA-n in Flash table 206.
`0049. Therefore, each time FPGA 202 consults before
`writing or reading data, it first accesses Flash LBA table 206
`to determine state of that particular LBA. The state deter
`mined is whether there is data for that address in RAM or
`not. All data writes to the disk are first written to SDRAM
`102 at a LBA in RAM evidenced by the current position of
`the RAM (EP) at the time of write. More detail about data
`
`HPE, Exh. 1021, p. 15
`
`

`

`US 2007/0276995 A1
`
`Nov. 29, 2007
`
`management through manipulation of tables 205 and 206 is
`provided later in this specification.
`0050 SDRAM 102 is illustrated in this example to have
`data stored therein in memory units 201a. Valid data in
`SDRAM 102 or data that cannot be overwritten is repre
`sented by Os and older data or data that may be overwritten
`or aged out of validity in represented by Xs. In actual
`practice, the data is sequentially written into SDRAM 102.
`Data from SDRAM 102 that has been moved to Flash MEM
`103 is represented by Zs and is illustrated alrea