`

`

`

`Case4:09-cv-05718-SBA Document48 Filed07/16/10 Page29 of 29
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`enlightenment as to the meaning of a claim term." Phillips v. AWH Corp., 415 F.3d 1303, 1314
`
`(Fed. Cir. 2005). "[T]he presence of a dependent claim that adds a particular limitation gives rise
`
`to a presumption that the limitation in question is not present in the independent claim." Id. at
`
`1314-1315 ( citations omitted). Claim 20 depends from claim 18 and recites that "the command
`
`signal is transmitted to the two ranks of the first number of ranks concurrently." The '912 Patent
`
`at 35: 1-3 (Hansen Deel., Exh. A) ( emphasis added). Google's construction of "at a time" as
`
`7 meaning "at the same time" would render "concurrently" in claim 20 superfluous. By definition,
`
`8
`
`9
`
`10
`
`if a command signal is transmitted to two ranks concurrently it is transmitted to them "at the same
`
`time." See Accumed LLC v. Stryker Corp., 483 F.3d 800, 806 (Fed. Cir. 2007) (refusing to
`
`construe "curved" to mean "nonangular continuous bend" because "such a restrictive reading
`
`11 would render claims 1 and 13 identical in scope"). Accordingly, the Court should reject Google's
`
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`25
`26
`27
`28
`
`construction and decline to construe "at a time."
`
`CONCLUSION
`
`For the reasons provided above, the Court should adopt Netlist's claim constructions in
`
`their entirety.
`
`DATED: July 16, 2010
`
`LEE TRAN & LIANGAPLC
`
`By Isl Steven R. Hansen
`
`Steven R. Hansen
`Attorneys for Plaintiff
`NETLIST, INC.
`
`-25-
`CASE NO. CV-09-05718 SBA
`NETLIST'S OPENING CLAIM CONSTRUCTION BRIEF
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2836
`
`

`

`Reexamination Control No.: 95/000,578
`Attorney Docket No. 17730-3
`Supplemental Information Disclosure Statement
`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Inter Partes Reexamination of:
`
`Art Unit: 3992
`
`Examiner: Woo H. Choi
`
`U.S. Patent No. 7,619,912
`Inventors: Bhakta, Jayesh R. et al.
`Filed: September 27, 2007
`Issued: November 17, 2009
`Title: lvfem01y Afodule Decoder
`
`Reexamination Control No. 95/000,578
`Filed: October 20, 2010
`Attorney Docket No.: 17730-3
`
`Mail Stop Inter Partes Reexam
`Central Reexamination Unit
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-145 0
`
`SUPPLEMENTAL INFORMATION DISCLOSURE STATEMENT
`
`Dear Sir:
`
`Third Party Requestor, SMART Modular Technologies (WWH), Inc., submits this
`
`Supplemental Information Disclosure Statement, under 37 C.F.R. § 1.98(a)(l) to further the
`
`information concerning this proceedings involving the U.S. Patent No. 7,619,912 and relies on
`
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`
`Third Party Requestor believes that no fee is required to file this supplemental IDS.
`
`However, if the Patent Office determines that a fee is required, please charge any such fees to
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`Deposit Account No. 15-0665.
`
`1
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2837
`
`

`

`Reexamination Control No.: 95/000,578
`Attorney Docket No. 17730-3
`Supplemental Information Disclosure Statement
`
`Dated: August 29, 2011
`
`Respectfully Submitted,
`
`/ Michael F. Heafey /
`
`Michael F. Heafey
`Reg. No. 38,178
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`(650) 614-7400
`
`Attorney for Smart Modular Technologies
`(WWH), Inc.
`
`CS_ WEST:261312095.1
`
`2
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2838
`
`

`

`Please type a plus sign(+) in this box 000
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`PTO/SB/08A (10-96)
`Approved for use through 10/31/99. 0MB 0651-0031
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`95/000,578
`7,619,912
`October 11, 2010
`Jayesh R. Bhakta
`3992
`CHOI, WOO H
`8810
`17730-3
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`Examiner
`Initials
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`Cite No. 1
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`Examiner
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`VOGT, P., "Fully Buffered DIMM (FB-DIMM) Server Memory Architecture:
`Capacity, Perfonnance, Reliability and
`Longevity", Intel
`Developer Formn,
`2/18/2004, 33 pgs.
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`Examiner
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`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2839
`
`

`

`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Inter Partes Reexamination of:
`
`Art Unit: 3992
`
`Examiner: Woo H. Choi
`
`U.S. Patent No. 7,619,912
`Inventors: Bhakta, Jayesh R. et al.
`Filed: September 27, 2007
`Issued: November 17, 2009
`Title: ,Memory 1\dodule Decoder
`
`Reexamination Control No. 95/000,578
`Filed: October 20, 2010
`Attorney Docket No.: 17730-3
`
`Mail Stop Inter Partes Reexam
`Central Reexamination Unit
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`CERTIFICATE OF SERVICE
`
`I, Susan Principe, declare as follows:
`
`I am employed with the law firm of Orrick, Herrington & Sutcliffe LLP, whose
`
`address is 1000 Marsh Road, Menlo Park, CA 94025. I am over the age of eighteen
`
`years and not a party to this action.
`
`On August 29, 2011, I caused to be served the following document(s):
`
`1. Third Party Requestor's Comments to Patent Owner's Response of July 5, 2011
`and the Office's Decision Granting Petition to Waive Page Limit of July 29,
`201 lUnder 37 C.F.R. § 1.947;
`
`2. Supplemental Information Disclosure Statement, Form SB08a Under
`37 C.F.R. 1.98(a)(l) and attached Exhibit PA-H.
`
`3. Table of Exhibits and attached Exhibits PAT-El, CC-I, OTH-H, OTH-I, and
`OTH-J.; and
`
`4. Declaration of Nader Bagherzadeh Under 37 C.F.R. 1.132 and MPEP § 2618(II)
`
`in this action by causing to be delivered true copies thereof to the following interested
`
`1
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2840
`
`

`

`

`

`Electronic Patent Application Fee Transmittal
`
`Application Number:
`
`Filing Date:
`
`95000578
`
`20-0ct-201 O
`
`Title of Invention:
`
`MEMORY MODULE DECODER
`
`First Named Inventor/Applicant Name:
`
`7619912
`
`Filer:
`
`Dana M. Zottola/Susan Principe
`
`Attorney Docket Number:
`
`17730-3
`
`Filed as Large Entity
`
`inter partes reexam Filing Fees
`
`Description
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`Fee Code
`
`Quantity
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`Amount
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`Sub-Total in
`USO($)
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`Basic Filing:
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`Claims:
`
`Miscellaneous-Filing:
`
`Petition:
`
`Petition fee- 37 CFR 1.17(f) (Group I)
`
`1462
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`1
`
`400
`
`400
`
`Patent-Appeals-and-Interference:
`
`Post-Allowance-and-Post-Issuance:
`
`Extension-of-Time:
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2842
`
`

`

`Description
`
`Fee Code
`
`Quantity
`
`Amount
`
`Sub-Total in
`USO($)
`
`Miscellaneous:
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`400
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2843
`
`

`

`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`10836629
`
`95000578
`
`International Application Number:
`
`Confirmation Number:
`
`8810
`
`Title of Invention:
`
`MEMORY MODULE DECODER
`
`First Named Inventor/Applicant Name:
`
`7619912
`
`Customer Number:
`
`20995
`
`Filer:
`
`Dana M. Zottola/Susan Principe
`
`Filer Authorized By:
`
`Dana M. Zottola
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`Attorney Docket Number:
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`17730-3
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`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2844
`
`

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`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2845
`
`

`

`9
`
`Reexam - Affidavit/Deel/Exhibit Filed by
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`009_((1.pdf
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2846
`
`

`

`Warnings:
`
`Information:
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`Total Files Size (in bytes)~
`
`62016428
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2847
`
`

`

`

`

`Bruce S. Itchkawitz
`KNOBBE MARTENS OLSON & BEAR LLP
`2040 Main Street
`Fourteenth Floor
`Irvine, CA 92614
`
`Adrian M. Pruetz, Esq.
`Erica J. Pruetz, Esq.
`PRUETZ LAW GROUP LLP
`200 N. Sepulveda Blvd.
`Suite 1525
`El Segundo, CA 90245
`
`Enoch H. Liang, Esq.
`Steven R. Hansen, Esq.
`LEE TRAN AND LIANG APLC
`601 S. Figueroa St.
`Suite 4025
`Los Angeles, CA 90017
`
`The Patent Office is hereby authorized to charge any fees or to credit any overpayments
`
`to Deposit Account No. 15-0665.
`
`Dated: August 29, 2011
`
`Respectfully Submitted,
`
`/ Michael F. Heafey /
`
`Michael F. Heafey
`Reg. No. 38,178
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`(650) 614-7400
`
`Attorney for Smart Modular Technologies
`(WWH), Inc.
`
`CS_ WEST:261312095.1
`
`2
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2849
`
`

`

`IN TH.E UNITED STATES PATENT AND TRA.DEI'V[ARK OFFICE
`
`In re Inter Panes Reexamination of
`
`j Art Unh: 3992
`
`U.S. Patent No, 7,619,912
`Inventors: Bhakta, Javesh R. et al.
`.,
`Filed: September 27, 2007
`Issued: November 17, 2009
`Titie: A1emmy Module Decoder
`
`.
`
`Reexamination Control No. 95/000,578
`Filed: October 20, 2010
`Attorney Docket No.: 17730-3
`
`1
`I Examiner: \\''oo H. Choi
`!
`
`I
`
`:·
`
`-----------------~-···---------····---------------·------···--··------~
`
`:tvfail Stop Inter Partes Reexai.11
`Central Reexarnination Unit
`Cormnissioner for Patents
`P.O. Box 1450
`Alexm1<lria, VA 22313-1450
`
`AMENDED CERTIFICATE OF SERVICE
`
`I, Susan Prindpe, declare as foHows:
`
`f m11 employed v,/ith the lav,,r firm of Orrick, Herrington & Sutcliffe LLP, whose
`
`address is 1000 r.farsh Road, Menlo Park, CA 94025, I am over the .age of eighteen
`
`years and not a party to this action.
`
`On August 29, 2011, 1 caused to be served the folknving document(s):
`
`] , Third Party Requester's Comrnents to Patent Owner's Response of July 5, 2011
`and the Office~s Decision Granting Petition to Vv'aive Page Limit of July 29,
`2011Under 37 CTR.§ 1.947;
`
`2. Supplemental Infomiation Disclosure Statement, Form SB08a Under
`'<\{)' )'·1·
`•.
`'
`'1'' 1··,.•.n,4. ~-s·.
`.t .::to( a. l ) ami attacned 1:'.·X,)WJ.t £ 1-~-u.
`•'(•"'/(''}'~}
`..h. ..
`J ,
`,.
`
`3, Table of Exhibits and attached Exhibits PAT-El, CC-19 OTH-H, OTH-l, and
`
`.,., A7c~rn ,,, 1.,., .. ,.
`. l} ..
`R
`4 "''' ' n
`u-
`l mra 1'arty equestor · s et1t1on , msuam 1 o 5
`.. ;<. 1-.... ~ L ~., lo ~uspem:t t_.1r
`.
`\Vaive The Page Count Limit Of 37 C.F.R. § 1.946(b)
`
`, , ,
`
`f:S
`
`l
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2850
`
`

`

`

`

`Electronic Acknowledgement Receipt
`
`EFSID:
`
`Application Number:
`
`10837525
`
`95000578
`
`International Application Number:
`
`Confirmation Number:
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`8810
`
`Title of Invention:
`
`MEMORY MODULE DECODER
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`First Named Inventor/Applicant Name:
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`7619912
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`Customer Number:
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`20995
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`Filer:
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`Dana M. Zottola/Susan Principe
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`Filer Authorized By:
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`Dana M. Zottola
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`Attorney Docket Number:
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`17730-3
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`Receipt Date:
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`Filing Date:
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`Time Stamp:
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`29-AUG-2011
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`20-0CT-2010
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`18:06:39
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`Application Type:
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`inter partes reexam
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`Payment information:
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`Submitted with Payment
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`I no
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`File Listing:
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`Document
`Number
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`Document Description
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`File Name
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`File Size(Bytes)/
`Message Digest
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`Multi
`Part /.zip
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`Pages
`(if appl.)
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`432082
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`1
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`Reexam Certificate of Service
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`17 _Certificate2.pdf
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`no
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`2
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`dbcac47b80a2ae4b52b98bcc777d3595af7
`26010
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`Warnings:
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`Information:
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2852
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`Total Files Size (in bytes)
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`432082
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`This Acknowledgement Receipt evidences receipt on the noted date by the USPTO of the indicated documents,
`characterized by the applicant, and including page counts, where applicable. It serves as evidence of receipt similar to a
`Post Card, as described in MPEP 503.
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`New Applications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary components for a filing date (see 37 CFR
`1.53(b)-(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date shown on this
`Acknowledgement Receipt will establish the filing date of the application.
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`National Stage of an International Application under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions of 35
`U.S.C. 371 and other applicable requirements a Form PCT/DO/E0/903 indicating acceptance of the application as a
`national stage submission under 35 U.S.C. 371 will be issued in addition to the Filing Receipt, in due course.
`
`New International Application Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary components for
`an international filing date (see PCT Article 11 and MPEP 181 O), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/R0/1 OS) will be issued in due course, subject to prescriptions concerning
`national security, and the date shown on this Acknowledgement Receipt will establish the international filing date of
`the application.
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2853
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`Inter Partes Reexamination Nos. 95/000,578; 95/000,579; 95/001,339
`Attorney Docket No.: 19473-0099RX I
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`On pages 59-60, the Response argues that, "[despite the] differences between EDO and
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`DOR addressing and command protocols, the Office Action at p. 44 asserts that it would have
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`been obvious ... 'to modify the design the DIMM of Micron to incorporate Connolly's
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`technique.' [Neither] the Office Action nor the '0579 Request explains how the proposed
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`combination would result in the claimed memory module."
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`The motivation here is not to copy circuits from Connolly to Micron, but to design a
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`lower-cost module that could be used instead of the Micron module. A person of ordinary skill
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`in the art would have known how to do this in an obvious and predictable way, as explained in
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`these comments and the Kozyrakis Declaration, using the knowledge such a person has and the
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`teachings of Micron and Connolly.
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`In addition, as explained in paragraph 13 of the Kozyrakis Declaration, a person of
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`ordinary skill in the art "would have a strong understanding and experience on the following
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`topics: memory array organization and control (rows, columns, banks, ranks, and channels),
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`address interleaving and decoding (generation of decoded row, column, bank, and rank select
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`signals from an encoded address); asynchronous interfaces (such as EDO DRAM interfaces);
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`synchronous interfaces (such as SDRAM and DDR DRAM interfaces); combinational logic
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`design; sequential logic design .... " Such a person would have been able to apply the
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`techniques taught by Connolly in the EDO context to the later DDR context.
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`As the Supreme Court noted, "the analysis need not seek out precise teachings directed to
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`the specific subject matter of the challenged claim, for a court can take account of the inferences
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`and creative steps that a person of ordinary skill in the art would employ." KSR v. Teleflex, 550
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`U.S. 398,418 (2007).
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`"When there is a design need or market pressure to solve a problem and there are a finite
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`number of identified, predictable solutions, a person of ordinary skill has good reason to pursue
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`the known options within his or her technical grasp. If this leads to the anticipated success, it is
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`likely the product not of innovation but of ordinary skill and common sense. In that instance the
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`fact that a combination was obvious to try might show that it was obvious under§ 103." KSR v.
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`Teleflex, 550 U.S. 398,422 (2007).
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`3
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2861
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`Inter Partes Reexamination Nos. 95/000,578; 95/000,579; 95/001,339
`Attorney Docket No.: 19473-0099RXI
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`the load on this signal. The load is due to the logic element and the PLL
`devices in the plurality of modules connected to the controller. If the PLL
`output clock is used, this clock is driven by the PLL and the POSIT A would
`analyze if the PLL can handle the load on this signal. The load is due to the
`logic element and the memory devices on the module. In both cases, the
`POSIT A would look at the specification of the driver for the clock signal
`within the memory controller or the PLL, the overall load on the signal, and
`the specification for the expected input clock for all devices that receive it
`to ensure that all constraints are met. If some constraint is not met, the
`POSIT A may need to retune the memory controller driver or the PLL to
`handle the load. Alternatively, the POSITA can change the load by
`changing the layout of devices in the module or the specific device used to
`implement the logic element. This careful analysis and tuning are necessary
`whenever a new memory module is designed, regardless if it uses the
`originally specified devices or a larger number of lower density devices.
`The POSIT A would understand this process based on the experience from
`previous memory module designs and the information included in industry
`specifications and standards for memory modules and PLLs.
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`These points are addressed in even more detail, and the erroneous conclusions of Dr.
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`Sechen are refuted in detail, in paragraphs 26-30 of the Kozyrakis Declaration. In particular, the
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`declaration notes:
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`28. As the Sechen '912 declaration correctly states, for memory modules
`operating at high speeds, it is necessary to connect all devices in the lower(cid:173)
`cost module, including the logic element, the register, and the memory
`devices to the same, high quality clock in order to achieve reliable operation
`for the module. However, the Sechen '912 declaration claims that a
`POSIT A would not have the knowledge to connect the device that
`implements to the logic element (CPLD, FPGA, or ASIC) to the output
`clock from the PLL prior to the priority date for the '912 patent (paragraph
`52). This claim is incorrect for the [reasons set forth in ,i,i 28(a)-(e)].
`(Kozyrakis Dec. ,i 28.)
`·
`Thus, as is clear from the Kozyrakis Declaration, the person of ordinary skill in the art
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`has a few choices in designing the lower-cost module, one of which is to clock the logic and the
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`memory devices from the phase-lock loop device.
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`"When ... there are a finite number of identified, predictable solutions, a person of
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`ordinary skill has good reason to pursue the known options within his or her technical grasp. If
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`this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill
`
`and common sense. In that instance the fact that a combination was obvious to try might show
`
`that it was obvious under§ 103." KSR v. Teleflex, 550 U.S. 398,422 (2007). In the present case,
`
`IO
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2868
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`Inter Partes Reexamination Nos. 95/000,578; 95/000,579; 95/001,339
`Attorney Docket No.: l 9473-0099RX I
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`EDO memory technology requires a RAS command to be immediately prior to the
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`corresponding CAS command, without intervening RAS or CAS commands, so it is not capable
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`of executing back-to-back adjacent read commands across DDR memory device boundaries or
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`successive read accesses from different ranks ofDDR memory devices. (Sechen Deel.,, 103.)"
`It is plain, but of no consequence, that an EDO module is not capable of executing any
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`commands on DOR devices.
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`The Response acknowledges that "The memory module of Micron presumably is
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`capable of performing such operations, since it is expected of standard DDR memory modules."
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`Thus, a person of ordinary skill in the art, motivated to implement a lower-cost module
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`meeting the specifications of a Micron module, would have been powerfully motivated to design
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`a module "capable of performing such ·operations."
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`As explained in paragraph 14 of the Kozyrakis Declaration, the person of ordinary skill in
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`the art was well qualified to design such a module:
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`As part of the two or more years of professional experience in the design of
`memory systems, a POSIT A would acquire a strong understanding and
`experience in the following topics: the specification of the latest memory
`devices (such as DDR, DDR-2, or DDR-3 devices); ... the signals for and
`sequencing of commands to memory devices (such as CAS, RAS, precharge,
`refresh or other commands); the design of memory modules using memory
`devices; the elimination of signal integrity, timing, and clocking issues in
`memory modules using register devices to buffer signals and using PLL devices
`to buffer clocks; ... the mapping and decoding of data addresses across the
`rows, columns, banks, ranks, and channels in the memory system (including the
`parts of the address decoded at the memory control and the parts of the address
`decoded at the memory devices); the design and configuration of memory
`controllers so that they can operate with several types of memory modules and·
`devices. A POSITA would also have a strong understanding of the
`specifications, standards, guidelines, and reference designs produced by industry
`organizations such as JEDEC.
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`In addition, as noted in paragraph 25(b) of the Kozyrakis Declaration,
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`... as part of the ordinary engineering process of testing the logic element, the
`POSIT A would develop test input cases that include all possible commands to
`the DOR devices. These commands are clearly enumerated in JEDEC
`specifications and in the datasheets of specific devices made available by a
`vendor (e.g., Micron). Hence, the POSITA would ... develop test inputs that
`demonstrate the correct operation of the functions for all possible
`commands ....
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`16
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2874
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`64811 U.S. PTO
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`l\ll\\\ll\lllll\\\\\\l\llll\l\\\l\\lll\llll\11111\
`08/29/11
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`Inter Partes Reexamination Nos. 95/000,578; 95/000,579; 95/001,339
`Attorney Docket No.: 19473-0099RX I
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`CERTIFICATE OF SERVICE
`
`I hereby certify that on, I caused a true and correct copy of the foregoing REQUESTER'S
`
`COMMENTS UNDER 37 C.F.R. § 1.947 to be served by U.S. mail on the following attorney of
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`record for the purported patent owner:
`
`Bruce S. Itchkawitz
`KNOBBE MARTENS OLSON & BEAR LLP
`2040 Main Street
`Fourteenth Floor
`Irvine, CA 92614
`
`Michael F. Heafey
`ORRICK, HERRINGTON & SUTCLIFFE LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`
`David A. Jakopin
`PILLSBURY WINTHROP SHAW PITTMAN, LLP
`P.O. BOX 10500
`MCLEAN, VA22102
`
`Date: August 29, 2011
`
`·
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`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2879
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`IJJi!i!\. UNITED STATES PATENT AND TRADEMARK OFFICE
`~
`
`Commissioner for Patents
`United States Patents and Trademark Office
`P.O.Box 1450
`Alexandria, VA 22313-1450
`www.uspto.gov
`
`DO NOT USE IN PALM PRINTER
`
`THIRD PARTY REQUESTER'S CORRESPONDENCE ADDRESS
`ORRICK, HERRINGTON & SUTCLIFFE, LLP
`IP PROSECUTION DEPARTMENT
`4 PARK PLAZA, SUITE 1600
`IRVINE, CA 92614-2558
`
`Date:
`
`MAILED
`OCT 04.ZOtf
`CENTRAL RF.EXM'll~ATIOH UHfT
`
`Transmittal of Communication to Third Party Requester
`Inter Partes Reexamination
`REEXAMINATION CONTROL NO.: 95000578 t qscoc S')C\ -t- o.soo \ o,3C\
`PATENT NO.: 7619912
`TECHNOLOGY CENTER: 3999
`ART UNIT : 3992
`
`Enclosed is a copy of the latest communication from the United States Patent and Trademark
`Office in the above identified Reexamination proceeding. 37 CFR 1.903.
`
`Prior to the filing of a Notice of Appeal, each time the patent owner responds to this
`communication, the third party requester of the inter partes reexamination may once file
`written comments within a period of 30 days from the date of service of the patent owner's
`response. This 30-day time period is statutory (35 U.S.C. 314(b)(2)), and, as such, it cannot
`be extended. See also 37 CFR 1.947.
`
`If an ex parte reexamination has been merged with the inter partes reexamination, no
`responsive submission by any ex parte third party requester is permitted.
`
`All correspondence relating to this inter partes reexamination proceeding should be directed
`to the Central Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end
`of the communication enclosed with this transmittal.
`
`PTOL-2070(Rev.07-04)
`
`Samsung Electronics Co., Ltd.
`Ex. 1010, p. 2883
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`

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`OFFICE ACTION IN INTER PARTES
`REEXAMINATION
`
`Control No. f / 33 '1
`95/000,578 + \~ Ci
`Examiner
`
`WOO H. CHOI
`
`Patent Under Reexamination
`
`7619912
`Art Unit
`
`3992
`
`•• The MAILING DA TE of this communication appears on the cover sheet with the correspondence address. ••
`
`Responsive to the communication(s) filed by:
`Patent Owner on 7/5/2011
`Third Party(ies) on 8/29/2011
`
`RESPONSE TIMES ARE SET TO EXPIRE AS FOLLOWS:
`
`For Patent Owner's Response:
`i MONTH(S) from the mailing date of this action. 37 CFR 1.945. EXTENSIONS OF TIME ARE
`GOVERNED BY 37 CFR 1.956.
`For Third Party Requester's Comments on the Patent Owner Response:
`30 DAYS from the date of service of any patent owner's response. 37 CFR 1.947. NO EXTENSIONS
`OF TIME ARE PERMITTED. 35 U.S.C. 314(b)(2).
`
`All correspondence relating to this inter partes reexamination proceeding should be directed to the Central
`Reexamination Unit at the mail, FAX, or hand-carry addresses given at the end of this Office action.
`
`This action is not an Action Closing Prosecution under 37 CFR 1.949, nor is it a Right of Appeal Notice under
`37 CFR 1.953.
`
`PART I. THE FOLLOWING ATTACHMENT(S) ARE PART OF THIS ACTION:
`1.D Notice of References Cited by Examiner, PT0-892
`2.IZ! Information Disclosure Citation, PTO/SB/08
`3.0
`
`PART II. SUMMARY OF ACTION:
`1 a. 1:2] Claims 1-118 are subject to reexamination.
`1 b. D Claims
`are not subject to reexamination.
`2. D Claims __ have been canceled.
`3. 1:2] Claims See Continuation Sheet are confirmed. [Unamended patent claims]
`4. D Claims __ are patentable. [Amended or new claims]
`5. 1Z1 Claims See C