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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`GOOGLE LLC,
`Petitioner,
`
`v.
`
`VALTRUS INNOVATIONS LTD.,
`Patent Owner.
`
`________________
`
`Case No. TBD
`
`Patent No. 6,816,809
`_____________
`
`
`
`DECLARATION OF VIJAY K. MADISETTI, PH.D.
`IN SUPPORT OF PETITION FOR INTER PARTES
`REVIEW OF U.S. PATENT NO. 6,816,809
`
`
`
`
`Google Exhibit 1003
`Google v. Valtrus
`
`

`

`
`
`TABLE OF CONTENTS
`
`
`CONTENTS
`
`I.
`
`INTRODUCTION ............................................................................................. 1
`
`A. Engagement ................................................................................................. 1
`
`B. Background and Qualifications ................................................................... 2
`
`II. MATERIALS REVIEWED AND CONSIDERED .......................................... 8
`
`III. MY UNDERSTANDING OF PATENT LAW ...............................................11
`
`A. Anticipation ...............................................................................................13
`
`B. Obviousness ...............................................................................................13
`
`IV. PERSON OF ORDINARY SKILL IN THE ART (“POSA”) .........................16
`
`V. THE ’809 PATENT ........................................................................................18
`
`A. Described Embodiments ............................................................................20
`
`B. Prosecution History of the ’809 Patent ......................................................24
`
`C. The Challenged Claims .............................................................................25
`
`VI. CLAIM INTERPRETATION .........................................................................27
`
`VII. PRIOR-ART REFERENCES ..........................................................................27
`
`A. Ogawa (Ex. 1005) ......................................................................................27
`
`B. Vea (Ex. 1006) ...........................................................................................30
`
`C. Bohac (Ex. 1007) .......................................................................................35
`
`D. McAnlis (Ex. 1010) ...................................................................................36
`
`E. Zalewski (Ex. 1008) ..................................................................................37
`
`F. Cellular-IRIX (Ex. 1009) ...........................................................................38
`
`VIII. THE CHALLENGED CLAIMS ARE UNPATENTABLE IN LIGHT
`OF THE PRIOR ART IDENTIFIED IN THE PETITION .............................39
`
`A. Ground 1: Ogawa Anticipates and/or Renders Claims 1-3, 5, 7, 9,
`10, 13, 15-17 Obvious ...............................................................................40
`
`1. Claim 1 ................................................................................................40
`
`2. Claim 2 ................................................................................................46
`
`i
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`

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`3. Claim 3 ................................................................................................46
`
`4. Claim 5 ................................................................................................51
`
`5. Claim 7 ................................................................................................51
`
`6. Claim 9 ................................................................................................52
`
`7. Claim 10 ..............................................................................................55
`
`8. Claim 13 ..............................................................................................56
`
`9. Claim 15 ..............................................................................................58
`
`10. Claim 16 ..............................................................................................59
`
`11. Claim 17 ..............................................................................................59
`
`B. Grounds 2 and 3: Ogawa and Bohac (Ground 2) and Ogawa and
`McAnlis (Ground 3) Render Claims 6 and 14 Obvious ............................60
`
`1. Ground 2: Ogawa and Bohac Render Claims 6 and 14 Obvious .......62
`
`2. Ground 3: Ogawa and McAnlis Render Claims 6 and 14
`Obvious................................................................................................64
`
`C. Ground 4: Ogawa and Zalewski and/or Ogawa and Cellular-IRIX
`Render Claims 10, 12, and 18 Obvious .....................................................65
`
`1. Claim 10 ..............................................................................................66
`
`2. Claim 12 ..............................................................................................67
`
`D. Ground 5: Ogawa, Zalewski, and McAnlis and/or Ogawa, Cellular-
`IRIX, and McAnlis Renders Claim 11 Obvious .......................................68
`
`1. Claim 11 ..............................................................................................68
`
`E. Ground 6: Vea Renders Claims 1-2, 4, 7-10, 13, 15-17 Obvious ............70
`
`1. Claim 1 ................................................................................................70
`
`2. Claim 2 ................................................................................................83
`
`3. Claim 4 ................................................................................................83
`
`4. Claim 5 ................................................................................................86
`
`5. Claims 7-8 ...........................................................................................87
`
`6. Claim 9 ................................................................................................89
`
`7. Claim 10 ..............................................................................................92
`
`8. Claim 11 ..............................................................................................92
`
`ii
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`9. Claim 13 ..............................................................................................93
`
`10. Claim 15 ..............................................................................................96
`
`11. Claim 16 ..............................................................................................97
`
`12. Claim 17 ..............................................................................................97
`
`F. Ground 7: Vea and Bohac Render Claims 6 and 14 Obvious ..................98
`
`1. Claims 6 and 14 ...................................................................................98
`
`G. Ground 8: Claims 10 and 12 are Rendered Obvious by Vea and
`Zalewski and/or Vea and Cellular-IRIX ...................................................99
`
`1. Claim 10 ..............................................................................................99
`
`2. Claim 12 ............................................................................................100
`
`IX. CONCLUSION ..............................................................................................100
`
`
`
`
`
`
`iii
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`
`
`I, Vijay K. Madisetti, declare:
`
`I.
`
`INTRODUCTION
`
`A. Engagement
`
`1.
`
`I have been retained on behalf of Google LLC (“Google” or the
`
`“Petitioner”) as an independent technical expert in the above-captioned IPR
`
`proceeding (“the IPR”). This document provides certain of my opinions
`
`concerning the patentability of all claims in U.S. Patent No. 6,816,809 (Ex. 1001,
`
`“the ’809 patent”), specifically claims 1-20 (the “Challenged Claims”). I make this
`
`Declaration in support of Google’s petition in the IPR.
`
`2.
`
`For my work as an expert in this matter, I am being compensated for
`
`my services at my standard rate of $600 per hour, plus actual expenses. My hourly
`
`compensation is based solely on the amount of time that I devote to activity related
`
`to this case and is in no way contingent on the nature of my findings, the
`
`presentation of my findings in testimony, or the outcome of this or any other
`
`proceeding. I have no other personal or financial stake or interest in the outcome of
`
`the present proceeding. I do not have any expectation or promise of additional
`
`business with the Petitioner in exchange for the positions explained herein.
`
`3.
`
`I make this Declaration based on my personal knowledge, including
`
`my education, training, research, and professional experience.
`
`1
`
`

`

`
`
`B.
`
`Background and Qualifications
`
`4. My curriculum vitae (“CV”) detailing my educational background,
`
`professional experience, and list of publications is provided as Exhibit 1004. Some
`
`of my background and experience that qualifies me to offer the opinions in this
`
`Declaration as an expert in the technical issues in this case are as follows.
`
`5.
`
`I have over thirty years of experience as an electrical and computer
`
`engineer in industry, education, and consulting.
`
`6.
`
`I am a Professor in the Schools of Electrical & Computer Engineering
`
`and Cybersecurity & Privacy at the Georgia Institute of Technology (Georgia
`
`Tech). I have worked extensively in the field of digital communications and have
`
`studied telecommunications and systems engineering since 1981. I also have over
`
`20 years of industry experience in computer engineering, distributed computer
`
`systems, networking, software engineering, signal processing, and
`
`telecommunications, including wireless communications and signal processing.
`
`Throughout this time, I have designed, implemented, and tested various products in
`
`the fields of electronics, computer engineering, and communications.
`
`7.
`
`In 1984, I received a Bachelor of Technology in Electronics and
`
`Electrical Communications Engineering from the Indian Institute of Technology
`
`(IIT). In 1989, I received my Ph.D. in Electrical Engineering and Computer
`
`Sciences (EECS) from the University of California, Berkeley. That year, I also
`
`2
`
`

`

`
`
`received the Demetri Angelakos Outstanding Graduate Student Award from the
`
`University of California, Berkeley, and the IEEE/ACM Ira M. Kay Memorial
`
`Paper Prize.
`
`8.
`
`In 1989, I also joined the faculty of Georgia Tech. I began working at
`
`Georgia Tech as an assistant professor, became an associate professor in 1995, and
`
`have held my current position since 1998. As a member of the faculty at Georgia
`
`Tech, I have been active in, among other technologies, cloud computing,
`
`distributed computing, image and video processing, computer engineering,
`
`embedded systems, chip design, software systems, wireless networks and cellular
`
`communications.
`
`9.
`
`I have been involved in research and technology in the area of
`
`computing and digital signal processing since the late 1980s, and I am the Editor-
`
`in-Chief the IEEE Press/CRC Press’s 3-volume Digital Signal Processing
`
`Handbook (Editions 1 & 2) (1998, 2010).
`
`10. Over the past three decades, I studied, used, and designed hardware
`
`and software systems and infrastructure that enable various aspects of distributed
`
`computing, ranging from parallel processing for scientific computation to
`
`implementation of various tracking and management applications including fleet
`
`tracking and management, intelligent transportation system management to name a
`
`few.
`
`3
`
`

`

`
`
`11.
`
`I have designed and implemented multiple processor computing
`
`systems that perform multimedia tasks (e.g., speech and audio recognition) and
`
`also avionics/embedded guidance systems since the mid-1990s, and I have also
`
`implemented real-time operating systems in the same time frame. Representative
`
`publications of my work in these areas include, The Georgia Tech Digital Signal
`
`Multiprocessor (DSMP), IEEE Transactions on Signal Processing, Vol. 41, Issue 7,
`
`1993, and “Task Scheduling on the Georgia Tech Digital Signal Multiprocessor”,
`
`Proc. IEEE ICASSP 1992. More recent work that is related to multimedia
`
`processing on multiprocessor systems can be found in “A Dynamic Resource
`
`Management and Scheduling Environment for Embedded Multimedia and
`
`Communications Platforms”, IEEE Embedded Systems Letters, Vol. 3, Issue 1,
`
`2011. Three generations of Digital Signal Multiprocessors (DSMP’s) (listed in the
`
`table below) were designed at Georgia Tech as part of my research and education
`
`efforts. Technologies including multiprocessor systems, task scheduling,
`
`distributed computing, and resource management are fundamental to cloud
`
`computing infrastructure.
`
`
`
`4
`
`

`

`
`
`
`In collaboration with the US Air Force, Lockheed Martin, and Hughes
`
`12.
`
`Corporation, I designed and implemented a 192-processor multiprocessor system
`
`for processing real-time avionics data (infrared search and track applications –
`
`IRST), and this represented one of the largest multiprocessor systems used in the
`
`mid-1990s timeframe on aircraft. See my publications, “Virtual Prototyping of
`
`Embedded Microcontroller-Based DSP Systems”, IEEE Micro, 1995, and also
`
`“VHDL Token-Based Performance Modeling for 2D and 3D Infrared Search and
`
`Track”, Proc. SPIE VIUF, 1998.
`
`5
`
`

`

`
`
`
`13. Since 1995, I have authored, co-authored, or edited several books in
`
`
`
`the areas of communications, signal processing, chip design, and software
`
`engineering, and cloud-based computing including VLSI Digital Signal Processors
`
`(1995), Quick-Turnaround ASIC Design in VHDL (1996), The Digital Signal
`
`Processing Handbook (1997 & 2010), Cloud Computing: A Hands-On Approach
`
`(2013), Internet of Things: A Hands-On Approach (2014), Big Data Science &
`
`Analytics (2016).
`
`14. Prior to 2002, I authored several published articles related to operating
`
`system design, performance optimization, and virtualization, including:
`
`• V. K. Madisetti and T. W. Egolf, “Virtual prototyping of embedded
`
`microcontroller-based DSP systems,” IEEE Micro, vol. 15, no. 5, pp. 9-
`
`21, Oct. 1995.
`
`6
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`

`

`
`
`• V.K. Madisetti, D.A. Hardaker, and R.J. Fujimoto, “The MIMDEX
`
`Environment for Parallel Simulation,” Journal of Parallel and
`
`Distributed Computing,” vol. 18, no. 4, pp. 473-483, Aug. 1993.
`
`• P. Kuacharoen, T. Akgul, V. J. Mooney and V. K. Madisetti,
`
`“Adaptability, extensibility and flexibility in real-time operating
`
`systems,” Proceedings Euromicro Symposium on Digital Systems
`
`Design, pp. 400-405, 2001.
`
`• T. Akgul, P. Kuacharoen, V.J. Mooney, and V.K. Madisetti, “A debugger
`
`RTOS for embedded systems,” Proceedings 27th EUROMICRO
`
`Conference. 2001: A Net Odyssey, pp. 264-269, 2001.
`
`• V. K. Madisetti. “System-Level Synthesis and Simulation in VHDL – A
`
`Taxonomy and Proposal Towards Standardization.” VHDL International
`
`Users Forum, Spring 1995 Proceedings, pp. 8.1-8.14, 1995.
`
`• S. Famorzadeh, V. Madisetti, T. Egolf and T. Nguyen, “BEEHIVE: an
`
`adaptive, distributed, embedded signal processing environment,” 1997
`
`IEEE International Conference on Acoustics, Speech, and Signal
`
`Processing, vol. 1, pp. 663-666, 1997.
`
`7
`
`

`

`
`
`15.
`
`In addition to co-authoring a book on cloud computing, I authored
`
`several publications on cloud computing. I am also the first inventor on over 30
`
`issued US patents and have several other pending applications in the area of cloud
`
`computing, blockchain and distributed computing.
`
`16.
`
`I have been elected a Fellow of the Institute of Electrical and
`
`Electronics Engineers (“IEEE”) in recognition of my contributions to embedded
`
`computing systems. The IEEE is a worldwide professional body consisting of more
`
`than 300,000 electrical and electronic engineers. Fellow is the highest grade of
`
`membership of the IEEE, with only one-tenth of one percent of the IEEE
`
`membership being elected to the Fellow grade each year.
`
`17.
`
`In 2006, I was awarded the Frederick Emmons Terman Medal from
`
`the American Society of Engineering Education (ASEE) and HP Corporation for
`
`my contribution to electrical engineering while under the age of 45.
`
`II. MATERIALS REVIEWED AND CONSIDERED
`
`18. My findings, as explained below, are based on my years of education,
`
`research, experience, and background in the fields of computer and electrical
`
`engineering, as well as my investigation and study of relevant materials for this
`
`declaration. When developing the opinions set forth in this declaration, I assumed
`
`the perspective of a person having ordinary skill in the art, as set forth in Section
`
`8
`
`

`

`
`
`IV below. In forming my opinions, I have studied and considered the materials
`
`identified in the list below.
`
`19.
`
`I have reviewed the ’809 Patent, its prosecution history, and the prior
`
`art and other documents and materials cited herein. For ease of reference, the list of
`
`documents that I have considered is included below. Each of these materials is a
`
`type of document that experts in my field would have reasonably relied upon when
`
`forming their opinions and would have had access to either through the applicable
`
`patent office and/or well-known libraries, conferences, publications, organizations,
`
`and websites in the field as further discussed herein.
`
`20. My opinions in this Declaration are based on my review of these
`
`documents, as well as upon my education, training, research, knowledge, and
`
`experience. When developing the opinions set forth in this declaration, I assumed
`
`the perspective of a person having ordinary skill in the art, as set forth in Section
`
`III below.
`
`21. The opinions and comments formulated during this assessment are
`
`based on observations and information available at the time of this investigation.
`
`Exhibit Description
`
`1001
`
`1002
`
`1005
`
`U.S. Patent No. 6,816,809
`
`Prosecution History of U.S. Patent No. 6,816,809
`
`Japanese Patent Application No. 60-24655 to M. Ogawa and H.
`Noguchi (“Ogawa”)
`
`1006
`
`U.S. Patent No. 4,924,428 to M. Vea (“Vea”)
`
`9
`
`

`

`
`
`Exhibit Description
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`1013
`1015
`1016
`1017
`1018
`1019
`
`1020
`
`1021
`1022
`1024
`1025
`1026
`1027
`1028
`
`1029
`1030
`1031
`1032
`1033
`1037
`1038
`1039
`1040
`1041
`
`U.S. Patent No. 6,166,984 (“Bohac”)
`
`U.S. Patent Application Publication No. 2002/0052914 (“Zalewski”)
`
`“Cellular IRIX 6.4 Technical Report”, SiliconGraphics Inc., 1996
`(“Cellular-IRIX”)
`
`U.S. Patent No. 4,458,307 (“McAnlis”)
`
`U.S. Patent No. 6,049,798 (“Bishop”)
`
`U.S. Patent No. 5,654,905 (“Mulholland”)
`“meter,” The New Oxford American Dictionary
`U.S. Patent No. 6,760,833 (“Dowling”)
`“meter,” Random House Webster’s unabridged dictionary
`U.S. Patent Application Publication No. 2002/0087901 (“Cooper”)
`U.S. Patent No. 6,901,522 (“Buch”)
`The Authoritative Dictionary of IEEE Standards Terms. IEEE Press.
`(2000)
`Katz, Randy H. Contemporary Logic Design. The
`Benjamin/Cummings Publishing Company Inc. (1994) (“Katz”)
`U.S. Patent No. 5,455,927 (“Huang”)
`U.S. Patent No. 6,581,137 (“Sandorfi”)
`U.S. Patent Appl. Pub. No. U.S. 2005/0177755 (“Fung”)
`U.S. Patent No. 5,590,342 (“Marisetty”)
`U.S. Patent No. 6,735,707 (“Kapil”)
`U.S. Patent No. 6,574,587 (“Waclawski”)
`Amarasinghe, et al. “The Multiprocessor as a General-Purpose
`Processor: A Software Perspective.” (Apr. 1996 IEEE Micro).
`(“Amarasinghe”)
`U.S. Patent No. 5,574,913 (“Ohtsu”)
`U.S. Patent No. 4,228,496 (“Katzman”)
`U.S. Patent Application Publication No. 2003/0126494 (“Strasser”)
`U.S. Patent No. 5,181,231 (“Parikh”)
`U.S. Patent No. 5,283,792 (“Davies”)
`U.S. Patent No. 5,710,710 (“Owen”)
`U.S. Patent No. 4,580,281 (“Carlton”)
`U.S. Patent No. 5,761,216 (“Sotome”)
`U.S. Patent No. 5,825,674 (“Jackson”)
`U.S. Patent No. 5,077,686 (“Rubinstein”)
`
`10
`
`

`

`
`
`Exhibit Description
`
`1042
`1044
`1045
`1046
`1047
`
`
`U.S. Patent No. 5,594,909 (“Inoue”)
`Push vs. pull in web-based network management (“Martin-Flatin”)
`U.S. Patent No. 7,225,250 (“Harrop”)
`U.S. Patent No. 5,774,732 (“Doumard”)
`High Performance Operations (“Cockshott”)
`
`III. MY UNDERSTANDING OF PATENT LAW
`
`22.
`
`In developing my opinions, I discussed various relevant legal
`
`principles with Petitioner’s attorneys. Though I do not purport to have prior
`
`knowledge of such principles, I understood them when they were explained to me
`
`and have relied upon such legal principles, as explained to me, in the course of
`
`forming the opinions set forth in this declaration. My understanding in this respect
`
`is as follows:
`
`23.
`
`I understand that “inter partes review” (IPR) is a proceeding before
`
`the United States Patent & Trademark Office for evaluating the patentability of an
`
`issued patent’s claims based on prior-art patents and printed publications.
`
`24.
`
`I understand that, in this proceeding, Petitioner has the burden of
`
`proving that the challenged claims of the ’809 Patent are unpatentable by a
`
`preponderance of the evidence. I understand that “preponderance of the evidence”
`
`means that a fact or conclusion is more likely true than not true.
`
`25.
`
`I understand that, in IPR proceedings, claim terms in a patent are
`
`given their ordinary and customary meaning as understood by a person of ordinary
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`11
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`

`
`
`skill in the art (“POSA”) in the context of the entire patent and the prosecution
`
`history pertaining to the patent. If the specification provides a special definition
`
`for a claim term that differs from the meaning the term would otherwise possess,
`
`the specification’s special definition controls. If a claim element is expressed as a
`
`“means” for performing a specified function, I understand that it covers the
`
`corresponding structure described in the specification and equivalents of the
`
`described structure. I have applied these standards in preparing the opinions in this
`
`declaration.
`
`26.
`
`I understand that determining whether a particular patent or printed
`
`publication constitutes prior art to a challenged patent claim can require
`
`determining the effective filing date (also known as the priority date) to which the
`
`challenged claim is entitled. I understand that for a patent claim to be entitled to
`
`the benefit of the filing date of an earlier application to which the patent claims
`
`priority, the earlier application must have described the claimed invention in
`
`sufficient detail to convey with reasonable clarity to the POSA that the inventor
`
`had possession of the claimed invention as of the earlier application’s filing date. I
`
`understand that a disclosure that merely renders the claimed invention obvious is
`
`not sufficient written description for the claim to be entitled to the benefit of the
`
`filing date of the application containing that disclosure.
`
`12
`
`

`

`
`
`27.
`
`I understand that for an invention claimed in a patent to be patentable,
`
`it must be, among other things, new (novel—i.e., not anticipated) and not obvious
`
`from the prior art. My understanding of these two legal standards is set forth
`
`below.
`
`A. Anticipation
`
`28.
`
`I understand that, for a patent claim to be “anticipated” by the prior art
`
`(and therefore not novel), each and every limitation of the claim must be found,
`
`expressly or inherently, in a single prior-art reference. I understand that a claim
`
`limitation is disclosed for the purpose of anticipation if a POSA would have
`
`understood the reference to disclose the limitation based on inferences that a POSA
`
`would reasonably be expected to draw from the explicit teachings in the reference
`
`when read in light of the POSA’s knowledge and experience.
`
`29.
`
`I understand that a claim limitation is inherent in a prior art reference
`
`if that limitation is necessarily present when practicing the teachings of the
`
`reference, regardless of whether a person of ordinary skill recognized the presence
`
`of that limitation in the prior art.
`
`B. Obviousness
`
`30.
`
`I understand that a patent claim may be unpatentable if it would have
`
`been obvious in view of a single prior-art reference or a combination of prior-art
`
`references.
`
`13
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`

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`
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`31.
`
`I understand that a patent claim is obvious if the differences between
`
`the subject matter of the claim and the prior art are such that the subject matter as a
`
`whole would have been obvious to a person of ordinary skill in the relevant field at
`
`the time the invention was made. Specifically, I understand that the obviousness
`
`question involves a consideration of:
`
`•
`
`•
`
`•
`
`the scope and content of the prior art;
`
`the differences between the prior art and the claims at issue;
`
`the knowledge of a person of ordinary skill in the pertinent art;
`
`and
`
`•
`
`if present, objective factors indicative of non-obviousness,
`
`sometimes referred to as “secondary considerations.” To my
`
`knowledge, the Patent Owner has not asserted any such
`
`secondary considerations with respect to the ’809 Patent.
`
`32.
`
`I understand that in order for a claimed invention to be considered
`
`obvious, a POSA must have had a reason for combining teachings from multiple
`
`prior-art references (or for altering a single prior-art reference, in the case of
`
`obviousness in view of a single reference) in the fashion proposed.
`
`33.
`
`I further understand that in determining whether a prior-art reference
`
`would have been combined with other prior art or with other information within
`
`14
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`

`
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`the knowledge of a POSA, the following are examples of approaches and
`
`rationales that may be considered:
`
`•
`
`combining prior-art elements according to known methods to
`
`yield predictable results;
`
`•
`
`simple substitution of one known element for another to obtain
`
`predictable results;
`
`•
`
`use of a known technique to improve similar devices in the
`
`same way;
`
`•
`
`applying a known technique to a known device ready for
`
`improvement to yield predictable results;
`
`•
`
`applying a technique or approach that would have been
`
`“obvious to try,” i.e., choosing from a finite number of
`
`identified, predictable solutions, with a reasonable expectation
`
`of success.
`
`•
`
`known work in one field of endeavor may prompt variations of
`
`it for use in either the same field or a different one based on
`
`design incentives or other market forces if the variations would
`
`have been predictable to one of ordinary skill in the art;
`
`•
`
`some teaching, suggestion, or motivation in the prior art that
`
`would have led one of ordinary skill to modify the prior-art
`
`15
`
`

`

`
`
`reference or to combine prior-art reference teachings to arrive at
`
`the claimed invention. I understand that this teaching,
`
`suggestion or motivation may come from a prior-art reference
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`or from the knowledge or common sense of one of ordinary
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`skill in the art.
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`34.
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`I understand that for a single reference or a combination of references
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`to render the claimed invention obvious, a POSA must have been able to arrive at
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`the claimed invention by altering or combining the applied references.
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`IV. PERSON OF ORDINARY SKILL IN THE ART (“POSA”)
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`35.
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`I have been informed and understand that for purposes of assessing
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`whether prior-art references disclose every element of a patent claim (thus
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`“anticipating” the claim) and/or would have rendered the claim obvious, the patent
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`and the prior-art references must be assessed from the perspective of a person
`
`having ordinary skill in the art (“POSA”) to which the patent is related, based on
`
`the understanding of that person at the time of the patent claim’s priority date. I
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`have been informed and understand that a POSA is presumed to be aware of all
`
`pertinent prior art and the conventional wisdom in the art, and is a person of
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`ordinary creativity. I have applied this standard throughout my declaration.
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`36. The ’809 Patent involves technology in the field of computer
`
`engineering. I have been asked to provide my opinions as to the state of the art in
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`this field by July 2002. I use this timeframe because the face of the ’809 Patent
`
`indicates an earliest claimed priority date of July 23, 2002. Whenever I offer an
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`opinion in this declaration about the knowledge of a POSA, the manner in which a
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`POSA would have understood the claims of the ’809 Patent or its description, the
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`manner in which a POSA would have understood the prior art, or what a POSA
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`would have been led to do based on the prior art, I am referencing the July 2002
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`timeframe, even if I do not say so specifically in each case.
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`37.
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`I understand that the Patent Owner may attempt to prove that the
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`alleged invention recited in the challenged claims was conceived at some time
`
`prior to the earliest claimed priority date on the face of the patent. At the time of
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`this declaration, I am unaware of the Patent Owner having alleged any earlier
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`conception date or produced any evidence to establish any earlier conception date.
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`38.
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`In my opinion, a person of ordinary skill in the art in the July 2002
`
`timeframe (“POSA”) would have had at least a Bachelor’s degree in Computer
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`Science, Computer Engineering, or a related field, with 3 years of experience in the
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`area of distributed computing systems, including performance and/or resource
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`optimizations. More education could substitute for experience, and vice versa.
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`This person would have been capable of understanding and applying the teachings
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`of the ’809 Patent and the prior-art references discussed in this declaration.
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`39. By 2002, I held a Ph.D. in Electrical Engineering and Computer
`
`Sciences (EECS), and I had about thirteen years of experience as a Professor of
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`Electrical and Computer Engineering. Therefore, I was a person of more than
`
`ordinary skill in the art during the relevant timeframe. However, I worked with
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`many people who fit the characteristics of the POSA, and I am familiar with their
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`level of skill. When developing the opinions set forth in this declaration, I
`
`assumed the perspective of a person having ordinary skill in the art, as set forth
`
`above.
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`V. THE ’809 PATENT
`
`40. U.S. Patent No. 6,816,809 (“the ’809 Patent”) (Ex. 1001) relates to a
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`hardware-based device that measures processor utilization using an indication of
`
`when the processor is busy or idle, a system clock, and a hardware counter. ’809
`
`Patent, FIG. 1A.
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`41. The ’809 Patent states that measuring processor utilization had only
`
`previously been done in software. Id., 1:11-18. The ’809 Patent identifies
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`drawbacks to software-based solutions for measuring CPU utilization (id., 1:15-45,
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`2:50-3:17) and proposes a hardware-based CPU utilization metering system that
`
`“determines processor utilization for billing and other purposes” would address the
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`drawbacks of software-based solutions (id., 1:6-8). The ’809 Patent uses the term
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`“metering” to mean measuring, which is consistent with how a POSA would have
`
`understood this term. Ex. 1013 (defining meter (noun) as “device that measures
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`and records the quantity, degree, or rate of something” and defining meter (verb) as
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`“measure by means of a meter”), Ex. 1016 (defining meter (noun) as “an
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`instrument for measuring, esp. one that automatically measures and records the
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`quantity of something” and defining meter (verb) as “to measure by means of a
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`meter”). One embodiment of a hardware system for metering CPU utilization is
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`shown in FIG. 1A (id., 2:23-25, 3:50-51) below.
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`A. Described Embodiments
`
`42. The ’809 Patent characterizes software-based solutions as presenting
`
`several issues for measuring CPU utilization (id., 1:15-45, 2:50-3:17) and proposes
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`a hardware-based CPU utilization metering system that “determine[s] processor
`
`utilization for billing and other purposes” (id., 1:6-8). A POSA understood
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`“metering” means measuring. Exs. 1013, 1016 (defining “meter”). One
`
`embodiment of a hardware system for metering CPU utilization of the ’809 Patent
`
`is shown in FIG. 1A (id., 2:23-25, 3:50-51) below.
`
`
`Idle indicator 120 provides “either an ‘idle’ indication or a ‘not-
`
`43.
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`idle/busy indication” for CPU 110 (id., 3:57-61). According to the ’809 Patent,
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`and consistent with a POSA’s understanding, “idle” means the CPU is “not
`
`processing commands” (id., 4:41-42). The ’809 Patent states some CPU chips had
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`“a pin … that provides a halt (idle) indication” when the operating system (“OS”)
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`halts the CPU, and in one embodiment idle indicator 120 is “coupled to the pin to
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`read the halt (idle) indication” (id., 4:39-45). As an alternative, the ’809 Patent
`
`states that an OS places an idle CPU in an idle loop, and that the OS is modified to
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`set and clear an “externally visible