|, Eric Vance, hereby declare:
`
`That | possess advanced knowledge of the Japanese and English languages. The attached Japaneseinto
`English translation has been translated by me and to the best of my knowledgeand belief, it is a true
`and accuratetranslation of Japanese Unexamined Patent Application Publication No. $60-24655.
`
`| declare that all statements made above of my own knowiedgeare true and thatall statements made
`on information and belief are believed to be true. | have been warned and understand thatwillful false
`
`statements and the like are punishable by fine or imprisonment, or both, under § 1001 ofTitle 18 of the
`United States Code.
`
`| declare under penalty of perjury that the foregoingis true and correct.
`
`Executed on May 27, 2022 in South Jordan, Utah.
`
`Eric Vance
`
`Notary Public
`
`Notary Commission Expiry
`
`“sy, MERCEDES ANNTIONETTE KELLEY
`SN
`ic
`-
`otaryFuteeUtah
`My Commission Expires on
`May 26, 2024
`y
`
`State of UTA: Countyof Salt Lote
`.
`The foregoing instrument was acknowledged before me
`this Z TEdayof M ou
`20.22.
`by
`
`vice Vance
`
`
`My Commission Expires
`
`Google Exhibit 1005
`Google Exhibit 1005
`Google v. Valtrus
`Google v. Valtrus
`
`

`

`
`
`
`
`
`(19) Japan Patent Office (JP)
`(11) Patent Application Publication No.
`(12) JAPANESE UNEXAMINED PATENT
`S60-24655
`APPLICATION PUBLICATION (A)
`
`Ident. Code
`Internal Ref. No.
`(43) Publication Date February 7, 1985
`
`6913-5B
`
`
`
`
`
`
`
`
`
`1
`No. of Inventions
`Examination Request Not Yet
`
`
`
`
`(51) Int. Cl.4
`G 06 F 11/34
`
`
`
`
`
` (Total 3 pages)
`
`
`(72) Inventor NOGUCHI, Hiroyuki
`(54) CENTRAL PROCESSING UNIT
`
`5-33-1, Shiba, Minato-ku,
`USAGE RATE MEASURING DEVICE
`
`Tokyo-to
`(21) Application No. S58-132355
`
`c/o NEC Corporation
`(22) Date of Filing
`July 19, 1983
`(71) Applicant NEC Corporation
`(72) Inventor
`OGAWA, Masaaki
`
`5-33-1, Shiba, Minato-ku,
`
`5-33-1, Shiba, Minato-ku,
`
`Tokyo-to
`
`Tokyo-to
`(74) Agent
`Patent Attorney: INOKUCHI,
`
`c/o NEC Corporation
` Hisashi
`
`
`
`
`
`
`
`Specification
`1. Title of Invention
`CENTRAL PROCESSING UNIT USAGE
`RATE MEASURING DEVICE
`2. Scope of Patent Claims
`rate
`A central processing unit usage
`measuring device used in an automatic exchanger
`having a processing format composed of a
`program which requires a time constraint and
`launches at a fixed time interval, the central
`processing unit usage rate measuring device
`comprising: a first counter for counting an
`effective processing time of a central processing
`unit due to a control order from the central
`processing unit; a first register for storing content
`of the first counter, a second counter for counting
`an idle time of the central processing unit due to
`the control order from the central processing unit;
`a second register for storing content of the second
`counter; an arithmetic circuit for calculating a
`central processing unit usage rate from the
`effective processing time and the idle time of the
`central processing unit; and a control order
`decoder for decoding the control order from the
`central processing unit and applying a control
`signal to the first and second counters and the first
`
`-325-
`
`and second registers; and being configured to
`calculate the central processing unit usage rate by
`using the arithmetic circuit to calculate the
`content stored in the first and second registers.
`3. Detailed Description of Invention
`The present invention relates to a device for
`measuring a usage rate of a central processing
`unit used in an automatic exchanger.
`Conventionally, in the measurement of the
`usage rate of a central processing unit, a counter
`for generating an interrupt timing is used to
`capture the content of a counter via a program,
`and an arithmetic operation is performed to
`calculate the usage rate of the central processing
`unit. However, in this method, the arithmetic
`operation for calculating the usage rate is
`performed using the central processing unit, and
`thus there is a disadvantage in that the load on the
`central processing unit increases.
`An objective of the present invention is to
`provide a central processing unit usage rate
`measuring device provided with a pair of
`counters and a pair of registers which can remove
`the foregoing disadvantage by measuring the
`usage rate of the central
`
`
`
`

`

`
`
`
`
`processing unit at a hardware level and reduce the
`load on the central processing unit, in order to
`measure the usage rate of the central processing
`unit.
`The central processing unit usage rate
`measuring device according to the present
`invention is used in an automatic exchanger
`having a processing format composed of a
`program which requires a time constraint and
`launches at a fixed time interval and is provided
`with first and second counters, first and second
`registers, an arithmetic circuit, and a control order
`decoder.
`The first counter is for counting an effective
`processing time of a central processing unit due
`to a control order from the central processing unit.
`The first register is for storing content of the
`first counter.
`The second counter is for counting an idle
`time of a central processing unit due to the control
`order from the central processing unit.
`The second register is for storing content of
`the second counter.
`The arithmetic circuit is for calculating a
`central processing unit usage rate from the
`
`
`unit 1 via the control order decoder 3. A clock
`signal from the clock generator 2 is inputted into
`the first and second counters 4 and 6. Output from
`the first and second registers 5 and 7 is connected
`to the arithmetic circuit 8. The central processing
`unit 1 is a processing unit of a format in which a
`periodic program is executed at a periodic time
`interval, and a clear 0 control order is sent from
`the central processing unit 1 to the control order
`decoder 3 at the start time of processing of the
`periodic program. The control order decoder 3
`decodes the foregoing control order, generates a
`CLR0 signal, and applies this to the first counter
`4. Once the CLR0 signal is applied, the content of
`the first counter 4 is cleared, the first counter 4
`starts counting the clock signal sent from the first
`clock generator 2. Once the central processing
`unit 1 ends all processing of the periodic program,
`a clear 1 control order is sent from the central
`processing unit 1 to the control order decoder 3.
`Then, the control order decoder 3 decodes this
`control order, generates a CLR1 signal, and
`applies this to the second counter 6 and the
`second register 7. Once the CLR1 signal is
`
`-326-
`
`JP S60-24655 (2)
`
`effective processing time and idle time of the
`central processing unit.
`The control order decoder is for decoding the
`control order from the central processing unit and
`applying a control signal to the first and second
`counters and the first and second registers.
`The present invention is configured to
`calculate the central processing unit usage rate by
`using the arithmetic circuit to calculate the
`content stored in the first and second registers.
`Next, an embodiment of the present invention
`will be described in detail with reference to a
`drawing.
`FIG. 1 is a block diagram illustrating one
`embodiment of the central processing unit usage
`rate measuring device according to the present
`invention. In FIG. 1, 1 is a central processing unit,
`2 is a clock generator, 3 is a control order
`decoder, 4 is a first counter, 5 is a first register, 6
`is a second counter, 7 is a second register, 8 is an
`arithmetic circuit, and 9 is a comparator circuit.
`In FIG. 1, the first counter 4, the first register
`5, the second counter 6, and the second register 7
`are connected to the central processing
`
`applied, the content of the second counter 6 is
`cleared, and the second counter 6 starts counting
`the clock sent from the clock generator 2. At this
`time, the first register 5 stores the content of the
`first counter 4. Once the central processing unit 1
`has again started the processing of the periodic
`program after a fixed amount of time has passed,
`the clear 0 control order is again sent from the
`central processing unit 1. Then, the content of the
`first counter 4 is cleared, and the first counter 4
`starts counting the clock signal from the clock
`signal generator 2. At this time, the content of the
`second counter 6 is stored in the second register
`7. The arithmetic circuit 8 calculates the usage
`rate of the central processing unit 1 based on the
`effective processing
`time of
`the central
`processing unit 1, which is the content of the first
`register 5, and the idle time of the central
`processing unit 1, which is the content of the
`second register 7. Furthermore, by adding the
`comparator circuit 9 and comparing against a
`fixed central processing unit usage rate such as
`80%, for example, it is possible to perform a
`
`

`

`JP S60-24655 (3)
`
`particular type of operations, such as extension
`transmission restrictions.
`When performing the above repeatedly, it is
`possible to calculate the usage rate of the central
`processing unit 1 at a hardware level.
`As described above, the present invention has
`an effect in that, by providing a pair of counters
`and a pair of registers and measuring the usage
`rate of the central processing unit at a hardware
`level, it is possible to reduce the load on the
`central processing unit.
`4. Brief Description of Drawings
`FIG. 1 is a block diagram illustrating one
`embodiment relating to a measurement device of
`a central processing unit, which is configured
`according to the present invention.
`1 … Central processing unit
`2 … Clock generator
`3 … Control order decoder
`4, 6 … Counter
`5, 7 … Register
`8 … Arithmetic circuit
`9 … Comparison circuit
`
`FIG. 1
`
`-327-
`
`

`

`

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