115
`United States Patent
`4,924,428
`[11] Patent Number:
`May8, 1990
`[45] Date of Patent:
`Vea
`
`[54] REAL TIME DIGITAL SIGNAL PROCESSOR
`IDLE INDICATOR
`
`[75]
`Inventor:
`[73] Assignee:
`
`Matthew J. J. Vea, Rowlett, Tex.
`
`Northern Telecom Limited, Montreal,
`Canada
`
`[21] Appl. No.: 130,153
`[22] Filed:
`Dec. 8, 1987
`[S12]
`Tint. C15 oeeseesesenccecssnenserseceneenenene GO04F 10/00
`[52] US. Ch. veecceesesesneseeseeeneesene 364/900; 364/921.8;
`364/942.7; 364/946.2; 364/946.9; 364/569
`[58] Field of Search ... 364/579, 580, 569, 200 MSFile,
`364/900 MSFile, 200, 900; 371/15, 16, 19, 28,
`29
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`........ssssseoeeee 364/200
`3,623,007 11/1971 Eckhart et al.
`
`364/200
`..
`3,771,144 11/1973 Beladyet al.
`364/200
`3,818,458
`6/1974 Deese.........
`364/200
`4,030,072
`6/1977 Bjornsson.......
`
`364/200
`4,126,895 11/1978 Weemaesetal. ..
`364/200
`2/1984 Bogaert etal. ....
`4,432,051
`
`
`371/19
`5/1985 Lewis......08
`4,517,671
`364/569
`4,677,580 6/1987 Saluski ....
`
`4,713,791 12/1987 Saluski 0...
`ssscsssereseseesnees 364/900
`
`OTHER PUBLICATIONS
`
`Z20 Assembly Language Programming by Lance Le-
`venthal, 1979, pp. 11-8 to 11-10.
`Primary Examiner—Gareth D. Shaw
`Assistant Examiner—P. V. Kulik
`Attorney, Agent, or Firm—Nixon & Vanderhye
`[57]
`ABSTRACT
`Instructions in the processor idle loop are used to mea-
`sure the percentage of time the processoris at idle. The
`processoridle loop instructions control the processorto
`alternate a processor data output between outputstates.
`’ The processor data output
`thus alternates between
`states wheneverthe processoris idle, and remains in the
`same state when the processor is performing useful
`tasks. A frequency counter or other indicating device
`responsive to the rate of processor data output state
`changedirectly indicates the amount oftime the proces-
`sor is idle relative to the total amount of processing
`time. Since the change ofstate, notthe stateitself, of the
`data outputis detected, it does not matter whatstate the
`data output is left in when the processor is interrupted
`from performing the idle loop instructions.
`
`22 Claims, 2 Drawing Sheets
`
`10 SEC OR
`
`WHATEVER
`GATE TIME
`
`Google Exhibit 1006
`Google Exhibit 1006
`Google v. Valtrus
`|Googlev. Valtrus
`
`

`

`US. Patent
`
`May 8, 1990
`
`Sheet1of2
`
`4,924,428
`
`
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`PROGRAM|procramSTORE 2a 10
`
`CP
`
`q
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`PI
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`10
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`REGISTER
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`
`
`© COUNTER
`
`FREQ
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`~ |
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`SEC OR
`10
`WHATEVER
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`| | J
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`“
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`JUL
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`GENERATOR
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`22
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`law
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`24 ~—L
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`[FIG. 2
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`

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`Sheet 2 of 2
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`4,924,428
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`US. Patent
`
`MLLLILEpfLLULULSLT50%LE
`IFIG.3A|SUTAAAAAAN100%IDLE
`
`May8, 1990
`
`FIG.3B
`
`

`

`1
`
`4,924,428
`
`REAL TIME DIGITAL SIGNAL PROCESSOR IDLE
`INDICATOR
`
`FIELD OF THE INVENTION
`This invention relates to arrangements which mea-
`sure the loading of a digital signal processor.
`BACKGROUND AND SUMMARYOF THE
`INVENTION
`
`10
`
`2
`processing time for each sample. Processor loading
`would then be approximately 50% (or perhapsslightly
`above 50% dueto additional overhead tasks the proces-
`sor must perform). If the incoming signal sampling rate
`is increased to one sample every 0.5 milliseconds, the
`processor loading will increase to around 100%.
`Excessive processor loading is potentially extremely
`detrimental. In the filtering example, excessive loading
`of the processor may cause data to be lost and/orintro-
`duce inaccuracies in the filtering process. If the proces-
`sor is fully but not excessively loaded by its real time
`processing functions, it may have insufficient additional
`capacity to perform otherfunctionsit is called upon to
`perform. On the other hand, faster processors are typi-
`cally much more expensive (and may not even be avail-
`able in someapplications), and in a cost effective design
`it is generally desirable to use components having capa-
`bilities on the same order as the demands placed upon
`them.
`Unfortunately, it is not always possible to accurately
`predict how muchloading a given processor will expe-
`rience while performing given real time functions. Typ-
`ical complex algorithms perform a variable number of
`instructions on input data depending upon factors
`which maybedifficult or impossible to accurately take
`into account. Computer simulations are helpful, but
`since they can only simulate actual operating conditions
`they may be inaccurate. It is therefore preferable to
`actually measure processor loading under various dif
`ferent operating conditions.
`Diagnostic programs which run concurrently with a
`processor’s normal programming in order to measure
`processor loading are generally known. This type of
`diagnostic program may be called by an operating sys-
`tem program (if one is provided), or alternatively, may
`be interrupt driven and called periodically (e.g., when-
`ever a timer times out). The diagnostic program may
`measure various parameters of processor loading (e.g.,
`count processor cycles, and/or read the contents of
`processor workareas such as status register, stack con-
`tents, and the like) and, based on these (and other) pa-
`rameters, calculate an indication of instantaneous or
`average loading. A history of such indications may be
`stored and analyzed to provide a measure of processor
`loading under various operating conditions.
`Unfortunately, such diagnostic programs are gener-
`ally complex and typically themselves add significantly
`to processor loading—causing the indications they pro-
`vide to be inaccurate in some circumstances and adding
`to processor loading during measurements. A program
`which determines processor loading by counting pro-
`cessor cycles may underestimate the loading of a very
`busy processor because the processor may haveinsuffi-
`cient resources to increment the cycle counter. A fur-
`ther shortcoming of such diagnostic programsis that
`they attemptto estimate how muchofthe time a proces-
`sor is busy—whereas in most cases a more relevant
`inquiry is how muchtime the processoris not busy (and
`is therefore available to perform additional tasks).
`It would be highly desirable to provide a cost effec-
`tive arrangement which measures average processor
`loading and yet is non-invasive in that it is completely
`transparent to the operation of the processor(i.e., does
`not itself add to processor loading). Such an arrange-
`ment would be even moreuseful if it were capable of
`directly measuring the amount ofavailable processing
`
`The need often arises to measure the available pro-
`cessing capacity of a computer. Digital signal proces-
`sors (e.g., microprocessors) have become commonplace
`in virtually every type of electronic equipment. Such
`processors can be used to perform a variety of func-
`tions. The flexibility provided by a processor is often
`advantageously used to augmentthe functions provided
`by a system, or to perform those functions using com-
`plex algorithms.
`As a simple illustration, suppose one is designing a
`band passfilter for speech signals in a communications
`system. An analog bandpass filter constructed using
`operational amplifiers, resistors, and capacitors is one
`design option that is quite cost effective and provides
`suitable performance in many applications. To increase
`flexibility and performance, however, one might choose
`digital filtering techniques instead of analog techniques.
`In digital filtering, the filter characteristics are deter-
`mined not by the values and configurations of amplifi-
`ers, resistors and capacitors, but by the program control
`steps performed by a digital signal processor(e.g., a
`microprocessor or some other device capable of pro-
`cessing digital signals). Thefiltering characteristics of a
`digital filter (e.g., frequencyroll-off, “‘corner” frequen-
`cies, and the like) may be changed simply by modifying
`the programming executed by the processor—adding
`tremendousflexibility to the system.
`There is typically a desire to take advantage of the
`capabilities of the processor to the fullest extent possi-
`ble. The same processor used to perform the filtering
`can also be used to perform other related (and even
`unrelated) functions. For example, it may be desirable
`to use the processor to generate signaling tones for
`various applications, to provide system status informa-
`tion (e.g., to illuminate indicators or drive alphanumeric
`displays), to receive and process user commands,orthe
`like. The processor can be used to perform far more
`complex filtering and other functions than could be
`performed cost effectively with analog circuitry.
`Unfortunately, not all program codeis as efficient as
`it could be, and evenefficient code performing complex
`functions in real time can cause excessive processing
`loading. Processors have minimum “cycle times” (the
`time the processor requires to execute a single program
`control instruction). In the digital filtering example, the
`processor must process incoming signals in real timein
`addition to performing any “overhead”andothertasks.
`Processor “loading” (typically measured in percentage
`of maximum loading) depends upon the incoming data
`rate, the efficiency and complexity of the program con-
`trol software, and the speed of the processor.
`Asa simple example, suppose the processor is capable
`of executing an instruction every microcsecond (10-6
`seconds) and the incoming signal! to be filtered is sam-
`pled once every millisecond (10-3 seconds). Suppose
`further that the filtering software performs an average
`of 500 instructions on each incoming sample—requiring
`a total time of 500 10-6 seconds =0.5 milliseconds of
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`4
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`DETAILED DESCRIPTION OF THE
`DRAWINGS
`
`3
`capacity under a variety of different operating condi-
`tions.
`The present invention provides these and other ad-
`vantageous features by including diagnostic instructions
`in the processor “idle loop.”
`A processor does not cease performing instructions
`whenit is not busy, but instead jumps or “traps” to a
`so-called “idle loop” wheneverit is idle. The idle loop
`generally consists of instructions which perform no
`useful function (e.g., “no operation,” delay and/or jump
`instructions). When the processor must perform a func-
`tion, it receives an “interrupt”—at which time it ceases
`performing instructions in the idle loop and begins per-
`forming other, useful program control instructions. The
`next time the processor has no further tasks to perform,
`it once again returnsto its idle loop.
`The present invention includes instructions in the
`processor idle loop which control the processor (or
`external circuitry associated with the processor) to
`measure the amount (or percentage) of time the proces-
`sor operates in the idle loop. In the preferred embodi-
`ment, instructions in the processor idle loop control the
`processorto alternate a processor data output between
`output states. The processor data output alternates be-
`tween states whenever the processor is idle, and re-
`mains in the same state when the processor is perform-
`ing useful tasks. A frequency counter or other indicat-
`ing device (e.g., a light emitting diode) responsive to the
`rate of processor data output state change may be used
`to directly indicate the amount of time the processoris
`idle relative to the total amount of processing time.
`Since the changeofstate, not the state itself, of the
`data outputis detected, it does not matter whatstate the
`data outputis left in when the processor is interrupted
`from performing the idle loop instructions (by design,
`the priority associated with executing idle loop instruc-
`tions is lower than the priority associated with execut-
`ing any otherinstruction).
`Because the processor performsthe idle loop instruc-
`tions only whenit has nothing else to do, the additional
`idle loop instructions add nothing to processor loading
`and the load detecting arrangementaccordingly is com-
`pletely transparent to the operation of the processor.
`Moreover, the idle loop instructions directly measure
`the amountof time the processor spendsin an idle state
`relative to the total amount of processing time—and
`therefore provide an extremely useful, direct indication
`of spare processing capacity. These advantagesare all
`provided by an arrangement which adds only minimal
`cost to the processor system.
`These and other features and advantagesof the pres-
`ent invention may be better and more completely appre-
`ciated by referring to the following detailed description
`of presently preferred exemplary embodiments in con-
`junction with the appended sheets of drawings, of
`which:
`FIG. 1 is a schematic block diagram of a presently
`preferred exemplary embodimentof the present inven-
`tion;
`FIG.2 is a schematic flowchart of exemplary pro-
`gram control steps executed by the processor shown in
`FIG.1 during idling; and
`FIGS. 3A and 3B are exemplary load-indicating out-
`put waveforms produced by the processor shown in
`FIG. 1.
`
`FIG.1 is a schematic block diagram ofthe presently
`preferred exemplary embodiment of a digital signal
`processing system 10 in accordance with the present
`invention. System 10 includes a central processing unit
`(“CPU”) or processor 12. Processor 12 may, for exam-
`ple, be a conventional microprocessor including a read
`only memory program store 12g, internal registers and
`an arithmetic logic unit, etc.—or virtually any other
`type of device which processes digital signals. A con-
`ventional clock signal generator 13 producesa periodi-
`cally-alternating digital clock synchronization signal
`which drives processor 12. The frequency (that is—the
`period) of this clock signal determines the time it takes
`for the processor 12 to execute each of its program
`control instructions.
`In the preferred embodiment, processor 12 may be
`connectedto a variety of associated conventional exter-
`nal circuits which perform various desired functions.
`For example, if processor 12 is to be used to provide
`digital filtering, it may be connected to the output of an
`analog-to-digital converter or other source ofdigitized
`signals (not shown). Processor 12 may also be con-
`nected to display devices, input/output peripheral de-
`vices, or virtpally any of the thousands of different
`devices designed to be interfaced with a processor (all
`as is well known to those skilled in this art).
`In the preferred embodiment, processor 12 includes
`at least one unused data output connection P1 whichis
`connected to the input of a conventional input/output
`(I/O) register 14. I/O register 14 is sensitive to the
`“edges” (transitions) of the P1 output of processor 12
`and produces an output signal “BIT” which changes
`state in response to those edges. In the preferred em-
`bodiment, register 14 buffers the signal outputted at the
`processor P1 data output, but does not alter the fre-
`quencyof that signal (and may but need not necessarily
`synchronize the signal to the processor clock).
`The register 14 “BIT” output is connected to the
`input of a frequency counter 16 operating as an event
`counter with a fixed gate time(of, e.g., 10 seconds). The
`“BIT”signal output of register 14 is also connected to a
`visual indicating circuit 18 (which can conveniently be
`provided on the same board as processor 12) providing
`a rough visual indication of processor idle percentage.
`Indicating circuit 18 in the preferred embodiment
`includes an exclusive OR (“XOR”) gate 20 the inputs of
`which are connected across a resistor 22. The “BIT”
`signal is connectedto a first input of XOR gate 20, and
`a second input of the XOR gate is connected through a
`capacitor 24 to ground potential. This input configura-
`tion of XOR gate 20 causes the XOR gate to produce a
`pulse whenevera transition occurs in the “BIT”output
`signal (since the XOR gate first
`input
`immediately
`changeslevels to track a level change of the “BIT”
`signal, but the gate second input changesstate only after
`a delay determined by the RC time constantofresistor
`22 and capacitor 24).
`The output of XOR gate 20 is connected through a
`current limiting series resistor 26 to the anodeofa light
`emitting diode (LED) 28—the LED cathode being
`connected to ground potential. An optional driver/-
`buffer amplifier 30 may be used to connectthe output of
`XORgate 20 to the frequency counter 16 inputin lieu of
`a direct connection between the counter input and the
`register 14 “BIT” signal output.
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`instructions one time is four microseconds, anda single
`Aswill be understood by those skilled in the art,it is
`loop execution will cause data output P1 to alternate
`not necessary to provide both frequency counter 16 and
`once between logic level 0 and logic level 1 (e.g., from
`indicating circuit 18 in the preferred embodiment, since
`0 to 1 to 0, or from 1 to 0 to 1)— resulting in a signal of
`both are used to indicate the same information. In the
`preferred embodiment, frequency counter 16 is only
`one-quarter the processor clock frequency being gener-
`connected when an exact load measurementis desired,
`ated whenever (and only when) the processor has noth-
`while indicating circuit 18 is continuously connected to
`ing to do andis idling.
`1/Oregister 14 so as to provide a constantvisual indica-
`The signal present on the processor P1 output does
`tion of processor idle percentage.
`not have a 50% duty cycle in the preferred embodiment
`FIG. 2 is a schematic flowchart of exemplary pro-
`even when processor 12 is 100% idling and the idle
`gram control steps performed by processor 12 when-
`endless loop steps shown in FIG. 2 are performed con-
`ever the processor is in an idle state. In the preferred
`tinuously. This is because the P1 output state remains
`embodiment, processor 12 executes a section of code
`constant during the time processor 12 executes the
`beginning at a predetermined address(ofits associated
`“jump”instruction. In the preferred embodiment, the
`read only memory program store 12a) wheneverit is at
`P1 output rises to logic level 1 only while processor 12
`idle and is not required to perform useful tasks. Program
`executes the “reset” instruction (that is, during the pro-
`control instructions specifying the tasks shown in the
`cessor cycle immediately after the “set” instruction has
`FIG.2 flowchart are loaded into the program store 12a
`been performed). The P1 output thenfalls to logic level
`beginning at that predetermined address and are there-
`0 immediately after the “reset” instruction executes-
`fore executed whenever processor 12is at idle.
`—and remains at logic level 0 during the time the
`Processor 12 is “interrupt driven” in the preferred
`“jump” instruction is executed as well as during the
`embodiment, meaning that it begins executing program
`time the “set” instruction is performed. It is for this
`controlinstructions stored in a portion of program store
`reason that frequency counter 16 (and indicating circuit
`12a other than that portion storing the instructions exe-
`18) is sensitive to transitions in the “BIT”signal rather
`cuted during idle in response to the occurrence of an
`than to some other characteristic of that signal.
`external event (e.g., receipt of input data to be pro-
`Frequency counter 16 in the preferred embodiment
`cessed). Typically, a device external to processor 12
`directly indicates the percentage of time processor12 is
`(e.g., a conventional I/O controller not shown) pro-
`idle relative to the total processing time by couriting
`duces a signal which is applied to a processorinterrupt
`edges of the signal “BIT” produced by I/Oregister 14.
`request (IRQ) input. The presence of an active signal
`If the processor is 100% idle, then edges(e.g., leading
`level on this interrupt request input causes the micro-
`edges) will occur at the rate of 1/T whereTis the time
`processor to cease executing the “idle” routine and to
`required by processor 12 to execute the idle loop in-
`“trap” to an interrupt handler routine stored in a differ-
`structions once (e.g., 4 microseconds in the example
`ent portion of program store 12a. The interrupt handler
`given above—which equals the time required to per-
`routine either itself performs desired processing(e.g., to
`form a set bit instruction-+the time required to perform
`process the input data which caused an I/O interrupt to
`be generated) or alternatively,
`transfers program to
`a reset bit instruction+the time required to perform a
`additional routines (also stored in program store 12a)
`jumpinstruction in the preferred embodiment). As the
`processor 12 does more and more real work,it spends
`which perform the desired processing. When. process-
`ing is completed, processor 12 once again returns to
`less time executing the idle loop instructions—and the
`executing the idle routine.
`,
`edges occur proportionately less often in direct ratio to
`The FIG.2 idle routine is very short in the preferred
`the amountofidle time which remains.
`embodiment. A first step 50 writes a logic level one to
`Assume, for example, that frequency counter 16 re-
`processor data output connection P1. A second step 52
`ceives one pulse (edge) every 4 microseconds when
`writes a logic level zero to the processor data output
`processor 12 is 100% idle (as described in the example
`connection Pl. The routine then jumpsbackto the first
`above). Suppose frequency counter 16 has a gate time of
`step 50 to repeat steps 50, 52.
`10 seconds (selected to provide a desired degree of
`The following are exemplary mnemonic instructions
`averaging over time). With processor 12 100% idle,
`for performing the steps shown in the
`frequency counter 16 will count 2.5 X 106 pulses (edges)
`over the ten second gate time (one pulse every 4 micro-
`seconds means 250,000 pulses every second, or 2.5 mil-
`lion pulses every ten seconds). Note thatit is helpful for
`this calculation to know (at least approximately) the
`relationship between the processor clock frequency and
`the gate time, as well as the number of clock cycles
`required to execute the idle loopin its entirety. A wave-
`form of the “BIT”signal for 100% idling of processor
`12 is shown in FIG.3A.
`Suppose frequency counter 16 counts 1.25106
`pulses (edges) during its ten second gate time. This
`count indicates that over the ten second gate time, pro-
`cessor 12 was 50% idle on the average. As is shown in
`FIG. 3B, this 50% idling condition does not halve the
`instantaneous frequency of the “BIT” signal. Rather,
`the “BIT”signal is generated at substantially the same
`frequency whenever processor 12 is idling in the pre-
`ferred embodiment. However, processor 12 ceases to
`producethe “BIT”signal altogether during times when
`
`The steps shownin the FIG. 2 routine form an end-
`less loop that causes processor data output P1 to “tog-
`gle” (that is—alternate between binary values 0 and 1)
`at a rate proportional to the processor clock rate when-
`ever the processor 12is idling, and causes data output
`P1 to remain constant whenthe processoris performing
`useful tasks. For example, assume processor 12 has a
`one megahertz clock frequency, executes the “set” and
`“reset” commands each in one cycle time (one micro-
`second), and executes the “jump” command in two
`cycle times (two microseconds). Thetotal time required
`to execute the “idle loop” consisting of these three
`
`ADDRESS
`x
`X+1
`X+2
`
`FIG.2 flowchart:
`INSTRUCTION
`Set Pl
`Reset Pl
`Jump to Address X
`
`>
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`

`

`7
`it is performing real work(i.e., useful tasks) rather than
`idling. When the frequencyof the “BIT”signal is aver-
`aged (integrated) over a time period whichis long rela-
`tive to the time between processor clock pulses, the
`result is a highly accurate indication of average proces-
`sor idle percentage.
`The indication provided by LED 28 wil! obviously
`not provide as accurate an estimate of processor idle
`time as that provided by frequency counter 16. How-
`ever, the LED 28 does provide an indicator which is
`also very helpful. If LED 28 is fully lit, processor 12is
`nearly 100% idle (the LED will actually have an on-off
`duty cycle of about 50% under this condition, but the
`alternations are so rapid as to be undetectable by the
`human eye). If LED 28 is dark or nearly dark, processor
`12 is 0% idle. If LED 28 is at half brightness compared
`to the 100% condition, processor 12 is operating at 50%
`idle.
`In someapplications it might be desirable to substi-
`tute a conventional frequency ratio detector for fre-
`quency counter 16. Such a detector may compare the
`ratio of the processor clock frequency to the frequency
`of the “BIT” signal to provide an indication of the
`percentage of processor time spent idling.
`While the invention has been described in connection
`with whatis presently considered to be the most practi-
`cal and preferred embodiments, it is to be understood
`that the invention is not to be limited to the disclosed
`embodiments, but on the contrary, is intended to cover
`various modifications and equivalent arrangements in-
`cluded within the spirit and scope of the appended
`claims.
`WhatI claim is:
`1. An arrangement for measuring the percentage of
`time a digital signal processor is idle comprising:
`a digital signal processor having an output terminal
`and including meansfor executing program control
`instructions to perform predefined useful tasks;
`said digital signal processor further including idle
`loop executing means for executing idle loop pro-
`gram control instructions wheneversaid processor
`is not busy performing said useful tasks, said idle
`loop executing means for alternating the signal
`levelat said digital signal processor output terminal
`between first and second binary levels whenever
`said processoris idling, for alternating the level at
`said processor output terminal at a rate over time
`which directly indicates the spare processing time
`of said digital signal processor, said digital signal
`processor maintaining said processor output termi-
`nal at a constant signal level wheneversaid proces-
`sor performs said predefined tasks; and
`’ means external to said processor and connected to
`said processor output terminal for producing an
`indication of said spare processing time in response
`to the rate over time at which said processoralter-
`nates the signal level at said processor output ter-
`minal between said first and second binary levels.
`2. An arrangementas in claim 1 wherein said indica-
`tion producing means includes frequency counting
`means for counting the numberoftimes said processor
`output terminal level alternates over a predetermined
`gate time.
`—
`3. An arrangementas in claim 1 wherein:
`said arrangement further includes clock generating
`means connectedto said digital signal processor for
`controlling the rate at which said executing means
`executes said program control instructions and the
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`tate at which said idle loop executing means con-
`tinually alternates the level at said processor output
`terminal when said processoris idle; and
`said frequency counting gate time has a predeter-
`. mined relationship to said controlled rate.
`4. A real time digital signal processing system com-
`prising:
`memory meansfor storing an idle loop program con-
`trol routine and a further program control routine
`defining input signal processing tasks;
`a processor means connected to said memory means,
`also connected to receive externally generated
`inputsignals, and having a data output connection,
`for processing said input signals substantially in
`real time in accordance with said further program
`control routine and for performing said idle loop
`program control routine whenever not occupied
`processing said input signals, said idle loop pro-
`gram control routine causing said data output con-
`nection to continually alternate between first and
`second states during the time said processor is per-
`forming said idle loop program routine; and
`indicating means connected to said output connection
`for producing an indication of the percentage of
`time said processor performs said idle program
`control routine in response to changes in said data
`output connection state.
`5. A system as in claim 4 wherein said indicating
`means includes means for counting the numberof data
`output connection state changes over time.
`6. A system as in claim 4 wherein said indicating
`meansindicates the time said processor means performs
`said idle loop program control routine over time.
`7. A system as in claim 4 wherein said idle loop pro-
`gram control routine defines:
`a first idle task which causes said processor data out-
`put connection to rise to a logic level 1;
`a second idle task which causes said processor data
`output connection to fall to a logic level 0; and
`a third idle task which causes said first and second
`idle tasks to be periodically executed whenever
`said processor is idle and is not performing said
`further tasks.
`8. A system as in claim 4 wherein said indicating
`meansincludes optical indicating means for indicating
`the frequency of said data output connection state
`changes.
`9. A system as in claim 4 wherein:
`said system further includes means for generating an
`alternating clock synchronization signal having a
`preset frequency, said processor means being con-
`nected to receive said clock signal and performing
`said idle and further tasks at a rate responsive to
`said clock signal; and
`said indicating means includes means for determining
`the ratio between the frequency at which said pro-
`cessor data output connection changes state and
`the clock signal frequency.
`10. A system as in claim 4 wherein processing of said
`idle loop program control routine does not increase the
`effective loading of said processor means.
`11. A system as in claim 4 wherein:
`said processor meansis interrupt driven, receipt of an
`input signal causing said processor means to exe-
`‘cute said further program control routine, said
`processor means performing said idle loop pro-
`gram control routine whenever no interrupt
`is
`occurring and performanceofsaid further program
`
`

`

`9
`control routine in response to previously received
`interrupts is completed.
`12. A system as in claim 4 wherein said indicating
`means includes:
`an exclusive OR gate having first and second input
`terminals and an output terminal, said first input
`terminal being coupled to said processor means
`data output;
`a resistor connected between said exclusive OR gate
`first and second input terminals; and
`a capacitor connected between said exclusive OR
`gate second input terminal and ground potential.
`13. A system as in claim 12 wherein said indicating
`means further includes a light emitting diode connected
`to said exclusive OR gate output terminal.
`14. A system as in claim 4 wherein said processor data
`output changesstate asymmetrically when said process-
`ing means is 100% idling.
`15. A system as in claim 4 wherein said idle tasks
`cause said data output to changestate at a preset instan-
`taneousrate, the average rate at which said data output
`changes state being directly proportional to the dura-
`tion said processor means performs said idle routine
`over time.
`16. A digital signal processing system comprising:
`a digital signal processing means of the type which
`alternately operates in a busy state and in an idle
`state, said processing means for processing input
`signals applied thereto when operating in said busy
`state, said processing means for performing an idle
`loop routine when operating in said idle state, said
`processing means including means for producing a
`continually alternating binary valued outputsignal
`whensaid processing meansis operatingin said idle
`state; and
`indicating means connected to receive said output
`signal for indicating the percentage of time said
`processing meansis operating in said idle state in
`
`10
`response to the rate overtime said output signalis
`alternated in response to said idle loop routine.
`17. A digital signal processing method comprising:
`(1) operating a digital signal processor alternately in a
`busy state and in an idlestate;
`(2) processing input signals with said processor when-
`ever said processor operates in said busystate;
`(3) producing a continually alternating binary valued
`output signal directly at an output terminal of said
`processor under control of a processor idle loop
`routine only when said processor operates in said
`idle state; and
`.
`(4) indicating the percentage of time said processor
`operatesin said idle state in response to the average
`rate over time said output signal is alternated by
`said step (3).
`18. A method as in claim 17 wherein said indicating
`step (4) includes counting the numberof transitions of
`said output signal occurring during a preset gate time.
`19. A method as in claim 17 wherein said indicating
`step (4) includes producing light every time said output
`signal changes value.
`20. A methodas in claim 17 further including:
`performing said processing step (2) in response to an
`interrupt request; and
`performing said producing step (3) after said process-
`ing step (2) finishes processing said input signals.
`21. A method as in claim 17 wherein said producing
`step (3) includes:
`(a) applying a logic level 1 to a data output of said
`processor;
`(b) applying a lo