US006166984A
`6,166,984
`[11] Patent Number:
`United States Patent
`Bohac, Jr.
`[45] Date of Patent:
`Dec. 26, 2000
`
`
`(15
`
`[54] NON-VOLATILE COUNTER
`
`[75]
`
`Inventor: Frank John Bohac, Jr., Tustin, Calif.
`
`Primary Examiner—Terrell W. Fears
`Attorney, Agent, or Firm—Blakely Sokoloff Taylor &
`Zafman LLP
`
`[73] Assignee: Custom Silicon Solutions, Inc.,
`Huntington Beach, Calif.
`
`[57]
`
`ABSTRACT
`
`[21] Appl. No.: 09/360,404
`
`.
`;
`;
`invention relates to a
`the present
`In one embodiment,
`particular configuration of a non-volatile counter, which
`significantly reduces the amount of area required for imple-
`mentationin an integrated circuit and improvesits reliability
`Jul. 23, 1999
`Filed:
`[22]
`of operation. This is accomplished by (1) replacing the
`Tint, C07 iccccccccssssscsssssssstsessetesneten G1IC 13/00
`FSU]
`volatile binary counter with a volatile counter coded for
`[52] US. Cl
`365/229; 365/226
`
`More equal distribution the changes in logic state over the
`[58] Field of Searchccs 365/51, 185.18,
`entire counter, (2) replacing the non-volatile latch circuit
`365/185.26, 185.27
`oe with a single non-volatile memory element, and (3) devel-
`oping testing techniques for complete and efficient testing of
`the critical non-volatile memory elements.
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,656,840
`
`8/1997 Yang ose eceeeeeecetenees 365/185.27
`
`22 Claims, 11 Drawing Sheets
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`Google Exhibit 1007
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`

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`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 1 of 11
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`6,166,984
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`Dec. 26, 2000
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`U.S. Patent
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`Dec. 26, 2000
`
`Sheet 3 of 11
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`6,166,984
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`DATAIN1
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`DATAIN2
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`DATAIN3
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`DATAIN4
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`205;
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`CINB
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`320
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`BUS INTERFACE
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`Figure 3
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`

`

`U.S. Patent
`
`Dec. 26, 2000
`
`Sheet 4 of 11
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`Dec. 26, 2000
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`Sheet 5 of 11
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`U.S. Patent
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`Dec. 26, 2000
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`U.S. Patent
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`Dec. 26, 2000
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`U.S. Patent
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`Dec. 26, 2000
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`Sheet 8 of 11
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`6,166,984
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`

`

`6,166,984
`
`1
`NON-VOLATILE COUNTER
`BACKGROUND
`
`1. Field
`This invention rclates to non-volatile clectronic counters
`in integrated circuits, more specifically, a counter which can
`store volatile digital data in a non-volatile register prior to
`power outage and can recall the data following the power
`outage.
`2. General Background
`Non-volatile counters implemented in integrated circuits
`typically consist of a volatile counter that has the capability
`of transferring its contents to a non-volatile register prior to
`powerbeing removed. When poweris restored, the contents
`of the non-volatile register (retained during the power off
`condition) are transferred back into the volatile counter and
`counting can continue where it ended prior to the disruption
`of power. This integrated circuit configuration is typically
`implemented with (i) binary volatile counter well known in
`the industry and (ii) one or more non-volatile registers
`(referred to as a “latch circuit”) as set forth in U.S. Pat. No.
`4,571,704.
`This latch circuit configuration is complex to design and
`occupies a large amount of area when implemented in an
`integrated circuit. Kor example, the latch circuit requires two
`non-volatile transistors to store its logic state during the
`power off condition, one for each side of the latch circuit.
`Often, since the non-volatile memory elements have a
`limited lifetime, two non-volatile transistors are used for
`each side of the latch circuit
`to provide more reliable
`operation through redundancy. Since the non-volatile tran-
`sistors used in the latch circuit are all relatively large, the use
`of four non-volatile transistors to store one bit of data is an
`inefficient use of area in the integrated circuit and results in
`a high implementation cost.
`There are also reliability concerns for this implementa-
`tion. Under conventional memorydesigns, non-volatile tran-
`sistors placed in a parallel redundant mannerare tested in a
`collective manner by monitoring a voltage level at a shared
`node. These transistors cannot be tested independently after
`manufacture. One difficulty is that that non-volatile transis-
`tors typically reside in an “open” or non-conducting state
`upon failure. Therefore, if one of the transistors has failed
`and no redundancyis present,the testing may still reveal that
`the latch circuit is operating properly. This has an effect on
`long term reliability of the non-volatile counters.
`Also, a general reliability problem in non-volatile
`counters is that the volatile counter is typically coded in
`binary, where the least significant bits change state substan-
`tially more often than the mostsignificantbits in the counter.
`Therefore, when information in the counter is transferred
`into the non-volatile latches, the latches receiving the Icast
`significant bits change state more often than those receiving
`the more significant bits. As a result, the latches responsible
`for storing the least significantbit of the volatile counter will
`normally fail well before latches associated with the other
`bits. In manysituations, the volatile counter is implemented
`in a binary coded decimal configuration (a decimal
`configuration, with each decimal coded in binary and often
`referred to as a “BCD”configuration) rather than a straight
`binary counter. The reliability problem is the same for this
`configuration, as the least significant bits of each decimal
`stage change state in a binary fashion and the lower order
`decimal stages change state more often than the higher order
`stages.
`
`SUMMARY
`
`In one embodiment, the present invention relates to a
`particular configuration of a non-volatile counter, which
`
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`significantly reduces the amount of area required for imple-
`mentation in an integrated circuit and improvesits reliability
`of operation. This is accomplished by (1) replacing the
`volatile binary counter with a volatile counter coded for
`more equal distribution the changes in logic state over the
`entire counter, (2) replacing the non-volatile latch circuit
`with a single non-volatile memory element, and (3) devel-
`oping testing techniques for complete and efficient testing of
`the critical non-volatile memory elements.
`This configuration for the volatile counter significantly
`improvesthe reliability by reducing the maximum number
`of times bits of the non-volatile memory clementare likely
`to change during the lifetime of the volatile counter. By
`more equally distributing the count overall the bits of the
`register,
`the typical characteristic for failure of the least
`significant bits is climinated. The decimal counting configu-
`ration is ideal for using this new counting algorithm sinceit
`requires the same numberof flip-flops as a (BCD) counter,
`yet reduces the maximum numberof state changes by a
`factor of approximately 2.5.
`The non-volatile memory element in this invention is a
`single element, such as a single non-volatile memory tran-
`sistor. This transistor is programmed to reside in either an
`ONor OFFstate, depending on the state the volatile counter
`at power-down. At power-on,a bias current is applied to the
`non-volatile transistor to determine its state, either ON or
`OFF. This increased simplicity, compared to the prior art,
`which consisted of two non-volatile transistors configured in
`a latching circuit, would result in reduced silicon area which
`makesthe integrated circuit in whichit is fabricated smaller
`and less expensive. In addition, it is simple in this case to add
`parallel redundancy to improve the reliability of the non-
`volatile transistor. Since there is only one non-volatile
`transistor, only one redundanttransistor would be needed.
`Also, since the non-volatile transistors are not in a latching
`configuration,
`it
`is easy to test
`them individually after
`manufacture to assure both are working. This assures the
`redundancy, and hence the required reliability is achieved.
`BRILI DESCRIPTION OP THE DRAWINGS
`
`The features and advantages of the present invention will
`become apparent from the following detailed description of
`the present invention in which:
`FIG. 1 is an illustrative embodiment of a non-volatile
`
`counter employed in an odometer system.
`FIG. 2 is an illustrative block diagram of an N-stage
`non-volatile binary coded decimal (BCD) counter including
`a pseudo gray-to-BCD (PGBCD) converter.
`FIG. 3 is an illustrative block diagram of an embodiment
`of a single stage of the non-volatile BCD counter of FIG. 2.
`FIG. 4 is an illustrative block diagram of an embodiment
`of a non-volatile memory cell and programming and reading
`circuitry employed in the single stage of FIG. 3.
`FIG. 5 is an illustrative diagram of READ waveforms for
`understanding the operation of the non-volatile memory cell
`of FIG. 4.
`
`FIG. 6 is an illustrative block diagram of an embodiment
`of a non-volatile memory cell with redundancy and pro-
`grammingandreading circuitry employedin the single stage
`of FIG. 3.
`
`VIG. 7 is an illustrative diagram of an embodiment of a
`non-volatile memory transistor test waveform to test the
`non-volatile transistors associated with the non-volatile
`
`memory ccll of FIG. 6.
`FIG. 8 is an illustrative diagram of an embodiment of
`programming waveforms necessary to program the non-
`volatile memorycell of FIG. 4.
`
`

`

`6,166,984
`
`3
`FIG. 9 is anillustrative block diagram of an embodiment
`of a pseudo gray decade counter of FIG. 3 and associated
`input/output circuitry of FIG. 3.
`FIG. 10 is an illustrative block diagram of an embodiment
`of circuitry of the bus interface of FIG. 3.
`FIG. 11 is an illustrative block diagram of an embodiment
`of logic forming the PGBCD converter of FIG. 2.
`DETAILED DESCRIPTION
`
`Herein, embodiments of an improved non-volatile counter
`are illustrated in FIGS. 1-11. The non-volatile counter is
`
`designed to significantly reduce the amount of area needed
`for implementation in an integrated circuit and to improve
`reliability. This is accomplished by implementing (i) a
`counter that more cqually distributes changesin logic state
`over the entire counter in lieu a volatile binary counter and
`Gi)
`a single non-volatile memory element
`in lieu of a
`non-volatile latch circuit. Also, the improved non-volatile
`counter provides for complete and efficient testing of the
`critical non-volatile memory elements.
`In the following description, certain terminology is used
`to describe characteristics of the present invention as well as
`its functionality. For example, a “counter” includes logic
`that adjusts a count value by incrementing or decrementing
`the count value. The term “high” indicates that a signalis at
`a predetermined voltage (e.g., 4-5 volts). The term “low”
`indicates that a signalis at a voltage ranging from zero to one
`volt. Of course, these voltage levels may be adjusted for
`higher and/or lower power supply voltages. A signal
`is
`chosen to be “active low” when thelast letter of the signal
`name ends with the letter “B”.
`
`Referring to FIG. 1, an illustrative embodiment of a
`non-volatile binary coded decimal (BCD) counter 100 is
`shown. Herein, counter 100 is used as an odometer system
`of a vehicle. Distance pulses from a vehicle sensor are
`counted by non-volatile BCD counter 100 and the result is
`displayed in an odometer display 110 via a display driver
`120 of a vehicle control panel 130. Non-volatile BCD
`counter 100 stores the counted miles in non-volatile memory
`whenthe vehicle poweris removed andrestores that mileage
`when the poweris restored.
`Referring now to FIG. 2, an embodimentof non-volatile
`BCD counter 100 of FIG. 1 is shown. Herein,
`in this
`embodiment, non-volatile BCD counter 100 comprises an
`N-stage pseudo gray counter 200 and a pseudo gray-to-
`binary coded decimal (PGBCD)converter 250. Each stage
`205,-205,, of pseudo gray counter 200 is coupled in parallel
`to a clock signal line 205 anda test signal line 210. Clock
`signal line 205 provides a standard clock signal (CLK) for
`synchronization of N-stages of pseudo gray counter 200
`without prior loading on carry signals. Test signal line 210
`places BCD counter 100 into a test mode whentest signal
`line 210 is active.
`DATA/ADDRESS line 215 receives data or address as
`input to select the N™ stage of pseudo gray counter 200.
`READ/WRITEcontrol line 220 controls the operations of
`pseudo gray counter 200. Most carry signal inputs (CINB)
`and carry signal outputs (COUTB) 230 are provided to
`successive stages of pseudo-gray counter 200. Of course,
`CINB 225 ofa first stage 205, is tied low and remainsactive
`while CINB signals for the remaining N-1” stages are
`provided from COUTRsignals of a proceeding stage.
`As shown, DATA/ADDRESSline 215 selects from which
`stage 205,—205,, binary output bits are placed on output bus
`235. Herein, output bus 235 is represented by four (4)bit
`lines for configuration as a binary decimal counter, although
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`the invention may be employed with different-sized
`counters. The output bits placed on output bus 235 are in
`accordance with a coding is similar to a well-known Gray
`coding (referred to a “pseudo-gray” code) and not standard
`binary coding. This pseudo-gray code is illustrated as fol-
`lows:
`
`Decimal Count
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`
`Binary Code
`o000
`0001
`0010
`0011
`0100
`0101
`0110
`0111
`1000
`1001
`
`Pseudo-Gray Code
`9000
`0001
`0011
`0110
`0100
`1000
`1001
`1011
`1110
`1100
`
`For each stage of pseudo gray counter 200, it is contem-
`plated thatits least significant bit changes state four (4) times
`in a ten (10) count as compared to ten (10) times for a
`standard binary counter. Thus, pseudo gray counter 200
`reduces the maximum numberof times anyparticular bit
`changes. This will improve thereliability of the non-volatile
`register in whichthebits are stored since typical non-volatile
`counters are limited in the maximum numberoftimes they
`may changestate.
`As still shown in FIG. 2, pseudo gray-to-BCD (PGBCD)
`converter 250 converts this pseudo-gray code routed to bus
`input port 260 to standard binary coding producedat output
`270. In this case, there is no provision for driving a display
`and the outputs would probably be read by a computer or
`processor.
`FIG. 3 illustrates an embodimentofa single stage (e.g.,
`first stage 205,) of pseudo-gray counter 200 of FIG. 2. Stage
`205, comprises a non-volatile (NV) memoryregister 310, a
`pseudo gray decade counter 320 and a businterface 330. NV
`memoryregister 310 further comprises non-volatile memory
`cells (NV CELL) 311-314. The contents of non-volatile
`counter 100 of FIG. 1 are transferred in parallel between
`non-volatile memory register 310 and pseudo-gray decade
`counter 320 over a first bus 340 at power-up and over a
`second bus 350 at power-down.
`For example, information is transferred to non-volatile
`memory register 310 via QxB ports 321 and DATAINxports
`315 at power-down (where “x” ranges up to the number of
`bits supported by NV cells 311-314). The information is
`returned to pseudo-gray decade counter 320 at power-up via
`DATAOUTx and NVOUT«ports 316 and 322, respectively.
`If each stage 205,-205,, of FIG. 2 is used in this manner,
`non-volatile counter 100 of FIG. 1 will retain ils count
`
`during power-down, and will start with that count when
`poweris returned. In this embodiment, bus interface 330 is
`used to transfer incoming information (e.g., pseudo-gray
`code) to output bus 235 during a normal read operation.
`Referring now to FIGS. 4 and 5, an embodiment of a
`non-volatile memory register (e.g., NV cell 311) is shown.
`NV cell 311 comprises (i) a non-volatile transistor 400, (ii)
`a programming circuit 410 and (iii) an output readingcircuit
`450. Programming circuit 410 is used to program non-
`volatile transistor 400 and includes PMOStransistors 420,
`425 and NMOStransistors 430, 435, 440, 445 in this
`embodiment. Transistors 420, 425, 430 and 435 constitute a
`cross-coupled level shifter. Output reading circuit 450
`includes a PMOStransistor 455, an NMOStransistor 460
`and an inverter 465.
`
`

`

`6,166,984
`
`5
`As shownin FIG. 5, waveformsillustrate how NV cell
`311 of FIG. 4 functions during a read operation where
`PMOStransistor 455 acts as a current source with the bias
`current input from READIB 500. A control gate (V,) 401
`and source (V,) 402 of non-volatile transistor 400 are at
`ground (GND).
`If non-volatile transistor 400 has been
`programmed with a negative threshold, it will be turned on.
`Thus, when READBinput 510 goes low (turning off NMOS
`transistor 460), it will keep the input (V,) to inverter 465 low
`and DATAOUT520 high. If non-volatile transistor 400 has
`been programmedto a positive threshold, it will be turned
`off so that when the READBinput 510 goes low, the input
`(V,,) to inverter 465 will rise due to the current from PMOS
`transistor 455 and DATAOUT 520 will go low. During the
`read operation, STOREB 530 is high and VPP 540 is at
`GND,assuring that control gate (V,) 401 of non-volatile
`transistor 400 is at GND. Therest of the circuitry in FIG. 4
`is used for programming.
`Another non-volatile transistor can be added to NV cell
`311 to provide redundancy and thereby improvereliability.
`This non-volatile memory cell with redundancy is shown in
`FIG. 6. Two non-volatile transistors 600 and 610 are coupled
`in parallel except for the sources, which are brought out
`separately as test lines LGND 620 and RGND 6390. Therest
`of the circuitry is the same as NV cell 311 of FIG. 4.
`Bringing the sources out separately allows for an indepen-
`dent test of non-volatile transistors 600 and 610.
`
`Referring to FIG. 7, an embodiment of non-volatile
`memory transistor test waveforms is shownin orderto better
`illustrate how non-volatile memorytransistors 600 and 610
`of FIG. 6 may be tested. If one of non-volatile transistors
`600 or 610 is shorted, it will be caught in normal read
`testing. However, an open (or non-programmable) non-
`volatile transistor cannot be detected during the normal read
`(due to the redundancy). The non-volatile memorytransistor
`test waveforms of FIG. 7 illustrate how to test for this
`condition. First, the non-volatile memory cell with redun-
`dancy is programmed with negative thresholds in non-
`volatile transistors 600 and 610. Normal read commandsare
`
`applied to all inputs except LGND 620 and RGND 630.
`When LGND 620 is pulsed high and RGND remainslow,it
`tests non-volatile transistor 610. When RGND 630is pulsed
`high and LGND remainslow,it tests non-volatile transistor
`600. If DATAOUT 640 goes low when oneof non-volatile
`transistor 600 or 610 is being tested, non-volatile transistor
`600 or 610 is open or not programmed adequately. Passing
`these tests assures that both non-volatile transistors 600 and
`610 are operational and the benefits of redundancy are
`available. The ability to fully test the redundancy of the
`non-volatile memory cell is a feature not practiced in the
`priorart.
`Referring now to FIGS. 4 and 8, to program a memory
`cell, the inputs READIB 500 and READB 510are held high
`at VDD. Data is input via the DATA and DATAB inputs 550
`and 560. When STORE input 570 is taken high, data is
`transferred via PMOStransistors 420 and 425 to cross-
`coupled NMOStransistors 430 and 435, whereit is latched.
`The input STOREB 530 is low, so that NMOStransistors
`440 and 445 are off. One side of this latch is connected to
`a diffusion underthe tunnel oxide (V,,,,,) 403 of non-volatile
`transistor 400, and the other side of the latch is connected to
`control gate (V,) 401 of non-volatile transistor 400. At this
`point, the programmingvoltageis only at the VDDlevel (not
`sufficient to program non-volatile transistor 400). The input
`VPP 540 begins the programming sequence at ground and
`then becomes negative to attain a sufficient voltage to
`program non-volatile transistor 400. This results in the
`
`6
`difference of the negative voltage (VPP) 540 and the positive
`voltage (VDD) being applied across the tunnel oxide of
`non-volatile transistor 400, programmingit to either an “on”
`state or an “off” state depending on the state of input DATA
`550. Note that if non-volatile transistor 400 is already in the
`same state to be programmed,there is no state change. This
`is an advantage over more typical memorycells, which are
`first erased and then rewritten with the same state informa-
`tion.
`
`Referring to FIG. 9, pseudo-gray decade counter 320 of
`FIG. 3 comprises a counter 700 and a small numberoflogic
`gatcs. Counter 700 includes a plurality of D-type flip-flops
`(DFF1-DFF4) 710-713 and NOR GATE720. The output of
`DFF1 710 dependson the state of DFF2 711 and DFF3 712.
`DFF2 711 and DFF3 712 are configured as a shift register.
`DFF4 713 toggles with the data from the output of preceding
`DFF3 712. Together, this circuitry generates the pseudo-gray
`code described earlier.
`The clock for DFF1 710, DFF2 711 and DFF3 712 is
`provided from NORgate 730 having inputs CLOCKN and
`CINB. CINB is an input carry signal from a preceding stage
`(or tied low) and CLOCKN isthe input clock signal. NOR
`gate 740 and NAND gate 750 receive an input CINB from
`a preceding stage (ortied low) and outputs from counter 700
`(Q4B, Q3B, Q2B) generate the carry output COUTB. This
`implementation is considerably less complex than a standard
`BCDcounter, saving area (costs) when implemented in an
`integrated circuit.
`Referring nowto FIG. 10, an embodimentof bus interface
`330 for a stage of pseudo-gray counter 200 of FIGS. 2 and
`3 is shown. In this embodiment, bus interface 330 comprises
`an AND gate 800, an inverter 810 and a plurality oftri-state
`inverters 820 (e.g., tri-state inverters 821-824). The function
`of bus interface 330 is simply to transfer data from an output
`of pseudo-gray decade counter 320 to output bus 235 of FIG.
`3.
`
`Finally, in FIG. 11, an embodiment of PGBCD converter
`250 of FIG. 2 is shown. Herein, the data on outputbus(e.g.,
`BUS1-4) 235 is converted from the pseudo-gray code to
`standard binary code typical of BCD counters. Combinato-
`rial logic (e.g., a collection of AND gates, NOR gates, XOR
`gates, and/orinverters, etc.) is used for this conversion. In
`this embodiment, the output (QxOUT, x=1, 2, 3, or 4) of
`PGBCD converter 250 is the following:
`Q1OUT=BUS1 XOR (BUS2 XOR BUS4);
`Q20UT=[NOT(BUS4) NOR QOUT1] XOR BUS2;
`Q30UT=NOT[((BUS2 AND BUS3) NOR BUS4) XOR
`BUS3]; and
`Q40UT=BUS3 AND BUS4.
`‘The present invention described herein may be designed
`in many different architectures and using many different
`components. While the present invention has been described
`in terms of various embodiments, other embodiments may
`come to mind to those skilled in the art without departing
`from the spirit and scope of the present
`invention. For
`example, the invention may be utilized in other types of
`counters besides BCD counters. The invention should,
`therefore, be measured in terms of the claims that follow.
`Whatis claimed is:
`1. Anon-volatile memorycell comprising:
`a programmable transistor to store a logic state during
`power off,
`the programmable transistor including a
`control gate and a diffusion under a tunnel oxide;
`a programmable circuit coupled to the control gate of the
`programmable transistor and the diffusion,
`the pro-
`gramming circuit to program the programmable tran-
`sistor; and
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`an output reading circuit coupled to a source and a drain
`of the programmable transistor.
`2. The non-volatile memorycell of claim 1, wherein the
`programmable transistor is a single non-volatile transistor.
`3. The non-volatile memorycell of claim 1, wherein the
`programming circuit includes a cross-coupled level shifter
`coupled to the control gate and the diffusion.
`4. The non-volatile memory cell of claim 3, wherein the
`cross-coupled level shifter applies one polarity of a most
`positive and a most negative potentials across the control
`gate and the diffusion.
`5. The non-volatile memory cell of claim 2, wherein the
`output reading circuit including
`a PMOStransistor coupled to the drain of the non-volatile
`transistor;
`a NMOStransistor coupled to the source of the non-
`volatile transistor; and
`an inverter coupled to a drain of the PMOStransistor,the
`drain of the non-volatile transistor and a drain of the
`NMOStransistor.
`
`6. The non-volatile memory cell of claim 1, wherein the
`programmable transistor includes a pair of non-volatile
`transistors having gates and drains in parallel and sources
`lacking parallelism.
`7. The non-volatile memorycell of claim 6, whereina test
`line is coupled to each source of the non-volatile transistors.
`8. A memory cell comprising:
`a transistor including a control gate and a diffusion under
`a tunnel oxide;
`a programming circuit coupled to the control gate of the
`programmable transistor and the diffusion; and
`an output reading circuit coupled to a source and a drain
`of the programmable transistor.
`9. The memory cell of claim 8, wherein the transistor is
`programmable.
`10. The memorycell of claim 9, wherein the program-
`mable transistor is a single non-volatile transistor.
`11. The memorycell of claim 8, wherein the programming
`circuit includes a cross-coupled level shifter coupled to the
`control gate and the diffusion.
`12. The memory cell of claim 11, wherein the cross-
`coupled level shifter applies one polarity of a most positive
`and a most negative potentials across the control gate and the
`diffusion.
`
`13. The memory cell of claim 8, wherein the output
`reading circuit including
`a PMOStransistor coupled to the drain of the transistor;
`a NMOStransistor coupled to the source of the transistor;
`and
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`an inverter coupled to a drain of the PMOStransistor, the
`drain of the transistor and a drain of the NMOS
`transistor.
`
`14. The memory cell of claim 9, wherein the program-
`mable transistor includes a pair of non-volatile transistors
`having gates and drains in parallel and sources lacking
`parallelism.
`15. The memory ccll of claim 14, whercin a test linc is
`coupled to each source of the non-volatile transistor.
`16. A non-volatile memory cell comprising:
`a programmabletransistor to store a logic state during
`power off the programmable transistor including a
`control gate and a diffusion under a tunnel oxide; and
`a programmable circuit coupled to the control gate of the
`programmable transistor, and the diffusion,
`the pro-
`grammable circuit to program the programmable tran-
`sistor.
`
`17. The non-volatile memory cell of claim 16, further
`comprising:
`an output reading circuit coupled to a source and a drain
`of the programmabletransistor.
`18. The non-volatile memorycell of claim 16, wherein the
`programmable transistor is a single non-volatile transistor.
`19. The non-volatile memorycell of claim 16, wherein the
`programmable circuit includes a cross-coupled level shifter
`coupled to the control gate and the diffusion, the crass-
`coupled level shifter applies on polarity of a most positive
`and a most negative potentials across the control gate and the
`diffusion.
`
`20. The non-volatile memorycell of claim 17, wherein the
`output reading circuit including
`a PMOStransistor coupledto the drain of the non-volatile
`transistor;
`a NMOStransistor coupled to the source of the non-
`volatile transistor; and
`an inverter coupled to a drain of the PMOStransistor, the
`drain of the non-volatile transistor and a drain of the
`NMOStransistor.
`
`21. The non-volatile memorycell of claim 16, wherein the
`programmable transistor includes a pair of non-volatile
`transistors having gates and drains in parallel and sources
`lacking parallelism.
`22. The non-volatile memory cell of claim 21, wherein a
`test
`line is coupled to each source of the non-volatile
`transistors.
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