`
`United States Patent
`McAniis et al.
`
`119
`
`[11] Patent Number:
`
`[45] Date of Patent:
`
`4,458,307
`Jul. 3, 1984
`
`[54] DATA PROCESSOR SYSTEM INCLUDING
`DATA-SAVE CONTROLLER FOR
`PROTECTION AGAINST LOSS OF
`VOLATILE MEMORY INFORMATION
`DURING POWER FAILURE
`
`[75]
`
`Inventors:
`
`James C. McAnlis, Bangor, Northern
`Ireland; Kuldip Kumar, Gateshead,
`England; Robert T. M. Gould,
`Downington, Pa.
`
`[73] Assignee:
`
`Burroughs Corporation, Detroit,
`Mich.
`
`[21] Appl. No.:
`[22] Filed:
`
`112,976
`
`Jan, 17, 1980
`
`Related U.S. Application Data
`Continuation-in-part of Ser. No. 944,481, Sep. 20, 1978,
`abandoned.
`
`[63]
`
`Foreign Application Priority Data
`[30)}
`Sep. 22, 1977 [GB] United Kingdom ............... 39465/77
`
`Tint, CIB cccsnesee GO6F 1/00; GO6F 13/00
`[SE]
`[52] US. Ch. once esesecereneeeerenreeee 364/200; 365/228
`[58] Field of Search ... 364/200 MSFile, 900 MSFile;
`365/228, 229; 371/66, 10
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`.........cccsseseceeers 364/200
`1/1965 Bade et al.
`3,167,685
`3,286,239 11/1966 Thompson et al. .
`-». 364/200
`3,321,747 5/1967 Adamson........
`s+, 364/200
`3,810,116 5/1974 Prohofsky...
`+ 365/228
`
`3,916,390 10/1975 Changet al
`e+ 365/228
`3,959,778
`5/1976 Brette......
`w+ 364/200
`4,004,283
`1/1977 Bennett et
`al. .......sccsseers 364/200
`
`
`
`
`2/1978 Fox et ab. oc scnsesesseeeeneee 364/200
`4,075,693
`vee 364/200
`4,096,560 6/1978 Footh .............
`
`4,307,455 12/1981 Juhasz et al...ee 371/66 X
`
`OTHER PUBLICATIONS
`
`IBM Tech. Discl. Bull., vol. 19, No. 11, Apr. 1977,
`“Auto Initial Microprogram Load”, Houdeket al., pp.
`4339-4346.
`IBM Tech. Discl. Bull., vol. 18, No. 12, May 1976,
`“Power Out Warning Interrupt Circuit”, Mong, pp.
`4147-4149.
`Chemical Instrumentation, vol. 7, No. 3, “A Minicom-
`puter Power Fail Detection System”, Rayside et al.,
`1976, pp. 211-218.
`
`Primary Examiner—Eddie P. Chan
`Attorney, Agent, or Firm—David G. Rasmussen; Kevin
`R. Peterson; Edmund M. Chung
`(57]
`ABSTRACT
`A data processing system, having a volatile main mem-
`ory prepares for power supply failure, at the first in-
`stance of power supply potential falling below a prede-
`termined limit, by readying its current task for restart,
`data-saving by storing the contents of volatile, proces-
`sor registers in the main memory, and completing any
`non-postponable tasks. If power deficiency lasts for
`longer than a predetermined period,
`the memory is
`maintained by a battery power source if and only if
`data-saving has been completed. Restoration of power
`during the predetermined period causes instant reversal
`and restart, but after the elapse of the predetermined
`period, causes reversal and restart if and only if a data
`save has been completed, otherwise causingreinitializa-
`tion.
`
`6 Claims, 8 Drawing Figures
`
`CARO
`READER/PUNCH |.4
`
`
`
`
`
`
`
`
`
`
`
`STANDBY
`36 SUPPLY
`
`
`Google Exhibit 1010
`Google Exhibit 1010
`Google v. Valtrus
`Googlev. Valtrus
`
`9
`vs
`OATA - SAVE
`CONTROL
`
`
`
`SYSTEM
`
`

`

`
`
`U.S. Patent
`
`Jul. 3, 1984
`
`Sheet 1 of 7
`
`4,458,307
`
`AC
`MAIN POWER
`
`
`CONTROL=SYSTEM
`
`SUPPLY
`
` DATA ~ SAVE
`
`
`
`
`
`STANOBY
`
` 36 SUPPLY
`
`
`

`

`U.S. Patent
`
`Jul. 3, 1984
`
`Sheet 2 of 7
`
`4,458,307
`
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`

`

`
`
`U.S. Patent
`
`Jul. 3, 1984
`
`Sheet 3 of 7
`
`4,458,307
`
`
`
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`

`

`U.S. Patent
`
`Jul. 3, 1984
`
`Sheet 4 of 7
`
`4,458,307
`
`AYOWAWAYOWSWSLIM=AYMOWAW
`
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`

`

`
`
`U.S. Patent
`
`jut3, 1984
`
`Sheet 5 of 7
`
`4,458,307
`
`TESTFLAG = 4
`
`FIG.5 TESTFLAG =0
`
`

`

`
`
`USS. Patent
`
`Jul. 3, 1984
`
`Sheet 6 of 7
`
`4,458,307
`
`INTERRUPT
`
`200
`
`STORE ADDRESS|
`
`
`IN
`REGISTER
`
`202
`
`
`
`204
`
`
`
`REQUEST
`NO
`FROM
`
`DATA SAV
`
`
`
`YES
`
`OTHER
`INTERRUPTS
`
`12
`
`READ
`STATUS
`
`214
`
`
`
`READ
`STATUS
`
`BRANCH
`
`
`RELOAD
`216
`
`
`OUTPUT
`REGISTERS
`
`O10}
`
`?
`
`CONTROL
`
`WRITE
`
`
`
`306
`
`208
`
`INITIALISE
`
`ERVICE
`OTHER
`INTERRUPTS
`
`226
`
`228
`
` XXMIOUX XX YES
`INTERRUPTS|222
`
`234
`
`ENABLE OTHER
`
`
`
`236
`
`ENABLE
`
`RETURN
`
`224
`
`

`

`
`
`U.S. Patent
`
`sul. 3, 1984
`
`Sheet 7 of 7
`
`4,458,307
`
`FIG. 6a
`
`8, + Bo
`
`
`
`
` DISPLAY B,
`
`ON
`
` TRANSFER
`LIGHTS ADD1
`
`to Bo
`
`Bo Bo +!
`
`
`
`

`

`
`
`1
`
`4,458,307
`
`DATA PROCESSOR SYSTEM INCLUDING
`DATA-SAVE CONTROLLER FOR PROTECTION
`AGAINST LOSS OF VOLATILE MEMORY
`INFORMATION DURING POWER FAILURE
`
`2
`the data processing system active long enoughto effect
`the necessary data transfer.
`Accordingly,it is a first object of the present inven-
`tion to provide a data processing system which provides
`itself with an early warning of an impending primary
`powerfailure, thereby giving itself sufficient time to
`execute an ordered shutdownroutine, leaving the sys-
`tem in a condition ready for instantaneous and complete
`recovery ofits interrupted operation on a restart after
`This is a continuation-in-part of application Ser. No.
`power restoration, and having completed any tasks
`which could not wait over until that time.
`944,481 filed Sept. 20, 1978.
`It is a second object of the present invention to pro-
`The present invention relates to data processor sys-
`tems, and particularly to such systems protected against
`vide a data processing system which transfers the con-
`tents of the processor’s registers, upon receipt of indica-
`loss of volatile memory information in the event of a
`tion of a power failure, to a volatile memory, which
`failure in the main power supply.
`memory is alone maintained, for the duration of the
`Various techniques have been devised in data pro-
`powerfailure, by a low power auxiliary supply, if and
`cessing systems for protection against loss of volatile
`only if the processor has successfully performed an
`memory information during a power failure. Some
`ordered shutdown.
`known techniques include an arrangement whereby,
`The inventionis herein described, by way of example
`upon the detection of a powerfailure, that is to say, the
`only, with reference to the accompanying drawings
`falling of the voltage of the primary power supply
`wherein;
`below a predetermined limit, the memory cycle already
`FIG.1, is a block diagram of one form of data pro-
`initiated is taken to completion,but all further memory
`cessing system constructed in accordance with the in-
`cycles are inhibited. In other known techniques, auxil-
`vention;
`iary power is supplied to the whole system for a time
`FIG. 2 is a block diagram of the data-save control
`after the loss of primary power, to allow for continued
`portion of the system of FIG. 1;
`operation of the system.Instill other systems, the con-
`FIG.3 is a logic diagram of the data-save controller
`tents of volatile memories are “dumped”into auxiliary,
`in the system of FIG.2;
`non-volatile stores.
`FIG. 4 is a block diagram of one known form of
`It is not generally possible to cease the operations of
`processor which may be used in the system of FIG.1;
`a data processing system at any unpredictable instant
`FIG. 5 is a state diagram illustrating the sequential
`with hope of recovery at a later time, namely, when
`operation of the machine state control unit defined by
`primary poweris restored, so as to continue operations
`the logic network in the data-save controller of FIG.3;
`as before. At the instant of “stopping”, the beginnings
`and
`and intermediate results of initiated operations are lost,
`FIGS. 6 and 6c illustrate one simplified program
`necessitating a certain amount of retracking before a
`which maybe used for performing an interrupt routine
`continuity of operations can be achieved. A processor,
`in a Data-save Operation.
`in order to achieve instantaneous and complete recov-
`FIG.7 illustrates a simplified data save program.
`ery from a powerfailure, or indeed, any other interrup-
`A system employing the present invention is illus-
`tion to its operation, must have had time to put the
`trated in generalized form in the block diagram of FIG.
`contents ofits various memories and registers in a state
`1. It includes a processor 2 supplied from an AC main
`ready for a restart before paying attention to the matter
`power supply 3. The processor 2 is of the programma-
`ble type, for example that described in detail in U.S.Pat.
`of the interruption.
`Anauxiliary power supply is a costly and bulky piece
`Nos. 3,886,523, 3,930,236, and 4,005,391, all assigned to
`of hardware, havinglittle economic relevance as part of
`the same assignee as the present invention. The proces-
`low cost, small systems. Further, the act of continuing
`sor is adapted to communicate with a host of peripheral
`to run a data processing system after a loss of primary
`units for data transfer, readout, and storage, such as a
`power can only be sustained for a short period because
`card reader punch 4 andaprinter 5, these being con-
`nected via a commonbidirectional I/O (Input-Output)
`of the large amounts of energy required. The question
`bus 6.
`of how to deal with the loss of primary poweris begged
`In addition, the processor 2 communicates with an
`by being postponed, and, in the event of a sustained
`external Read/Write memory 7 via a memory interface
`powerfailure, the auxiliary power supply offers no real
`8. The memory address for selecting one unique mem-
`solution.
`ory location for data retrieval or data deposition pur-
`The “dumping”of the contents of volatile memories
`poses, is supplied to the interface 8 via bus 10, and the
`into non-volatile peripheral stores offers a long term,
`Read/Write signal,
`indicating whether data is to be
`real solution to the powerfailure problem. In the past,
`written into or retrieved from the memory(7) is fed via
`when nearly all memory employed by processing sys-
`bus 12, the interface 8 in turn feeding to memory Jand
`tems was of the non-volatile core variety, volatile mem-
`enable signal via bus 13, a Read/Write address via bus
`ory, was restricted to a small number of processor buff-
`14, and the clocks via bus 16.
`ers and registers. The transfer of the contents of these
`The specific construction and operation of the pro-
`registers and buffers to peripheral store was thus rapid.
`cessor 2, and the manner of control of its various pe-
`Nowadays, the replacing of core store with volatile,
`ripheral units 3, 4, do not form part of the present inven-
`semiconductor devices has caused the amountof data to
`tion and therefore are not described herein in detail. A
`be “dumped”to increase at least ten thousand fold. The
`block diagram of a processor that may be used is illus-
`time required for data transfer has thus increased enor-
`trated in FIG. 4 and is described below to the extent
`mously, and,
`if this solution is presently adopted, a
`necessary for an understanding of the present invention.
`whole system auxiliary power source is required to keep
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`55
`
`65
`
`

`

`3
`If desired, further details of the construction and opera-
`tion of such a processor may be had by reference to the
`above-cited patents.
`The present invention concerns primarily the preser-
`vation of the volatile data in the registers of the proces-
`sor 2 in the event of a powerfailure in the AC main
`powersupply 3. For this purpose, a data-save control
`system, generally designated 20 in FIG.1, is coupled to
`the processor 2 via its bi-directional bus 6. The data-
`save control system is supplied with isolated AC vialine
`21 from the processor 2. In addition, the data-save con-
`trol system includes a DC supply 22 connected toit via
`line 24, and one or morebatteries 26 connected toit via
`line 28,
`the latter line including a cut-out switch 30.
`Uponthe detection of a failure in the AC/main power
`supply 3 by a mains-fail detector within the data-save
`control system 20 as will be described more particularly
`below,the data-save control system is effective to moni-
`tor the transfer, via Memory Write bus 32, of the infot-
`mation in the volatile data registers of the processor 2 to
`the external Read/write memory 7; and upon the detec-
`tion of the restoration of the supply mains, the data-save
`control system 20 is effective to monitor the retransfer,
`via Memory Read bus 34, of the information from the
`Read/Write memory 7 to the volatile data registers of
`the processor. During the foregoing operation of the
`data-save control system 20, it supplies standby power,
`via bus 36 to the Read/Write memory 7 for a sufficient
`time to complete the transfer and retransfer operations.
`Cut-out switch 30 in line-28 to the standbybatteries is
`actuated by a relay R1 in line 38, which relay is con-
`trolled by battery chargers included in the data-save
`control system 20. In addition, the data-save control
`system 20 controls, via line 39, a circuit breaker relay
`R2 having contacts 40 in the mains to the AC power
`supply 3, such as to inhibit the reconnection of proces-
`sor 2 to the main power supply until a predetermined
`time interval has elapsed following the restoration of
`the AC main power supply. All the foregoing opera-
`tions, and the manner the data-save controller perfoms
`them, are described more particularly below.
`FIG.2 is a block diagram of the data save control
`system 20 of FIG. 1. The system comprises an instruc-
`tion decoding unit 42, decoding the instructions re-
`ceived from the processor 2 via bus 6, a machinestate
`control unit 44 including the logic network defining the
`state sequence of the controller; a first timer TC1, a
`mains-fail detector 46 detecting a failure (e.g. either
`blackout or brownout) in the AC main power supply 3
`as sensed via the isolated AC inputline 21; a latch 48 for
`latching the Mains-Fail signal received via line 47 from
`detector 46; a second timer TC2; and an output gating
`circuit 50 gating the output to I/O bus6. Thefirst timer
`TC1is preferably a digital counter set to time-out 16 ms
`after actuation; it is used for timing in the state se-
`quence. The second timer TC2 is preferably an R-C
`Schmidt trigger set to time-out about 0.5 to 2 seconds
`after actuation;it is used for restart timing. All the fore-
`going components, which may be implemented on a
`single IC Integrated Circuit) chip, constitute a Data-
`Save Controller, which Controller is described more
`particularly below with respect to FIG.3.
`The data-save control system 20 illustrated in FIG. 2
`further comprises a battery charger 60 connected to the
`DC supply 22 via lead 24 and adapted to maintain the
`standbybattery 26 (FIG. 1) fully charged by controlling
`cut-out switch 30 via its relay R1 in line 38; a battery
`under-voltage protection unit 62 guarding against the
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`65
`
`4,458,307
`
`4
`batteries becoming too deeply discharged; an inverter
`unit 64 for supplying the standby AC voltagetoall the
`devices, including the external Read/Write memory 7
`(FIG. 1) via line 36, during 2 Mains-Fail condition; an
`under-voltage protection unit 66 protecting inverter 64
`against an under-voltage; an over-voltage protection
`unit 68 protecting the inverter against an over-voltage;
`and a drive circuit 70 which supplies driving current to
`circuit breaker R2 whose contacts 40 (FIG. 1) are in the
`AC supply mains.
`The foregoing units, which can be implemented on
`one or more additional IC chips, may be of known
`construction, and therefore further details of their con-
`struction and operation are not deemed necessary.
`FIG. 3 illustrates more particularly the data-save
`controller in the circuit of FIG. 2. The controller in
`FIG.3 includes two fixed memory devices 72, 74, pref-
`erably PROM’s (Programmable Read Only Memory
`Devices) which decode the inputs received from the
`processor 2 via 1/O bus 6. The data-save controller
`further includes four J-K flip-flops 76,78, 80,82, three of
`which (76,78,80) define the existing state of the data-
`save controller, the remaining one (82) registering the
`success or otherwise of the Data-Save Operation. In
`addition,
`the controller includes the two previously
`mentioned timers TC1 and TC2 used for timing in the
`state sequence; the mains fail latch 48 for latching the
`Mains-Fail signal received from the mains-fail detector
`46 (FIG.2) via line 47; the output gating circuit 50 for
`gating the output from the controller via 1/O bus 6 to
`the processor 2; and a test flip-flop 84 which is used
`during a testing operation to reset the mains-fail latch
`
`As indicated earlier, the data-save control system of
`the present invention may be used with different types
`of processors, FIG.4 illustrating, for purposes of exam-
`ple, one form of processor 2 with which the invention
`may be used, theillustrated processor being that more
`particularly described in the above cited patents.
`Briefly, the processor illustrated in FIG. 4 is one
`driven by micro-instructions made up of varying num-
`bers of syllables, depending upon the function and lit-
`eral values required. The processor employs twolevels
`of subinstruction sets by which macro (or subject) in-
`structions are implemented by strings of micro instruc-
`tions all of which are implemented by control instruc-
`tions. Each level of instruction sets may be stored in
`separate portions of memory, or even in separate memo-
`ries, with the control instructions being stored in a
`Read-Only memory internal
`to the processor. The
`micro instructions are thus formed of varying numbers
`of syllables, with the different syllables being stored in a
`micro instructions memory and fetched in sequence
`under the control of a Machine State Control unit TMS
`to form the particular micro instruction. One syllable of
`each micro instruction is selected to indicate the partic-
`ular combination of the function to be performed, the
`source and destination register to be employed,
`the
`particular busses which are to be used for data transfer,
`and the timing of micro instruction execution, i.e., the
`numberofcharacters,digits, or bits to be operated upon
`during the micro instruction execution. When the par-
`ticular micro instruction is formed of more than one
`syllable,
`the remaining syllables represent values or
`literals used as address parameters and also for logical
`operations.
`Asillustrated in FIG. 4, the processor 2 includes a
`function unit 120 to which data is supplied by A-bus 121
`
`

`

`4,458,307
`
`5
`and B-bus 122, and from which data is received by
`F-bus 123. All data moves from the various registers
`through function unit 120. These respective busses are 8
`bits wide, which is the basic width ofall syllables and
`data segments employed in the system. A bus 121 and
`B-bus 122 receive information segments from the re-
`spective registers, and also from memory, by way of
`U-buffer register 124, which is also employed to supply
`8 bit addresses to control memory 137.
`The machine instructions or S-instructions (which
`may be a higher level programme language, such as
`Cobol) are implemented by strings of micro instructions
`which are stored in an external memory. Preferably, a
`portion of external memory 7 (FIG. 1) is used for this
`purpose, the memory being divided into separate por-
`tions including a Read-Only portion for the permanent
`storage of micro instructions to provide “bootstrap”
`facilities, and Read/Write portions for storing the S
`instructions, some micro instructions, and data, during
`the normal operation of the processor. In addition, the
`Read/Write portion of external memory 7 is used dur-
`ing the Data-Save Operation for storing the volatile
`data in internal registers of the processor upon the de-
`tection ofa failure in the main power supply (3, FIG. 1),
`the information being retransferred back to the volatile
`data registers when the power supply has been restored,
`as will be described more particularly below.
`The memory address registers MARI and MARZ are
`identical 16-bit registers which operate in either the
`Transfer Mode or the Count Mode. In the Transfer
`Modeeachregister is arranged as two 8-bit byte regis-
`ters 125¢, 1256 and 126, 1264, both capable of being
`loaded from function unit 120 by way of F-bus 123.
`Whenin the Count Mode, each of the memory address
`registers is employed to address memory via a 16-bit
`output bus 144 connected to the memory address bus 10
`(FIG.1).
`The processor includes the following additional reg-
`isters; BO-Register 127 and B1-Register 128, which are
`single character general purpose registers; B2-Register
`1292 and B3-Register 1294, which are single character
`general purpose registers that may be concatenated to
`form a two-byte register; flag register 130, which is a
`single character register for storing general flags bytes;
`Y-Registers 131a~131d, and X-Registers 1330-1334,
`which may, respectively, be concatenated together to
`form two 4-byte registers or one 8-byte (16 digit) regis-
`ters (XY); working registers WRU, WR1, and addi-
`tional registers JUJL,KU,KL, and LU,LL.
`The processor 2 further includes micro address regis-
`ters (uMAR1-5) 135 capable of being loaded from, or
`unloaded to, function unit 120. They can be arranged to
`form a push-downorlast-in-first-out (LIFO), address
`stack for micro memory addressing and for storing
`program andinterrupt routine addresses. This informa-
`tion is outputted via 16-bit micro memory address bus
`145 and the memory address bus 10 (FIG. 1) to the
`memory interface unit 8.
`In addition, processor 2 further includes U-buffer
`register 124, whichis an 8-bit register used for address-
`ing control memory 137and for providing information
`about the next micro instruction to be executed. This
`information is used to generate overlap of the micro
`instruction fetch and execution phases. Uponthe access-
`ing of control memory 137, a control instruction is
`supplied to control buffer register 138, which holds the
`signals of a control instruction during the time required
`for its execution.
`
`6
`The input-output interface of the processor via 1/O
`bus 6 comprises I/O address bus 143 connected to 1/0
`address register 141, and 1/O request bus 142. I/O ad-
`dress register 141 is an 8-bit register used to address a
`plurality of bi-directional I/O channels or control units,
`and is loaded from, or unloaded to, function unit 120.
`Further details of the construction and operation of
`the processor may be had by reference to the above-
`cited patents. For purposes of the present invention,
`suffice it to point out thatall the above-mentioned regis-
`ters illustrated in FIG. 4 are internal to the processor;
`andthatall, except those of the control memory 137 and
`the micro address registers 135, are adapted to contain
`volatile data whichis to be saved in the event of a mains
`failure by the immediate and automatic transfer of the
`information from the volatile registers to the external
`Read/Write memory 7 supplied by the standby power
`supply via bus 36, the information being automatically
`transferred from the external memory7 to the processor
`registers upon the restoration of the mains, the transfer
`and retransfer of such information during a Data-Save
`Operation being monitored by the data-save controller
`in the control system 20 of FIGS. 1 and 2.
`The state diagram of FIG. 5 illustrates the manner in
`which the data-save controller of FIG. 3 monitors the
`transfer of the information from the volatile registers in
`the processor 2 to the external Read/Write memory 7
`upon the detection of a mains failure, and the retransfer
`of the information back to the registers upon the resto-
`ration of the supply mains. As pointed out above, the
`state sequence of the data-save controller is defined by
`the logic network of the controller illustrated in FIG. 3.
`State-0 is the initialized state of the controller,
`in
`which the data-save condition flip-flop 82 (FIG. 3) is
`reset, and the mains-fail latch 48 outputs a low level
`signal to fixed memory device 74. In State-0, the con-
`troller can be affected by:
`(1) the Mains-Fail signal from latch 48 going high,
`indicating that the mains-fail detector 46 (FIG. 2)
`has detected a failure (either black-out or brown-
`out) in the AC main power supply 3 (FIG. 1) or
`(2) Control Write signal being generated by the pro-
`cessor 2 with a specified data word.
`the
`In the event either of these conditions occurs,
`controller moves to State-1, generating a Request for
`access to the memory, and in addition, actuating the
`delay counter TC1 which counter times-out at 16 ms. If
`the Mains-Fail signal goes high,it is latched by latch 48
`and is thus synchronized to the system clocks in order
`to obviate timing errors.
`The provision for moving the controller from State-0
`to State-1 by a Control Write signal, is a test facility to
`enable simulation of a “mains failure” from the proces-
`sor.
`State-1 is a Request State, in which the controller
`requests the processor for access to the memory. If,
`while the controller is in State-1 the Mains-Fail signal
`returns low indicating that the supply mains has been
`restored, the controller returns to State-0. As indicated
`above, the controller will also return to State-0 if the
`processor sends a control Write signal for testing pur-
`poses. In this case, the Control Write signal sets the
`Mains Mail latch 48 via test flip-flop 84 (FIG. 3). The
`latter flip-flop is also actuatable by a Data In signal from
`the processor to reset the latch, this facility enabling the
`data-save operationto be inhibitedduringinitial loading
`of the memories by causing the controller to toggle
`between States 1 and 0.
`
`20
`
`25
`
`35
`
`40
`
`45
`
`55
`
`60
`
`65
`
`

`

`7
`If, the controller, while in State-1 receives a Read
`Status signal from the processor, the controller moves
`to State-2. This is a transitional state, and starts timer
`TC1. If no recognisable change or signal is recorded
`during a time period of 16 ms, timer TC1 will run-out,
`and the controller will move to State-3.
`If no Read Status signal is received from the proces-
`sor while the controlleris in State-1, timer TC1 will also
`run out after 16 ms, whereuponthe controller will move
`directly from State-1 to State-3.
`In State-3, the data-save controller generates another
`Request signal for access to the memory. If, when the
`responding Read Status signal from the processor is
`received by the Controller, the Mains-Fail signal has
`returned low (indicating that the main power supply has
`been restored), the controller will movetoits initialized
`State-0. If however, the Mains-Fail signal is still high,
`the Read Status signal will cause the controller to move
`to State-4. If no Read Status signal is received from the
`processor, the controller will lock-out in State-3.
`Wheneverthere is a Request from the data-save con-
`troller, the processor reads the status, and all other
`interrupts are ignored. By reading the status, the proces-
`sor can determineif the controller is in State-1 or State-
`3. A test flag is used for this purpose, thetest flag being
`a dedicated bit in a register (e.g. flag register 130, FIG.
`4) set or reset in order to differentiate between States 1
`and 3. Thus, the test flag is set high after State-1, low
`after State-3, and is low in the other States 4, 5, 6, 7 and
`0. If the data-save controller generates a Request signal
`before a data-save operation has been executed (this
`being recognized by the processor in the manner de-
`scribed below), the processor examinesthe state of the
`test flag. If the test flag is not set, the controller is in
`State-1; if the test flag is set, the controller is in State-3,
`and preparations must be made before shut down.
`While the controller is in State-4, the processor exe-
`cutes a stored data-save-operation program wherebyit
`effects a transfer of the information from its volatile
`registers to a non-volatile portion of external memory 7
`(FIG.1). In State-4, the processor can also complete the
`current instruction and usually several more until a
`convenient point to stop is reached at which pointit can
`then transfer the required registers to the memory for
`retention.
`The data-save-controller remains in State-4 until it
`receives a Control Write Signal from the processor
`indicating that a successful Data-Save -Operation has
`been completed, i.e. that the information in its volatile
`registers has been transferred intact
`into the non-
`volatile portion of external memory7. If no such Con-
`trol Write Signal is received by the controller, it will
`lock out in State-4. Upon receipt of Control Write sig-
`nal indicating that a successful Data-Save Operation has
`been completed, the controller moves to State-5.
`The data save controller remains in State-5 until the
`Mains-Fail signal from detector 46 and latch 48 returns
`low, indicating that power has been restored. All the
`while the Mains-Fail signal is high, the system remains
`in the Standby Mode, wherein the state flip-flops 76, 78,
`80, 82 (FIG. 3) of the data-save controller, and the
`external memory 7 together with its refresh circuitry
`and clocks, are powered by the standby batteries 26 via
`line 36 (FIG. 1.)
`When the power is restored, the Mains-Fail signal
`goes low, but the data save controller will wait in State-
`5 and not move to State-6 until timer TC2 (FIG. 2)
`times out. As indicated above,
`this timer is an RC
`
`10
`
`_ 5
`
`20
`
`25
`
`35
`
`40
`
`45
`
`50
`
`35
`
`60
`
`65
`
`4,458,307
`
`8
`Schmidt trigger circuit. It may be present to time-out
`after about 1 second and provided to ensure that start-
`up control is by the data-save controller. It prevents the
`possibility that the processor may examine a Request
`signal before the data-save controller has had a chance
`to generate one in State-6, i.c., before the information
`from the memoryhas been restored into the appropriate
`registers by the Data-Save Operation. The timeris trig-
`gered by the Mains-Fail signal going high upon the
`restoration of the power to ensure the discharge ofits
`timing capacitor, so that if power returns upon the con-
`troller entering State-5, the time-out will still have to
`run. It also ensures that on reaching State-5, the state
`flip-flops (76, 78, 80, 82, FIG. 3) can be locked in that
`state independently of clocks and input data, thereby
`reducing the numberof devices required to be powered
`during the Standby mode. As soon as the time(e.g. 1
`second)present in timer TC2 has run out from the time
`the controller has moved to State-5 (and assuming the
`Mains Fail signal has gone low, indicating power has
`been restored), the controller moves to State-6.
`Whenthe data-save-controller is used with the pro-
`cessor illustrated in FIG. 4, the first address register
`p»MAR1ofits micro memory address store 135is reset,
`and the processor executes a programme stored in a
`non-volatile memory portion of the external memory7,
`whenever the power is switched on, or a Request is
`generated by a controller indicating a requirement for
`updated information or similar action by the processor.
`The programme executed by the processor first
`in-
`structs the processor to store the address of the location,
`held in the memory address register (uMAR1) before
`interruption, in a subsidiary register (uMAR3), so that
`the processor can return to that address after servicing
`the Interrupt on receipt of an Enable Return signal. If
`the system has only been switched on, there being no
`volatile data to be saved, no Enable Return signal will
`be exectuted, and instead, the address of thefirst in-
`struction required in the volatile store will be entered
`into the first address register (uMAR1) of the micro
`address store 135.
`After temporarily storing the original memory ad-
`dress, the programmestored in the non-volatile mem-
`ory determines if there is a Request from the data-save
`controller. If there is no request, indicating that no data
`has been saved, the processor generates a Read Status
`signal moving the data-save controller from State-6 to
`State-7. A Control Write signal is then sent from the
`processor, which moves the controller from State-7 to
`the initialized State-0.
`If the mains should fail while the controller is in
`State-7, the controller will immediately return to State-
`5.
`
`Asindicated earlier, the processor can identify either
`of the Request States 1 or 3 by examining the Test Flag
`(e.g. in flag register 130, FIG. 4), the Test Flag being
`reset in State-1 and set in State-3.
`Both of the above States 1 or 3 can occur only when
`the Mains-Fail signal is high, indicating a failure in the
`supply mains. If Mains-Fail signal is low , however,
`indicating that the power has been restored, and a Re-
`quest is generated by the controller, this means that the
`controlleris in State-6. In this state, the data-save condi-
`tion flip-flop 82 (FIG.3)is set, indicating that the vola-
`tile register information of the processoris stored in the
`non-volatile portion of its external memory 7. The pro-
`cessor thereupon retransfers retransfers the volat