as) United States
`a2) Patent Application Publication (10) Pub. No.: US 2002/0087901 A1
`(43) Pub. Date: Jul. 4, 2002
`
`Cooperetal.
`
`US 20020087901A1
`
`(54) DEMAND-BASED METHOD AND SYSTEM
`OF CPU POWER MANAGEMENT
`
`(52) US. Ch.
`
`vosssssscsssssssssssssssasuntssstsnsasenssneensee 713/320
`
`(76)
`
`Inventors: Barnes Cooper, Beaverton, OR (US);
`Jay Arjangrad, Portland, OR (US)
`
`(57)
`
`ABSTRACT
`
`Correspondence Address:
`Justin M. Dillon
`BLAKELY SOKOLOFF TAYLOR & ZAFMAN
`LLP
`7th Floor
`12400 Wilshire Boulevard
`
`Los Angeles, CA 90025 (US)
`
`(21) Appl. No.:
`
`09/751,759
`
`(22)
`
`Filed:
`
`Dec. 30, 2000
`
`Publication Classification
`
`(51) Unt. Ch? ee eccseeceseeee GO06F 1/26; GO6F 1/32
`
`A demand-based method and system of central processing
`unit power management. The utilization of a central pro-
`cessing unit (CPU) during a sampling time interval
`is
`determined by measuring a time quantum within the sam-
`pling time interval during which a central processing unit
`clock signal is active within a processor core of the CPU.
`The total number of cycles of the central processing unit
`clock signal that are applied to the processor core and the
`period of the central processing unit clock signal are used to
`determine the time quantum. The utilization may then be
`expressed in termsofa ratio of the time quantumto the total
`time interval and used to select a processor performance
`mode. The CPU is then operated in the selected processor
`performance mode.
`
`
`
`102
`
` 12 i]
`
`
`
`
`
`
`
`110 ™\
`
`
`
`
`
`
`
`
`— 108
`
`
`
`
`106
`
`Google Exhibit 1017
`Google Exhibit 1017
`Google v. Valtrus
`Google v. Valtrus
`
`

`

`Patent Application Publication
`
`Jul. 4, 2002 Sheet 1 of 7
`
`US 2002/0087901 Al
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`Patent Application Publication
`
`Jul. 4, 2002 Sheet 2 of 7
`
`US 2002/0087901 Al
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`Patent Application Publication
`
`Jul. 4, 2002 Sheet 3 of 7
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`US 2002/0087901 Al
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`Patent Application Publication
`
`Jul. 4, 2002
`
`Sheet 4 of 7
`
`US 2002/0087901 Al
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`Figure 4
`
`| 400
`
`
`( Start
`
`ye
`
`
`
`Manangment Lo—
`
`Power
`
`Application
`Requests CPU
`Utilization Status
`
`402
`
`
`
`!
`
`CPUUtilization is
`Determined
`
`wee“
`
`
`
`
`
`
`
`Yes >
`
`
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`wel
`
`Switch CPU to
`Maximum
`Performance
`Mode
`
`
`Utilization Greater
`
`
`Than or Equal
`to
`
`
`
`No
`
`-
`
`
`Is the CP
`
`Utilization Less
`
`Than or Equal
`to
`
`75%?
`
`Switch CPU to
`Battery Optimized
`Mode
`
`
`
`
`No
`
`
`
`
`

`

`Patent Application Publication
`
`Jul. 4, 2002 Sheet 5 of 7
`
`US 2002/0087901 A1
`
`500
`
`
`
`Start
`
`Figure 9
`
`
`[ 502
`Power
`User-Specified
`Management A 504
`Maximum Battery
`Application
`Power
`»| Generates a Set
`Management
`State SMI for
`Profile Received
`Maximum Battery
`Mode
`
`
`-
`
`4 508
`
`a
`
`baienent
`Abccat‘on
`Requests CPU
`Utilization Status
`
`7
`
`_
`
`506
`
`
`
`SMI Notes
`Maximum Battery
`Modeis Entered
`and Switches CPU
`toBatey
`Optimized Made
`
`
`
`
`
`
`
`
`
`
`
`
`
`CPU Utilization is
`Determined
`
`Is Maximum
`
`Battery Mode
`
`Enabled?
`
`
`
`516
`
`
`
`EnableThrottling
`of CPU Clock
`Signal
`
`be
`:
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`Yes -
`
`514
`
`Yes
`Xx
`an oP
`Greater Shen
`le
`NOR
`
`No
`
`
`
`

`

`Patent Application Publication
`
`Jul. 4, 2002 Sheet 6 of 7
`
`US 2002/0087901 A1
`
`Figure 6
`
`
`
`
`602
`
`
`
`L
`
`—————_
`Power
`Manangment
`Application
`Requests CPU
`
`Utilization Status
`
`CPUUtilization
`Determined
`
`
`
` A. 608
`L 610
`
`
`
`
`Than or Equai to
`
`Yes
`
`Clock Signal
`.
`
`t—-——>|
`
`
`Performance
`
`
`
`
`
`rs
`
`F
`
`
`612
`
`A
`
`ye
`
`614
`
`Is the CPU
`Utilization Greater
`Than 20%?
`
`Yes
`
`Switch CPU to
`Battery Optimized +»
`Mode
`
`Enable CPU Clock
`
`Signal Throttling
`
`
`
`
`Ys606
`/
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`
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`
`CtlizationGreats
`Disable CPt
`ein
`aeee
`Throttling
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`
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`
`
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`Clock Signal
`
`Throttling
`
`
`
`
`
`A 618
`
`
`
`
`620
`
`
`
`
`Switch CPU to
`|———-») Battery Optimized
`Mode
`
`

`

`Patent Application Publication
`
`Jul. 4, 2002 Sheet 7 of 7
`
`US 2002/0087901 A1
`
` cT00
`
`Figure /
`
`(
`
`Start
`
`702
`
` |
`
`Read System-Independent Timer ~~
`
`a,
`
`Using a System-Independent a
`
`Define a Sampling TimerInterval
`
`704
`
`Timer Clock Period, a Current
`and a Prior System Independent
`Timer Value
`
`
`
`
`|
`
`
`
`
`
`
`2 706
`
`708
`
`740
`
`
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`
`712
`
`Read Time Stamp Counter Value |“
`
`!
`
`
`¥v
`
`Determine the Total number of
`Clock Cycles of the CPU Clock
`Applied to the CPU's Processor
`Core During the Sampling Time
`Interval Using Current and Prior
`Time Stamp Counter Values
`
`
`
`
`!
`
`Calculate Active Time Quantum
`of CPU Clock Signal within the
`Sampling Time interval using the
`Total Number of Applied CPU
`Clock Cycles and the CPU Clock
`Period
`
`——
`
`
`
`bn
`
`Divide Calculated Actiive Time
`Quantum of CPU Clock by
`Sampling Time Interval to Obtain
`CPU Utilization
`
`714
`
`End
`
`

`

`US 2002/0087901 Al
`
`Jul. 4, 2002
`
`DEMAND-BASED METHOD AND SYSTEM OF
`CPU POWER MANAGEMENT
`
`FIELD OF THE INVENTION
`
`[0001] The field of the invention relates generally to
`central processing units (CPUs). More particularly the ficld
`invention relates to CPU power management. Still more
`particularly, the field of the invention relates to a demand-
`based method and system of CPU power management.
`
`BACKGROUND OF THE INVENTION
`
`[0002] As battery-dependent portable computing devices
`(notebook computers, personal digital assistants, etc.) have
`become moreprevalent, the conservation of battery poweror
`“power management” has become more and more impor-
`tant. In many power management systems, some or all
`system components may be deactivated or “powered down”
`to conserve power. This method however, requires that the
`devices powered down be inactive or unused for a suffi-
`ciently long period of time to justify the latency associated
`with their re-activation. Therefore, a number of methods
`have been implemented to decrease device power consump-
`tion within the active or “powered on” state. Since,
`the
`powerdissipated by a device is dependent both onits applied
`voltage and on the frequency with which device transitions
`or “switching” occurs, conventional power management
`techniques typically focus on one or both of these factors.
`
`[0003] Modem power management systems implement a
`variety of voltage and frequency reduction or “scaling”
`techniques. Although substantial power savings can bereal-
`ized by reducing a device’s voltage, special hardware is
`often required to correctly operate such devices using low
`and variable voltages. Such voltage reduction techniques
`also currently limit the maximum frequency at which a
`device may be operated. Similar power savings may be
`realized by scaling a device’s operating frequency or
`“clock”.
`In conventional power management systems, a
`device’s operating frequency may be altered in a variety of
`ways. In one approach, the applied clock signal is periodi-
`cally stopped and restarted such that the average or effective
`operating frequency is lowered (throttling).
`In another
`approach, a lower frequency clock signal, gencrated inde-
`pendently or derived from an existing clock, is applied to a
`device. Although these approaches may be usedalone or in
`combination to reduce a device’s or system’s power con-
`sumption,
`this frequency scaling technique reduces the
`operating frequency of the device, and consequently the
`numberof operations or tasks it can perform.
`
`In the past, several approaches have been taken to
`[0004]
`control the activation of the above-described power man-
`agement techniques such as the user selection of a pre-
`defined power mode,
`the occurrence of environmental
`events such as the application or removal of an A/C (alter-
`nating current) power source, or the detection of a system or
`device temperature. More recently, power management sys-
`tems have looked to device utilization or “idleness” to
`
`trigger the application or removal of such techniques in an
`effort to conserve power in a more user-transparent manner.
`Whena utilization-based power managed deviceis idle for
`a pre-determinedperiod of time, power reduction techniques
`such as voltage and frequency scaling are applied to
`decrease the amount of power consumed. The greatest
`
`difficulty traditionally associated with such demand-based
`systems has been in determining a device’s current utiliza-
`tion, particularly for processing devices such as the central
`processing unit (CPU) of a data processing system.
`
`In a conventional operating system (OS), CPU
`[0005]
`utilization is determined by accumulating CPU idle time
`across a sampling interval to determine the percentage of
`time the processor is inactive. To accomplish this, a list of
`tasks or threads is maintained by the OS which are ready-
`to-run, i.e., not waiting for some event to resume execution.
`When this ready-to-run list is empty, no tasks are being
`executed and the processor is idle. Accordingly, a CPU-
`independent timer is read and the processor is placed in a
`low power state. When a new task is added to the ready-
`to-runlist, the processor is placed in an active state and the
`timer is read again. The difference between the first and
`second timer reads (multiplied by the timer’s period) then
`represents the CPU’s idle time. The accumulation of this
`time across a sampling intervalis then used to determine the
`CPUutilization (what percentage of the CPU’s timeis spent
`idle). Unfortunately, neither this measure of CPU utilization
`nor the state of the ready-to-run task list is available outside
`of the OS through a supported application programming
`interface (API). Consequently, this OS-generated CPU uti-
`lization metric cannot be utilized in a “demand”orutiliza-
`tion-based power management system.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`invention is illustrated by way of
`[0006] The present
`example and not limitation in the figures of the accompa-
`nying drawings, in which
`
`[0007] FIG. 1a illustrates a conventional data processing
`system useable with the present invention;
`
`[0008] FIG. 15 illustrates a prior art architecture of the
`data processing system depicted in FIG. 1a;
`
`[0009] FIG. 2 illustrates a portion of the architecture
`depicted in FIG. 1b in greater detail;
`
`FIG.3 illustrates an architectural system diagram
`[0010]
`depicting the operation of a data processing system accord-
`ing to the present invention;
`
`FIG.4 illustrates a high-level logic flowchart of a
`([0011]
`first embodiment of the method of the present invention;
`
`FIG.5 illustrates a high-level logic flowchart of a
`{[0012]
`second embodimentof the method of the present invention;
`
`FIG.6 illustrates a high-level logic flowchart of a
`[0013]
`third embodiment of the method of the present invention;
`
`FIG.7 illustrates a high-level logic flowchart of a
`[0014]
`method of determining the utilization of a central processing
`unit according to one embodimentof the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`{0015] Ademand-based method and system of CPU power
`managementis disclosed. In the following detailed descrip-
`tion, numerous specific details are set forth in order to
`provide a thorough understanding of the present invention.
`However, it will be apparent to one of ordinary skill in the
`art that these specific details need not be used to practice the
`present invention. In other circumstances, well-knownstruc-
`
`

`

`US 2002/0087901 Al
`
`Jul. 4, 2002
`
`tures, materials, circuits, processes and interfaces have not
`been shownordescribed in detail in order not to unneces-
`
`sarily obscure the present invention.
`
`[0016] Referring now to FIG. 1a, a conventional data
`processing system 100 useable with the present invention is
`illustrated. Data processing or computer system 100 is
`comprised of a system unit 102, output devices such as
`display 104 and printer 110, and input devices such as
`keyboard 108, and mouse 106. Data processing system 100
`receives data for processing by the manipulation of input
`devices 108 and 106 or directly from fixed or removable
`media storage devices such as disk 112 and network con-
`nection interfaces (not shown). Data processing system 100
`then processes data and presents resulting output data via
`output devices such as display 104, printer 110, fixed or
`removable media storage devices like disk 112 or network
`connection interfaces.
`
`there is depicted a
`[0017] Referring now to FIG. 16,
`high-level block diagram of the components of a data
`processing system 100 such asthat illustrated by FIG. 1a. In
`a conventional computer system, system unit 102 includes a
`processing device such as central processing unit (CPU) 120
`connected to a level two (L2) cache 122 over a processor
`system bus (PSB) 114. Processor system bus 114 is in turn
`coupled to an expansion bus such as local bus 116 and a
`memory 126 via a north bridge circuit 124. Local bus 116
`may include a peripheral component interconnect (PCD),
`Video Electronics Standards Association (VESA)busorthe
`like, tightly coupled to the processor 120 and the processor
`system bus 114 to permit high-speed access to select devices
`such as display device 128.
`
`[0018] Memory 126 may include read-only (ROM) and/or
`random access (RAM) memory devices such as a synchro-
`nous dynamic random access memory (SDRAM) module
`capable of storing data as well as instructions to be executed
`by CPU 120. Access to data and instructions stored within
`memory 126 is provided via a memory controller (not
`shown) within north bridge circuit 124. L2 cache 122 is
`similarly used, typically in a hierarchical manner, to store
`data and instructions for direct access by CPU 120. Display
`device 128 may include a cathode ray tube (CRT) display
`such as display 104,
`liquid crystal display (LCD), or a
`similar device for displaying various kinds of data to a
`computer user. For example, image, graphical, or textual
`information may be presented to the user on display device
`128. System unit 102 of data processing system 100 also
`features an expansion or “compatibility” bus 118 such as the
`Industry Standard Architecture (ISA) bus, and a south bridge
`circuit 134 coupling it to local bus 116 to facilitate the
`attachmentof other, relatively slower devices to the system
`100. South bridge circuit 134 includes a universal serial bus
`(USB) port 138 as well as other direct connections for
`devices such as a network interface card 130, a data storage
`device, such as a magnetic hard disk drive 132, and an audio
`device 140 such as a speaker or sound card.
`
`[0019] Other devices not directly coupled to south bridge
`134 may be connected to the system 100 via the expansion
`bus 118 as illustrated. A floppy disk drive (FDD) 144
`providing additional data storage capacity on removable
`media storage devices such as disk 112, and input devices
`such as a keyboard 108 and a cursor control device 136 are
`each coupled to expansion bus 118 in this manner to
`
`communicate data, instructions, and/or commandselections
`to central processing unit 120. Cursor control device 136
`may comprise a conventional mouse such as mouse 106 of
`FIG. 1a, a trackball, or any other device capable of con-
`veying desired cursor manipulation. Similarly, expansion
`bus 118 includes an input/output (I/O) controller having
`standard serial and parallel port functionality for connecting
`other I/O devices such as printer 110 to the system.
`
`[0020] The system of the present invention includessoft-
`ware, information processing hardware, and various pro-
`cessing steps, which will be described below. The features
`and process steps of the present invention may be embodied
`in machine or computer executable instructions embodied
`within media such as disk 112. The instructions can be used
`to cause a general purpose or special purpose processor such
`as CPU 120, which is programmed with the instructions to
`perform the described methods of the present invention.
`Alternatively, the features or steps of the present invention
`may be performed by specific hardware components that
`contain hard-wired logic for performing the steps, or by any
`combination of programmed computer components and cus-
`tom hardware components.
`
`([0021] Referring now to FIG. 2, a portion of the archi-
`tecture depicted in FIG. 15 is illustrated in greater detail.
`Processor 120 is shown in communication with memory 126
`over the processor system bus 114 utilizing a memory
`controller 226 of north bridge circuit 124. Acommon system
`clock, (BCIk) 216 is generated by a clock generator 208 and
`applied to a clock control phase lock loop (PLL) 218 of CPU
`120 and to memory controller 226. A core voltage 206 is
`similarly applied to CPU 120in the illustrated embodiment,
`providing necessary operating power. While the BCIk signal
`216 is applied, accesses to and from memory 126 occur at
`its frequency of approximately 100 megahertz (MHz). The
`central processing unit 120 however, is capable of perform-
`ing tasks at much greater speeds than this and accordingly,
`a bus ratio or multiplier 212 is selected using a clock control
`signal, GHI#202 and a higher frequency central processing
`unit clock signal is generated utilizing PLL 218. So for
`example,
`if the system or front side clock 216 has a
`frequency of 100 MHz,and a ratio 212 of 5 to 1 is selected
`using the GHI# signal 202, then the generated CPU clock
`will have a frequency of approximately 500 MHz. Alterna-
`tively, a higher multiplier or ratio 212 of say 7 to 1 could be
`selected, yielding a CPU clock frequency of approximately
`700 MHz.
`
`[0022] The generated central processing unit clock signal
`is then applied to clock throttling logic 220 before being
`passed to processor core 200. Throttling is a technique by
`which the CPU clock is deasserted or “gated off” from the
`processor core to prevent functional units within the core
`from operating. Throttling logic 220 therefore acts as a
`switch, actuated by a stop clock (Stp,, Clk) control signal
`204, between the PLL 218 and the processor core 200. A
`time stamp counter 224is also included within the CPU 120
`and incremented for each cycle (sometimes called ticks or
`pulses) of the CPU clock which is “gated through” or
`applied to the processor core as shown. Because time stamp
`counter 224 tracks the number of clock ticks or cycles
`applicd to the functional units of the processor core 200 such
`as instruction decoders,floating point and integer execution
`units, etc. it provides an extremely accurate representation of
`the actual work performed by CPU 120. One additional
`
`

`

`US 2002/0087901 Al
`
`Jul. 4, 2002
`
`illustrated in FIG. 2 is
`chipset architecture component
`independent timer 210. System independent timer 210 runs
`independently of CPU 120 andits associated system clock
`216, unaffected by Stp_Clk signal 204 throttling or BClk
`signal 216 frequency modifications. Using the number of
`ticks of independent timer 210 elapsed between readsandits
`fixed frequency, an accurate measure of the passage of time
`may be obtained. In one embodiment, a Windows™ high
`performance counter, exported via the Win32 Application
`Programming Interface (API) as the QueryPerformance-
`Counter(Q) function can be used as independent timer 210. In
`an alternative, Advanced Configuration and PowerInterface
`(ACPI) compliant embodiment, a power managementtimer
`may be utilized. Although in the illustrated embodiment
`independent timer 210 is depicted as being integrated with
`clock generator circuit 208, in alternative embodiments the
`timer 210 may be generated in a separate device or inte-
`grated circuit.
`
`[0023] Referring now to FIG.3, an architectural system
`diagram depicting the operation of a data processing system
`according to the present
`invention is illustrated.
`In the
`illustrated embodiment, a plurality of application programs
`302 such as power management application 304 interact
`with various platform hardware devices 308 including a
`CPU 120 via an operating system 300 such as the Win-
`dows™ operating system from Microsoft Corporation, one
`or more device drivers 306, and basic input/output system
`(BIOS) code 310. The illustrated system is interrupt-driven
`both with respect to the multitasking of the various appli-
`cations 302 and communication between applications 302
`and platform hardware 308.
`
`in one embodiment of the present
`[0024] Accordingly,
`invention, an application 302 request
`for
`a hardware
`resource from within platform hardware 308 can cause an
`interrupt, such as a System Control Interrupt (SCI) or a
`System Management Interrupt (SMI) to be generated and an
`interrupt handler routine to be responsively executed. Inter-
`action between operating system 300 and platform hardware
`308 is then facilitated by a device driver 306 and BIOS 310.
`In the illustrated embodiment, BIOS 310 contains informa-
`tion such as physical device addresses of the various devices
`308 attached to the data processing system 100 and is useful
`with respect to the actual transmission of data. By contrast,
`device driver 306 is typically specific to a particular hard-
`ware device and is usually concerned with the translation of
`data between various device formats.
`
`[0025] Referring now to FIG.4, a high-level logic flow-
`chart of a first embodiment of the method of the present
`invention is illustrated. In FIG. 4 there is depicted a tech-
`nique by which a demand-based transition between two
`processor performancestates is executed. At block 400, the
`illustrated process is begun and thereafter a CPU utilization
`status request is received from a power management appli-
`cation (block 402). The described utilization request may be
`periodic or may occur in response to relevant power man-
`agement events such as thermal or processor workload
`events, the connection of an alternating current power sup-
`ply or the like. Once the CPU utilization has been estab-
`lished (block 404), a determination is then made whetherthe
`calculated utilization exceeds a utilization threshold (block
`406). In the illustrated embodiment, a relatively high utili-
`zation threshold of 95% is selected to identify the execution
`of demand-intensive applications such as DVD movie play-
`
`ers, personal computer games, and performance benchmark
`tests.
`It should be readily appreciated however that
`the
`various utilization thresholds described herein have been
`
`selected for illustrative purposes only and that a wide range
`of threshold values could be substituted therefore without
`
`departing from the spirit and scope of the present invention.
`If the utilization threshold is exceeded, the CPU is transi-
`tioned to a maximum performance processor performance
`mode (block 408) and operated at a higher performance
`level
`to ensure that
`the execution performance of such
`demand-intensive application programs is not degraded.
`[0026]
`If the utilization of the CPU is not above or equal
`to the 95% utilization threshold,
`it
`is then determined
`whether the CPU’s utilization falls at or below a second
`utilization threshold of, in the illustrated embodiment, 75%
`(block 410). The processor performance level may then be
`matchedto its current utilization level by switching the CPU
`to a battery optimized processor performance mode (block
`412) to conserve power when the utilization level falls
`below this figure and a decrease in performance will be less
`noticeable to the end user. Otherwise the process is termi-
`nated (block 414) with the processor performance mode of
`the central processing unit remaining unchanged. Power
`may be conserved and the maximum performance mode
`distinguished from the battery optimized modebythe fre-
`quency at which the processor is operated. While numerous
`other power and performance management techniques are
`knownand within the scope of the present invention, in one
`embodimentutilization of the maximum performance pro-
`cessor performance mode entails the operation of the central
`processing unit at an operating frequency of 600 MHz while
`the battery optimized mode entails the application of a 500
`MHz central processing unit clock signal. Following any
`transition to either maximum performance or battery opti-
`mized mode, the process is terminated (block 414). In an
`alternative embodiment, factors other than an instantaneous
`CPU utilization and a utilization threshold may be used to
`select an appropriate processor performance mode such as
`the duration of time that the examined CPU remainsat a
`
`particular utilization level or within a particular range of
`utilization levels.
`
`[0027] Referring now to FIG.5, a high-level logic flow-
`chart of a second embodimentof the method of the present
`invention is illustrated. After the process is begun (block
`500) a uscr-specificd power managementprofile is reccived
`(block 502) in which power conservation and system per-
`formance are prioritized generally or a specific, preferred
`processor performance mode may be designated. In the
`illustrated embodiment, a maximum battery or ultra battery
`optimized profile is received conveying that power conser-
`vation is to be favored over execution speed. Then an
`executing power management software or firmware appli-
`cation generates a system management
`interrupt
`(SMI)
`(block 504) in response to the receipt of the user power
`management profile which in turn transitions the CPU to
`battery optimized mode if necessary from whatever prior
`state the processor was operating in. Subsequently,
`the
`power management application issues a request for the
`current CPU utilization status (block 508) which is deter-
`mined either by the generated SMIor directly by the power
`management application itsclf (block 510) by a method
`which will be described in greater detail with reference to
`FIG. 7 herein. In alternative embodiment,
`the described
`system managementinterrupt is used only to transition the
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`system from one performance or power mode to another
`with both CPU utilization detection and other related tasks
`
`being performed directly by the power management appli-
`cation.
`
`consumed. Following any transition to (or retention of) any
`of the above-described power management performance
`modes (maximum performance, battery optimized mode,
`and maximum battery) the process is terminated (block
`622).
`
`[0028] The user-specified power managementprofile is
`([0031] Referring now to FIG.7, a high-level logic flow-
`then checked to ensure that maximum battery modeisstill
`currently enabled (block 512). If so,
`the resolved CPU
`chart of a method of determining the utilization of a central
`utilization is examined to determine whether it exceeds a
`processing unit according to one embodimentof the present
`utilization threshold of 20% (block 514) in this embodiment.
`inventionis illustrated. FIG. 7 depicts a technique by which
`If not, the process is terminated (block 518). If the current
`a the utilization of a CPU may be determined independently
`utilization of the CPU exceeds the tuneable threshold, the
`of a data processing system’s operating system. In one
`embodiment,
`this method is utilized to determine CPU
`CPUis transitioned from battery optimized modetoavirtual
`utilization within the various method embodiments of the
`maximum battery performance mode by engagingthrottling
`of the central processing unit clock signal at a particular
`frequency (block 516). Otherwise, the process ends (block
`§18) and the battery optimized performance modeis utilized
`until another transition-precipitating event occurs. Using the
`illustrated process allows small, bursty tasks or code seg-
`ments which can be completed within the sampling time
`interval of the CPU utilization determination to be executed
`
`the full, battery optimized performance level without
`at
`enabling CPU clock signal throttling. Such tasks can be
`completed faster at
`this non-throttled rate, allowing the
`system to transition after their completion to an even lower
`power state than can be achieved with clock throttling,
`conserving more poweroverall.
`
`[0029] Referring now to FIG.6, a high-level logic flow-
`chart of a third embodiment of the method of the present
`invention is illustrated. The beginning of the process is
`depicted at block 600 and thereafter a CPU utilization status
`request is received from a power management application
`(block 602). Once the CPU utilization has been established
`(block 604), a determination is made whether the calculated
`utilization exceedsa utilization threshold (block 606). In the
`illustrated embodiment, a relatively high utilization thresh-
`old of 95% is selected for this first utilization threshold as
`illustrated.
`If the utilization threshold is exceeded, any
`previously applied CPU clock signal throttling is disabled
`(block 608) and the CPU is transitioned to a maximum
`performance processor performance mode (block 610) and
`operated at a higher performance level to ensure that the
`execution performance of demand-intensive application pro-
`grams is not degraded.
`
`If the utilization of the CPU is not above or cqual
`[0030]
`to the 95% utilization threshold,
`it
`is then determined
`whether the CPU’s utilization falls at or below a second
`utilization threshold of, in the illustrated embodiment, 20%
`(block 612). If the current CPU utilization level
`is not
`greater than the 20% utilization threshold,
`the CPU is
`operated in battery optimized mode (block 620) and clock
`throttling is disabled (block 618) such that power saving
`states such as the C2 and C3 states defined by the well
`known Advanced Configuration and PowerInterface Speci-
`fication, Revision 2.0, Jul. 27, 2000 (ACPI) can be entered
`more quickly following completion of the CPU workload.
`Lastly, for CPU utilizations falling in between the two
`utilization thresholds, the CPUis transitioned to and oper-
`ated in maximum battery mode by entering battery opti-
`mized mode (block 614) and enabling clock throttling for
`the applicd CPU clock (block 616). Conscqucntly,
`the
`performance of CPU workloads having a consistent, inter-
`mediate demand intensity is reduced and the completion
`time is extendedin order to reduce the total amount of power
`
`present invention such as at blocks 404, 510, and 604 of
`FIGS. 4,5, and 6, respectively. ‘Whe process illustrated by
`FIG.7 begins at block 700. Thereafter, a system-indepen-
`dent timer such as an ACPI chipset-compliant power man-
`agement timer or Windows™performance counteris read.
`(block 702). Next, a sampling time interval is defined using
`the independent timer’s clock period, as well as currently
`and previously read system-independent timer values (block
`704). A value is then read from a time stamp counter (block
`706) which is incremented for each cycle or “clock” of a
`CPUclock signal which is applied to the processor core 200
`of central processing unit 120. Using a previously read time
`stamp counter value and the currently read value, the total
`number of CPU clock signal ticks or cycles applied to the
`CPU’s processor core 200 during the sampling time interval
`maybe obtained (block 708). Thereafter, the total amount or
`“quantum” of time within the sampling time interval during
`which the CPU clock signal was active within the CPU’s
`processor core 200 can be derived using the accumulated
`number of CPU clock cycles and the CPU clock signal’s
`period (block 710). CPU utilization may then be expressed
`as a ratio of this active CPU clock signal
`time to the
`sampling time interval (block 712). Thereafter, the process
`is terminated (block 714).
`
`[0032] Although the present invention is described herein
`with reference to a specific preferred embodiment, many
`modifications and variations therein will readily occur to
`those with ordinary skill in the art. Accordingly, all such
`variations
`and modifications
`are
`included within the
`intended scope of the present invention as defined by the
`following claims.
`Whatis claimedis:
`
`1. A method comprising:
`
`measuring a time quantum within a sampling time interval
`during which a central processing unit clock signal is
`active within a processor core of a central processing,
`unit;
`
`determining a utilization of said central processing unit
`during said sampling time interval utilizing said time
`quantum;
`
`selecting a processor performance mode from a plurality
`of processor performance modes based upon said uti-
`lization of said central processing unit; and
`
`operating said central processing unit in said selected
`processor performance mode in response to said selec-
`tion.
`
`2. The method as set forth in claim 1, wherein selecting
`a processor performance mode from a plurality of processor
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`US 2002/0087901 Al
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`Jul. 4, 2002
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`determine a utilization of said central processing unit
`during said sampling time interval utilizing said time
`quantum;
`
`select a processor performance mode from a plurality of
`processor performance modes based uponsaid utiliza-
`tion of said central processing unit; and
`
`performance modes comprises selecting a proces