United States Patent i
`Huang
`
`[54] DUAL SOCKET UPGRADEABLE
`COMPUTER MOTHERBOARD WITH
`AUTOMATIC DETECTION AND
`ENABLEMENT OF INSERTED UPGRADE
`CPU CHIP
`
`[75]
`
`Inventor: Hung-Ta Huang, Taipei, Taiwan
`
`[73] Assignee: Acer Incorporated, Taipei, Taiwan
`
`CY0A
`
`US005455927A
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,455,927
`Oct. 3, 1995
`
`FOREIGN PATENT DOCUMENTS
`
`0333318
`0381448
`0411806
`61-84764
`61-84765
`61-84767
`
`9/1989 European Pat. Off. .
`8/1990 European Pat. Off. .
`2/1991
`European Pat. Off. .
`4/1986 | Japan .
`4/1986
`Japan.
`4/1986
`Japan.
`
`OTHER PUBLICATIONS
`
`[21] Appl. No.: 998,879
`
`IBM Technical Disclosure Bullitin, IBM Corp., Sep. 1989,
`vol. 32, No. 4A, pp. 467.
`
`(22] Filed:
`
`Dec. 28, 1992
`
`“Motherboard Convertibility,” BYTE, Jun. 1991, p. 68.
`
`Related U.S. Application Data
`
`[63] Continuation of Ser, No. 748,780, Aug. 22, 1991, aban-
`doned.
`
`Judy Wong, Modular CPU Upgrade Comparison of Acer,
`ALR and AST, Jun. 13, 1991, pp. 1-2.
`
`Electronic Engineering Times, “Intel Rolls Out Road Map:
`At PC EXPO: Upgrade Plans and 586 Hints,” Jul. 9, 1991.
`
`Tint, C18 iecccccccssssssssssssssssecsssssssnssensessvess GO6F 15/76
`(51]
`[52] US. Che eeececssssensesesscssessnsascssecnensneesaeeanseseessesnecs 395/500
`[58] Field of Search.
`..........ccccssssscsceesees 395/500, 800
`
`Spiegelman, Lisa L., “12 New Microprocessors to be
`Unleashed by Intel: Move Could Speed User Upgrades,”
`Computer Reseller News, Jui. 1, 1991.
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`7/1983 Kaufman et al. oieesse 395/400
`Re. 31,318
`3/1973 Edstrom et al. .
`3,721,961
`2/1978 Fox et al..
`4,075,693
`7/1981 Grants et al. wenn 395/425
`4,281,392
`4/1984 Adcock .
`4,443,846
`11/1984 Stiffler et al. .
`4,484,273
`S/L9B6 Wade et al.
`.....seseresesssesseesees 395/725
`4,591,975
`4,703,419 10/1987 Krause et ab.
`ou.
`ecesssseessecneee 395/725
`
`4,716,526 12/1987 Mori et al. oo...
`eseesneee 395/800
`
`4,860,252
`8/1989 Sykord ....cscessessesersescesensees 395/400
`4,862,355
`8/1989 Newman etal. .
`. 395/500
`4,899,306
`2/1990 Greer.........
`
`. 395/425
`
`4,908,789
`3/1990 Blokkum etal.
`4,947,478
`8/1990 Maeno.......
`
`
`4,951,248
`8/1990 Lynch.........
`4,953,930
`9/1990 Ramscy Ct al, ccsssersenscseseeen 350/357
`4,964,074 10/1990 Suzuki et al.
`.
`5,077,686 12/1991 Rubinstein... sesesseecees 395/550
`5,101,342
`3/1992 Namimoto .
`5,109,506
`4/1992 Begun...eceeeeeeesereereees 395/575
`5,297,272
`3/1994 Luctal..
`
`Primary Examiner—Parshotam S. Lall
`Assistant Examiner—Richard L. Ellis
`Attorney, Agent, or Firm—David N. Slone; Townsend and
`Townsend and Crew
`.
`
`[57]
`
`ABSTRACT
`
`An upgradeable/downgradeable data processing system
`capable of operating with different types of central process-
`ing units (CPU). The system hasa first socket for registration
`of a first CPU and a second socket for registration of a
`second CPU. Meansare provided for preventing possible
`signal contention betweenthe first and second CPU,andfor
`synchronizing clocks for operating a CPU with the system
`clock. Meansare also provided for interfacing with a copro-
`cessor associated with the different types of CPU as well as
`for adjusting the signals to and from the CPUto the signal
`width of the system.
`
`26 Claims, 15 Drawing Sheets
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`U.S. Patent
`
`Oct. 3, 1995
`
`Sheet 1of15
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` §
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`5,455,927
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`MAPS
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`U.S. Patent
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`Oct. 3, 1995
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`U.S. Patent
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`Oct. 3, 1995
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`U.S. Patent
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`Oct. 3, 1995
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`5,455,927
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`U.S. Patent
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`Oct. 3, 1995
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`1
`DUAL SOCKET UPGRADEABLE
`COMPUTER MOTHERBOARD WITH
`AUTOMATIC DETECTION AND
`ENABLEMENTOF INSERTED UPGRADE
`CPU CHIP
`
`This is a file wrapper continuation application of U.S.
`patent application Ser. No. 07/748,780,filed Aug. 22, 1991
`now abandoned.
`
`TECHNICAL FIELD
`
`This invention relates in general to a data processing
`system capable of operating with different types of central
`processing units (CPU).
`
`BACKGROUND OF THE INVENTION
`
`5,455,927
`
`2
`80x86 where x represents a different generation of micro-
`processors.
`Some generations have submodels. For example, the ’386
`series of microprocessors includes 80386SX (also known as
`P9) and 80386DX and the ’486 series of microprocessors
`includes 80486DX. Moreover, generation of these comput-
`ers are also classified in accordance with their respective
`operation clock frequencies. For example, 80386 has. sub-
`models that run on 16 MHz, 20 MHz, 25 MHz and 30 MHz
`and 80486 has submodels that run on 20 MHz, 25 MHz,33
`MHz and 50 MHz. However,the differences between dif-
`ferent generations of microprocessors are usually greater
`than the differences between submodels.
`
`10
`
`To make upgrading more economical, the motherboard of
`some prior art computer systems are modulized so that the
`CPUand other relevant circuits (e.g. controller circuits) are
`put onto a special board. The special board can be swapped
`when a new CPU is introduced. In comparison with buying
`a whole new computer, upgrading a computer with modu-
`lized boards is of course more economical. However,as the
`associated circuits in the special boardstill constitute a high
`percentage of its cost, a substantial waste will still be
`incurred in upgrading a modulized CPU board.
`Modulized CPU boards also take up space, a undesirable
`result in view of the current demand for smaller and more
`compact computers.
`Currently, the more popular microprocessors used by the
`industry are the Intel microprocessors model numbers 8086,
`80286, 80386 80486 and 80487SX (80487SX,also known
`as P23N, is a microprocessor having an internal coproces-
`sor). Fhese Intel computers are sometimes referred to as
`
`55
`
`60
`
`65
`
`For a motherboard to be able to operate with different
`types of CPU,the different characteristics of the different
`types of CPU must be considered. Also needed to be
`considered are the specifications of an interface controller
`(such as the Acer M1209interface controller) which controls
`New microprocessors are introduced at such faster and
`the interface between the CPU and system devices.
`faster pace that it seems a new model of microprocessor is
`In addition, for a motherboard to be able to operate with
`introduced once every two years or even sooner. As capa-
`different types of CPU (e.g. 80486 or 80386), the following
`bility and/or speed of newly introduced microprocessors
`technical problems must be considered:
`frequently surpass older products and as they tend to be
`(a) Clock Synchronization
`more adapted to needs of the market, they are usually more
`For example,
`the meaning of “20 MHz” in a model
`expensive. But whenstill newer products are introduced, the
`80386/20 MHz CPUis different from the meaning of “20
`prices of these once-new products usually drop drastically.
`MHz”in a model 80486/20 MHz CPU. In a model 80386
`On the other hand, new application software are intro-
`CPU, a 40 MHzclock is applied to the CPU chip, and “20
`duced almost daily which offer more user-friendly and more
`MHz”actually means the frequency of the clock controlling
`powerful
`functions. But
`these new software typically
`30
`internal operations. For a model 80486 CPU, ‘20 MHz”
`demand more and more processing power. Asaresult, users
`means the clock frequency of the external clock applied to
`frequently find their computers not powerful enough to run
`the chip. In other words, the frequency of the external clock
`new software one or two years after the purchase thereof.
`to the model 80386/20 MHz CPUis actually double that of
`Those given the responsibilities of procuring data processing
`the model 80486/20 MHz CPU.
`equipment, and users in general, therefore, face a problem,
`what computer to purchase and whenis the most appropriate
`time to purchase a new computer.
`Basic components of a typical data processing system
`include a central processing unit (CPU), memories, control
`circuits (e.g. clock generators) and interface circuits (e.g.
`bus interface). In most personal computers, the CPU resides
`in a main processor chip, e.g. the Intel 80x86. Becauseit
`performs logic and arithmetic functions of the system, the
`CPUchipis the heart of the system and is a major deciding
`factor determining a system’s capability and performance.If
`the CPU can be changed,the performance of a system can
`be improved.It is thus desirable to have a computer that can
`be upgradeable when new and more powerful microproces-
`sors are introduced.
`
`15
`
`20
`
`23
`
`35
`
`40
`
`45
`
`Persons skilled in the art know that system clock is
`commonly divided into different phases and that a certain
`system activities, such as reading and storing of information,
`must occur at certain clock phases. For example, in a model
`80386 CPU,
`the cycles of the system clock are divided
`alternately into a phase 1 and a phase 2. Some system
`activities, such as the initiation of a CPU cycle (at which
`time the Address Status signal ADS# is activated) must
`occur at phase 1, and other system activities, such as reading
`the CPU Ready signal (CPURDY#) (which signals the end
`of aCPU cycle) must be performed when phase 2 is changed
`to phase 1. For 80486 and 80386 to beable to operate in the
`same motherboard, clock phase problems mustbe solved.
`(b) Signal contention at the system bus
`Most CPUs go through initialization before they can
`begin normal operation. The initialization typically begins
`when an external signal (for example the CPURSTin the
`80x86 chips) is applied. The external signal causes the CPU
`to enter into RESET whereby the CPUpinsare set to certain
`levels (i.e. high “1”, low “0”, floating “F’ or undefined).
`An external HOLDsignal can be applied to cause certain
`pins of the 80386 to float and electrically isolate from the
`bus. But some microprocessors such as the 80386 will
`ignore the HOLD signal at RESET. For other microproces-
`sors such as the 80486, floating pins can be achieved either
`by applying the HOLDsignalor bysetting the BOFF#signal
`to “0” (80386 does not have the BOFF# pin).
`For a motherboard to be able to operate when two
`different types of microprocessors, such as a 80486 and a
`80386, are present(so that the system can operate with either
`oneof the two microprocessors), signal contentionat the bus
`must be prevented. Prevention of signal contention can be
`
`

`

`5,455,927
`
`3
`prevented by performing a power-up sequenceto control the
`CPUs when entering into operation, taking into consider-
`ation their respective special characteristics.
`(c) Coprocessor interface
`Some microprocessor such as the 80386 have a copro-
`cessor (i.e. 80387) which resides in a separate chip. The
`main processor 80386 must issue a coprocessor cycle in
`order to communicate with its coprocessor. In other micro-
`processors such as models 80487SX and 80486DX CPU,the
`coprocessor is internal to the main processor chip and the
`main processor of these models of CPU can communicate
`directly with its internal coprocessor.
`In many microprocessor designs, the coprocessor must
`interface with an interface controller (which providesinter-
`face between the CPU and other system components).
`Different coprocessors interface differently with the inter-
`face controller. As a result, the interface signals between a
`CPU andtheinterface controller are different (for example,
`interface signals in the 80486 are Floating Point Error
`(“FERR#’)
`and: Ignore Numeric Error
`(“IGNNE#”),
`whereas interface signals in the 80386 are NOBUSY#,
`NSERROR# and N9PEREQ [“N9” represents 80387 and
`“PEREQ”
`represents COPROCESSOR REQUEST)).
`Therefore, for an interface controller to be able to work with
`coprocessors of different microprocessor models, coproces-
`sor interfacing must be provided with the capability to detect
`and process coprocessor errors of different types of copro-
`Cessors.
`
`(d) Different bus sizes and different bus signals
`Data addressing by different types of microprocessors is
`different. For example, 386SX uses a high portion address
`(A2-A23) to access units of 16 bits of data (a “word’’) and
`a low portion address (AO, Al, BHE#) to access either the
`whole word, the high byte (8 bits) of the word or the low
`byte (8 bits) of the word; however, 80486 uses the high
`portion address (A2-A3]) to access units of 32 bits of data
`and the low portion address (BE3#, BE2#, BEI#, BEO#) to
`determine whether the data to be accessed is the whole 32
`bits, or a 24-bit, 16-bit or 8-bit portion thereof.
`Moreover, some microprocessor such as the 80486 have
`an internal cache memory. In such types of microprocessor,
`a cacheable memory read cycle (also called a cacheline full
`cycle) is used to access 128-bit data from external memory.
`Therefore, for a motherboard to be ableto use different
`types of CPU such as either a 80486 or a 80386, bus
`interfacing must be provided to change and process signals
`from the different types of CPU.
`Accordingly, an object of the invention is to provide a
`clock synchronization means to handle clock synchroniza-
`tion problems associated with using different types of CPU.
`Another object of the invention is to provide a power-up
`sequencer which prevents signal contention caused by dif-
`ferent types of CPU.
`Another object of the invention is to provide a coproces-
`sor interface so that coprocessors of different types of CPU
`can operate with an interface controller which controls other
`system components.
`Another object of the invention is to provide a bus
`interface which can change and processsignals between the
`system bus and different types of CPU.
`Other objects and technical characteristics of the inven-
`tions will be understood with reference to the description of
`the preferred embodiment and the drawings.
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`SUMMARYOF THE INVENTION
`
`This invention provides a data processing system capable
`of operating with different types of central processing units
`(CPU). The system according to the present invention com-
`prises a clock synchronization means for synchronizing
`clocks of different microprocessor models to the system
`clock, a power-up sequencer for controlling a CPU in
`entering normal operation, a coprocessor interface for
`detecting a coprocessor and for handling errors in copro-
`cessors of different types of CPU, and a businterface for
`providing an interface between different types of CPU and
`the system bus.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a map showing the arrangementof FIGS.1a,1b,
`and 1c to form a complete figure,
`FIGS. 1B and 1C are a block diagram of part of a
`computer system in which the present invention is embod-
`ied,
`
`FIG. 2 is a diagram of the clock synchronizer of the
`system shown in FIG.1.
`FIG. 3 is a diagram of the power-up sequencer within the
`system shownin FIG,1,
`FIG.4 is a diagram of the coprocessorinterface within the
`system shown in FIG.1.
`FIG. 5 is a map showing the arrangement of FIGS. 5A and
`5B to form a complete figure.
`FIGS. 5A and 5Bare a diagram ofthe businterface within
`the system shown in FIG, 1 shown in FIG. 1.
`FIG. 6a and 6b are diagrams of the timing sequence
`generated by the clock synchronizer of FIG. 2.
`FIG. 7 is a diagram of the timing sequence of the
`power-up sequencer.
`FIG. 8 is a map showing the arrangement of FIGS. 8A,
`8B, and 8C to form a complete figure.
`FIGS. 8A, 8B, and 8C are a block diagram of another
`embodimentof the present invention.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`The present invention is described by way of example
`using 80486 and 80386.
`System Architecture
`FIG. 1 shows a computer system motherboard comprising
`a clock synchronizer 1, a power-up sequencer 2, a bus
`interface 15, an interface controller 6, a first CPU socket 9
`for plugging in with a first CPU, a coprocessor socket 8 for
`plugging in with a coprocessor, a second CPU socket 7 for
`plugging in with a second CPU, a power supply 10, an
`oscillator 11 and a system bus 12.
`The second CPU socket 7 according to this preferred
`embodiment is for receiving a CPU chip from the 80486
`family, such as 80487SX, 80486SX and 80486 (’486). The
`first CPU socket 9 according to this preferred embodiment
`is for receiving a CPU from the 80386 family, such as the
`80386SX, 80386DX and 80386 (’386). The coprocessor
`socket 8 is for receiving a coprocessor chip such as the
`80387DX or 80387SX.
`
`Interface controller 6 according to the preferred embodi-
`ment
`is an ASIC chip such as the Acer M1209 which
`provides interfacing between the CPU and the system.
`System start
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`5
`Referring to FIG. 1, when power supply 10 is turned on
`and power is supplied to the various parts of the system,
`oscillator 11 will generate a clock CLK2 that has a certain
`frequency F2. CLK2 is supplied to the clock synchronizer 1,
`the power up sequencer 2, the coprocessor socket8,thefirst
`CPU socket 9 and the system bus 12. Through the system
`bus 12, CLK2 is also supplied to the interface controller 6.
`The clock synchronizer 1 receives CLK2 and produces
`another clock CLK1at frequency Fl. This CLK1 from the
`clock synchronizer 1 is supplied to the power-up sequencer
`2, the second CPU socket 7 and the decoder 5 of the bus
`interface 15, Depending on the requirement of the CPU and
`other system components such as the interface controller6,
`F1 may be faster, slower or same as F2. In this preferred
`embodiment F2 is equal to two times F1.
`Power supply 10 has means for detecting stability of
`powerin the system. When powersupply 10 is turned on and
`the voltage level of the power supply becomesstable (e.g.
`whenfluctuations in the powerlevel are less than +x%ofthe
`voltage value), a power good signal (“POWERGOOD”)will
`be sent to the related units (e.g. the power-up sequencer 2,
`the interface controller 6). An inactive POWERGOOD
`(POWERGOOD="0”) meansthat the power supply has not
`yet been stable.
`.
`signal
`Interface controller 6 outputs a CPU reset
`(CPURST=“1”) which is high when poweris turned on and
`before it senses the POWERGOOD="1”signal. Upon sens-
`ing POWERGOOD="“1”, interface controller 6 will drop the
`CPURSTsignal to CPURST=“0”after it has performed an
`internal initialization.
`
`Clock synchronization
`*386 CPUs divide the cycles of CLK2 into two phases
`alternate to each other. The cycle that starts after the drop-
`ping of the RESETsignal (a high-to-low transition of the
`RESETsignal (CPURST)) and every other cycle that fol-
`lowsare identified as phase 2.
`Clock synchronization is performed to cause CLK1to be
`in-phase with CLK2. “In-phase” meansthat the rising edge
`of the CLK1 will occur substantially simultaneously with
`the rising edge of phase 2 of CLK2. The major reason for
`synchronization is to allow those units (i.e. the power-up
`sequencer 2, the second CPU socket 7 and the decoder 5)
`that receive CLK1 to operate in synchronization with the
`interface controller 6.
`
`The principle of operation of the clock synchronizer 1 is
`now described with reference to FIG. 2 and the timing
`diagrams of FIGS. 6a and 6b.
`The major components of the clock synchronizer 1 are a
`D-type flip-flop (e.g. 74F74) U1 whichis used for delaying
`CLK2, a NANDgate (e.g. 74F20) U4, an AND gate (e.g.
`74F11) US, and a J-K flip-flop (e.g. 74F109) U2.
`The preset input (PR) and the clear input (CL) of the
`D-typeflip-flop U1 are connected to +5 V. The data input (D)
`receives the CPUreset signal (CPURST)from the interface
`controller 6. The clock input (C) receives CLK2 from the
`oscillator 11. The data output (Q) of the flip-flop U1 is a
`delayed signal (DCPURST)of the CPU reset (CPURST).
`NAND gate U4 receives the inverted CPU reset signal
`(CPURST#) at a first input, the output (Q) of the D-type
`flip-flop U1 at a second input, and the output (Q) of the J-K
`flip-flop U2 at a third input. The NAND gate 44 output is
`connected to the J-input of the J-K flip-flop U2.
`AND gate US receives the inverted CPU reset signal
`(CPURST#) at a first input, the delayed CPURSTsignal
`(DCPURST)at a second input and the Q output of the J-K
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`flip-flop U2at a third input. The output of AND gate USis
`connected to K-input of the J-K flip-flop U2. The preset
`input (PR) and the clear input (CL) of the J-K flip-flop U2
`are connected to +5 V. Its clock input (C) receives CLK2
`from the oscillator 11. The outputof the J-K flip-flop U2 as
`a functionof its inputs is shown in the followinglogic table:
`
`TABLE1
`
`Input
`
`g
`
`0
`0
`1
`1
`
`K#)
`
`0
`1
`0
`1
`
`Output
`
`(Q)
`
`0
`Q
`, Q
`1
`
`Because the output signal from the NAND gate U4 and
`the output signal from the AND gate US are at opposite
`levels, J and K# will not be “0” concurrently or “1”
`concurrently. FIG. 6a shows the operation of the J-K flip-
`flop when CLK1 and CLK2 are in-phase. Betweent5 andt6,
`CPURST#=“1” and DCPURST="1”, therefore, if CLK2 is
`low,J will be “1” and K# will be “0” and the output Q ofthe
`J-K flip-flop U2 will, as shown in Table 1, will continue to
`toggle at each cycle of CLK2 whichis receivedat its input
`(C). Thus, the J-K flip-flop U2 will operate as a frequency
`divider to divide the frequency of CLK2. In other words, the
`output Q of the J-K flip-flop U2 will have a clock signal
`(CLK1) which frequency is half the frequency of CLK2
`received at the clock input (C) of the J-K flip-flop U2, as
`shown in FIG. 6a.
`But if CLK2 between t5 andt6 is “1” as shown in FIG.
`6b, so that CLK1 is out of phase with CLK2, then J will be
`“0” and K# will be “1”. As shown in Table 1, the output Q
`of the J-K flip-flop U2 will maintain its previous level. After
`point t6, however, DCPURST will change to “O”, so that
`=“1” and K#=“0", and the output Q ofthe J-K flip-flop U2
`will, as shown in Table 1, resume to toggle at each subse-
`quent cycles of CLK2 receivedat its input (C), at which time
`CLK1 and CLK2 will already be in-phase.
`Power-Up Sequence
`Since there is a possibility that both the first CPU socket
`9 and the second CPU socket 7 will be plugged in with a
`CPU,in which event, the signals from each of the two CPU
`may result in signal contention at the system bus 12.
`Signal contention at the system bus 12 is prevented by
`controlling the signal levels of the CPUs’ pins. Controlling
`the signal levels of the CPUs’ pins is in turn achieved by
`setting the CPU to a predeterminedstate.
`To set the CPU to a predeterminestate, it is first made to
`go through an internalinitialization. For the 80x86 micro-
`“processors, this is performed by applying an external CPU
`reset signal (CPURST) soas to cause the CPU to enter into
`RESET.In orderto cause a °386 atthe first CPU socket 9 to
`enter into RESET, the power-up sequencer 2 generates a
`PORSTsignal (i.c. PARST=“1”) to the "386 in the first CPU
`socket 9.
`
`Table 2 showsthesignal levels at the pins of the °386 at
`RESET (for example, ADS#="1”, D1S—D0=“F’”(floating),
`BHE#=“0", A23—-A1="1” and PPHLDA=“0”).
`POHLDA is actually the HLDA signal of the °386.
`Because the power sequencer 2 receives a HLDAsignal
`from boththe first CPU socket 9 and the second CPU socket
`7, this signal is named P9HLDAto moredistinctly point out
`that it is the HLDAsignal from the °386. Similarly, the
`HOLDsignal is renamed as P9HOLD for the same purpose.
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`P9HLDA(i.e. HLDA) is connected to +5 V through a
`resistor R3, but when ’386 enters into RESET, P9HLDAwill
`change from “1” to “0”.
`
`TABLE 2
`
`Pin name
`
`signal state of '386 at reset
`
`ADS#
`D15-D0
`BHE#
`A23-Al
`WIR#
`D/C#
`M/IO#
`LOCK#
`POHLDA (HLDA)
`
`1 (high)
`F (float)
`0 (low)
`1 (high)
`0 dow)
`1 (high)
`0 (ow)
`1 (high)
`0 (low)
`
`Similarly, to cause ’486 in the second CPU socket 7 to
`enter into RESET, a P23RST signal
`(P23RST=“1") is
`applied from the power-up sequencer 2 to the °486.
`Table 3 lists the signal levels of the pins of a ’486 (e.g.
`80486SX) at RESET. As shown in Table 3, at RESET, the
`logic states of A31-A2, BE3#-BE0#, PCD, M/IO# D/C#,
`W/R# BLAST# FERR# are undefined, D31-D0 are in high
`impedancestate, LOCK#, ADS#are in logic “1”, and BREQ
`and P23HLDAarein logic “0”.
`
`TABLE3
`Pin level when HOLD
`and BOFF# are inactive
`and 486SX is in RESET
`
`Undefined
`undefined
`undefined
`undefined
`undefined
`undefined
`undefined
`undefined
`high impedance
`1 (high)
`1 (high)
`0 (low)
`0 (low)
`
`PIN names
`
`A31-A2
`BE3#BEQ#
`PCD
`M/O#
`D/C#
`W/R#
`BLAST#
`FERR#
`D31-D0
`LOCK#
`ADS#
`BREQ
`P23HLDA (HLDA)
`
`P23HLDAis actually the HLDA signal of the 486.
`Because the power sequencer 2 receives a HLDAsignal
`from both the first CPU socket 9 and the second CPU socket
`7, this signal is named P23HLDAto more distinctly point
`out that it is the HLDA signal from the ’486.
`The BREQpin of the second CPU socket 7 is connected
`to the power-up scquencer 2. The BREQis pulled high to +5
`V via a resistor R2 so that if no CPU is plugged into this
`second CPU socket 7, the BREQ pin will be high. But when
`a CPU chipis plugged in and whenit is at RESET (i.e. when
`P23RST=“1”is sent by the power-up sequencer2), the level
`of BREQwill be “0”. From the “0” level of BREQ at reset,
`one can then ascertain that the second CPU socket 7 is
`plugged in with a "486.
`A person skilled in the art will understand that besides
`HLDA,other pins, such as HLDA, LOCK# and ADS# may
`also be used for purposes of ascertaining whether a CPU
`chip is plugged into the socket. However, if a pin such as
`LOCK# and ADS#are used, then such pin should be pulled
`to appropriate levels.
`the power-up
`To float
`the output pins of the °386,
`sequencer 2 sends PPHOLD="1” to the first CPU socket 9.
`Upon receiving PHHOLD=“1”, the ’386 in the socket will
`enter into HOLD and will return P9HLDA=“1” to the
`
`8
`power-up sequencer 2 to notify the power-up sequencer 2
`that °386 has entered into HOLD.
`
`Thelogic levels of the pins of the °386 in HOLDarelisted
`in the following Table 4:
`
`TABLE 4
`
`Pin Names
`Signalstate
`
`
`High “1”
`HLDA
`Float
`LOCK#, M/IO#
`Float
`D/C#, W/R#
`Float
`ADS#, A23-Al
`
`BHE#, D15-D0 Float
`
`Floating output pins of ’486 can be achievedbysetting it
`to HOLD.
`
`The condition under which ’486 can be put to HOLD is
`different from that of "386. When ’486 is in RESET
`(P23RST="1”) it can receive BOFF#="0” anytime to enter
`into HOLDstate. On the other hand, ’386 must have exited
`the RESET (P9RST=“0”) before a PPHOLD=“1” can cause
`it to enter into HOLD.
`
`Moreover, putting ’486 to HOLDcan be doneby applying
`either P23HOLD="1” (as with the ’386) or BOFF#="0".
`(386 does not have an input pin for BOFF#). But if the
`P23HOLDis used, ’486 will return a P23HLDAsignal,
`which will be sent to various system units such as the
`power-up sequencer 2 and the interface controller 6. Since
`the P23HLDA,if sent to the other units, may cause misin-
`terpretation and produce unexpectedresults, putting the ’486
`into HOLDin this preferred embodimentis thus performed
`by setting BOFF#="0” which will not cause °486 to return
`a P23HLDAsignal. Another advantage with using the
`BOFF#=“0”signal is that onceit is received, ’486 will enter
`into HOLD immediately.
`When 486 enters into HOLDstate, its pins will have the
`levels listed in the following Table 5.
`
`TABLE 5
`
`
`Pin name
`Signal state
`
`A2-A31
`Float
`DO-D31
`Float
`BEO#-BE3#
`Float
`ADS#
`Float
`MU0#
`Float
`DIC#
`Float
`W/R#
`Float
`BLAST#
`Float
`LOCK#
`Float
`PCD
`Float
`BREQ
`not float
`P23HLDA (HLDA)
`not float
`
`
`.FERR# notfloat
`
`By comparing Table 4 with Table 5, it can be seen that
`when one of the CPUs (386 or ’486) in the system is in
`HOLD,the output pins of the HOLDed CPU which other-
`wise would have conflicted with pins of the other CPU will
`float, and signal contention at the system bus 12 is pre-
`vented,
`
`With reference to FIGS. 3, 7 and 1, when power is
`supplied from the power supply 10, POWERGOOD="0”
`will be sent from the power supply 10 to the power-up
`sequencer 2 and the interface controller 6. The interface
`controller 6, in response to the POWERGOOD="0", sends
`CPURST="1”to the power-up sequencer 2. In response to
`CPURST="1”, power-up sequencer 2 generates P23RST=
`“1” to 486 and P9ORST="1” to ’386.
`
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`As shownin Tables 2 and 3, when ’486 and ’386 are both
`in RESET (P23RST=P9RST="1”), there will be signal con-
`tention between the pins of ’486 and the pins of ’386.
`Therefore, when power-up sequencer 2 receives P23RST=
`“1”, it sends BOFF#=“0”to the *486 to cause the ’486 to
`enter into HOLD. Referring to FIG. 3, P9RST=“1”is also
`generated, butit is delayed by a delay circuit U8 (a 74F174),
`The reason for causing the °486 to enter into HOLD
`(P23RST="1” and BOFF#=“0") first when the ’386 is in
`RESETis to prevent signal contention between the pins of
`the °386 and the pins of ’486. Another reason is because
`when °386 is in RESET,it cannot enter into HOLDstate
`directly as can the *486.
`With reference to Table 2, FIGS. 3 and 7, when ’386is in
`RESET (P9RST="1”), P9IHLDA="0” and HLDAfrom the
`power-up sequencer 2 to the interface controller 6 will be
`“0”.
`
`From Tables 3 and 5, it can be seen that when the second
`CPU socket 7 is plugged in with a ’486 chip and whenthis
`’486 enters into HOLD (P23RST=“1”, BREQ=“0”), BREQ
`will be “0”. This BREQ="0”signal is sent to the power-up
`sequencer2.
`As described above, when the interface controller 6
`receives POWERGOOD="1” (meaning that powersupplyis
`stable), the interface controller 6 will send a CPURST=“0”
`to the power-up sequencer 2. When the power-up sequencer
`2 senses CPURST=“0” and BREQ="0”, it knows that there
`is a ’486 in the second CPU socket 7. A timing control logic
`means U7 (116R8PAL) in the power-up sequencer 2 will set
`P23#="0” to inform the system, including the coprocessor
`interface 3, that there is a 486 in the system. P23#="0”also
`causes the power-up sequencer 2 to generate the PPHOLD
`signal to the first CPU socket 9 to put the "386 into HOLD.
`In addition, the timing control logic means U7 (16R8PAL)
`generates a del