United States Patent
`US 6,735,707 B1
`(10) Patent No.:
`(12)
`Kapil
`(45) Date of Patent:
`*May 11, 2004
`
`
`US006735707B1
`
`(54) HARDWARE ARCHITECTURE FORA
`MULTI-MODE POWER MANAGEMENT
`SYSTEM USING A CONSTANT TIME
`REFERENCE FOR OPERATING SYSTEM
`SUREORT
`
`5,987,614 A * 11/1999 Mitchell et al. oo... 713/300
`9/2000 Orton et al. one 327/44
`6,118,306 A
`
`6,397,340 B2 *
`5/2002 Watts et al.
`.....
`veo LLB/322
`tee e ee eee cee eeeeeeeeeeees 713/322
`6,668,330 Bl + 12/2003 Kapil
`FOREIGN PATENT DOCUMENTS
`
`(75)
`
`Inventor: Sanjiv Kapil, Sunnyvale, CA (US)
`
`EP
`
`O 487 049 AL
`
`5/1992 eee GO06F/1/32
`
`(73) Assignee: Sun Microsystems, Inc., Santa Clara,
`C&LUS)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 604 days.
`
`(*) Notice:
`
`OTHER PUBLICATIONS
`International Search Report, dated Nov. 25, 2002, 7 pages.
`* cited by examiner
`Primary Examiner—Thomas Lee
`Assistant Examiner—Albert Wang
`(74) Attorney, Agent, or Firm—Osha Novak & May L.L-P.
`This patent is subject to a terminal dis-
`(57)
`ABSTRACT
`dleimer;
`Asystem for implementing a power management system in
`(21) Appl. No.: 09/698,427
`a computer system using a constant
`time reference to
`an
`support an operating system. The system uses a PCI clock
`Filed:
`(22)
`et, 27,2000
`(SL) Unt. CI? ie ceccccccecccccecseeeeesseesteesenseessees GO6F 1/32_signal and a CPU clock signalto generate the constanttime
`(52)
`UWS. Che veceececceecceen 713/322; 713/400; 713/502
`reference such that the operating system uses the constant
`(58) Field of Search ...0...0.0ee 713/322, 400
`time reference when the power management system causes
`713/502
`the computer system’s CPU frequency to change or when
`the CPU frequency has changed. The power management
`system comprises of circuitry to interface between normal
`power management system operations with that of the
`operations used to support the operating system.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`5,319,772 A
`5,428,790 A
`
`6/1994 Hwang ....ccccccccecerreee 395/550
`6/1995 Harperet al. 0... 395/750
`
`20 Claims, 8 Drawing Sheets
`
`int_PCI
`
`44
`
`ESTAR_MODE
`
`1:0]
`
`stick_alm
`
`
`
` STICKDP
`
`
`TRAP
`
`Google Exhibit 1026
`Google Exhibit 1026
`Google v. Valtrus
`Google v. Valtrus
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 1 of 8
`
`US 6,735,707 B1
`
`18 \
`
`20
`
`16
`
`
`
`22
`
`database
`system
`
`
`
`
`
`
`
`compiler
`
`assembler
`
`text editor
`
`system and application programs
`
`
`operating system
`
`12
`
`computer hardware
`(microprocessor,
`memory, etc.)
`
`10
`
`Figure 1 (prior art)
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 2 of 8
`
`US 6,735,707 B1
`
`30
`
`32
`
`
`
`
`Power
`
`
`Management
`34
`Unit
`
`
` CLOCK
`
`CONTROL
`
`
`
`SDCLK
`
`Figure 2
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 3 of 8
`
`US 6,735,707 B1
`
`NORMALFS
`
`2E*activVe)(‘1/2 E* SLEEPon
`
`
`
`
`
`
`
`1/6 E* ACTIVE
`
`Figure 3
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 4 of 8
`
`US 6,735,707 B1
`
`
`
`int_PCl
`
`
`44
`
`
`
` enable
`ESTAR_MODE
`
`STICKDP
`
`
`
`Figure 4
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 5 of 8
`
`US 6,735,707 Bl
`
`
`
`miu_stick_cmp_rd_en
`
`CPU clock
`
`pbm_sync_div
`
` miu_stick_reg
`STIEKDP
`
`miu_stick_reg_rd_en
`
`miu_stick_cmp_wr_en
`
`
`
`
`pdp_mcu_pio_data{31:0
`
`miu_estar_mode_rd_en
`
`miu_estar_mode_wr_en
`
`Figure 5
`
`to MCU_PDP_PIO path
`
`stick_alm
`(to Trap)
`
`estar_mode[1:0]
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 6 of 8
`
`US 6,735,707 B1
`
`eeSL. Afei
`
`70
`
`1
`i
`1
`
`i
`
`‘
`'
`'
`
`oo.
`miu_stick
`
`reg.wren
`
`ode_wr_en
`‘
`miu_estar_m ee mT ene
`CE
`
`62
`
`78 #
`
`pT TTT gree:
`pbrn_
`syne. |
`ceucoa!|SYNCHRONIZER +2 tis[OR|U
`
`i
`|
`1
`\ nf aes eee eeeees1! 76
`74 i‘
`pdp_meu_pio62:0)
`4
`
`88
`
`\
`'
`'1
`x
`fo PLL
`'
`Pa
`
`
`
`
`unit
`‘
`STICK_REG
`CPUClock A. oe
`—ee\
`{‘1
`
`ct
`
`0462.0)
`
`cpu
`
`ce
`
`1620}
`
`83
`
`80
`
`pdp_mcu_pio{63}
`CPU Clock
`
`miu_slick_cmp_wr_en
`~n
`
`a*
`
`‘86
`
`:
`
`v
`+
`1
`
`84
`
`TRAP
`
`stick_alm
`
`trap to
`processor
`
`Figure 6
`
`iu_slick_
`miu_stick_|
`reg_td_en
`emp_rd_e
`miu_estar_m
`ode_rd_en
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 7 of 8
`
`US 6,735,707 Bl
`
`ESTAR_MODE{1}
`
`CPU clock
`
`
`
`
`
`
`ESTAR_MODE(0]
`
`CPU clock
`
`to PLL Divider 1
`to PLL Divider 2
`to PLL Divider 3
`
`
`
`
`
`
`
`
`mux_sel[74]
`
`mux_sel(0}
`
`Figure 7
`
`

`

`U.S. Patent
`
`May11, 2004
`
`Sheet 8 of 8
`
`US 6,735,707 B1
`
`110
`
` S/W can write to
`ESTAR_MODE Register
`
`timeout
`
`timeout
`
`Wait n CPU Clocks
`
`
`
`112
`
`Figure 8
`
`

`

`US 6,735,707 B1
`
`1
`HARDWARE ARCHITECTURE FORA
`MULTI-MODE POWER MANAGEMENT
`SYSTEM USING A CONSTANT TIME
`REFERENCE FOR OPERATING SYSTEM
`SUPPORT
`
`BACKGROUND OF THE INVENTION
`
`With reference to FIG. 1, a modern computer system may
`be divided roughly into four conceptual elements: the hard-
`ware (10), the operating system (12), the application pro-
`grams (14), and the users (16, 18, 20, 22). The hardware
`(10), i.c., the microprocessor, the memory, and the input/
`output devices, provides the basic computing resources. The
`application programs (14), such as compilers, database
`systems, software, and business programs, define the ways
`in which these resources are used to solve the computing
`problems of the users. The users (16, 18, 20, 22), people,
`machines, and other computers, use the application
`programs, which in turn employ the hardware,
`to solve
`numerous types of problems.
`An operating system (“OS”) (12)is a program that acts as
`an intermediary between a user of a computer system and the
`computer hardware. The purpose of an operating system is
`to provide an environment
`in which a user can execute
`programs in a convenient and efficient manner. A computer
`system has many resources (hardware and software) that
`may be required to solve a problem,e.g., central processing
`unit (“CPU”) time, memory space, file storage space, input/
`output (“I/O”) devices, etc. The operating system acts as a
`manager of these resources and allocates them to specific
`programs and users as necessary for tasks. Because there
`may be many, possibly conflicting, requests for resources,
`the operating system must decide which requests are allo-
`cated resources to operate the computer system efficiently
`and fairly.
`Moreover, an operating system can be characterized as a
`control program. A control program controls the execution
`of user programs to prevent errors and improper use of the
`computer. It is especially concerned with the operation of
`I/O devices. In general, operating systems exist because they
`are a reasonable way to solve the problem of creating a
`usable computing system. The fundamental goal of a com-
`puter system is to execute user programs and make solving
`user problems easier. Toward this goal, computer hardware
`(10) is constructed. Because bare hardware alone is not
`particularly easy to use, application programs are developed.
`These various programs require certain commonoperations,
`such as those controlling the I/O operations. The common
`functions of controlling and allocating resources are then
`brought together into one piece of software: the operating
`system. The operating system,in turn, needs a constant ime
`reference to support the aforementioned tasks and adminis-
`trative tasks such as thread scheduling, process scheduling,
`event scheduling, and other system related activities.
`A typical operating system uses the CPU clock for its
`constant time reference. Modern CPUs have frequencies
`between 166 MHz to over 600 MHz. For example, an
`UltraSparc-IIe microprocessor developed by Sun Microsys-
`tems in Palo Alto, Calif., runs at speeds greater than 500
`MHz, meaning that the processor goes through more than
`500x10° CPU clock cycles per second.
`In order to conserve cnergy, some computer systems
`incorporate power control mechanisms. For example,
`Energy Star (“E*”) power requirements require system
`power consumption to be lowered to 15% of the normal
`
`10
`
`15
`
`20
`
`30
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`operating power consumption level whenthe system isidle.
`In order to meet this goal, the system must turn off (or lower
`the operating frequencies of) inactive devices (disk drives,
`network cards,etc.). In addition, the CPU itself should enter
`into power saving mode, becauseit is likely to be the most
`power-consuming device in the system.
`To save power, the CPU must lowerits operating fre-
`quency. The CPU cannot be turned off entirely becausethis,
`in effect, would shut down the entire system. When the CPU
`lowers its operating frequency, the time reference for the
`operating system changes, and it consequently performsits
`duties depending upon a varying time reference. During the
`change over to different frequency modes,
`the operating
`system loses its absolute reference of time, which it had
`before the frequency change, and counters using the CPU
`core clock increment at different rates as the frequency
`changes.
`Because the operating system designates and allocates
`system resourcesto different tasks, it must have a constant
`time reference in order to perform those tasks effectively and
`efficiently. If there is not a constant time reference, the
`operating system is forced to attempt to schedule tasks using
`a fluctuating time reference. This results in the loss of many
`clock cycles while the operating system waits for a constant
`time reference to be established, and eventually this effect
`inhibits system performance.
`The prior art allows an operating system to delay its
`requests and interrupts to system hardware when the CPU
`core frequency of the system is being changed. Hardware
`embodying such a system includes registers which basetheir
`clock cycles on a CPU clock to generate periodic interrupts
`to the operating system. However, when the CPU clock
`frequency changesas the system enters or exits a power save
`mode, the interrupt periods vary and therefore the operating
`system schedules events indeterministically. The prior art
`also embodies systems in which the operating system simply
`and waits for the system to complete its frequency change
`transition and accepts the loss of many clock cycles. All
`requests and interrupts are stalled until the system frequency
`has been changed to a desired frequency.
`SUMMARYOF THE INVENTION
`
`the invention relates to a system for
`In one aspect,
`implementing a power management scheme to conserve
`computer system power when computer resources are idle.
`The system further provides a plurality of power saving
`modesthat can be entered into when designated by system
`software. The system further includes implementation of the
`power management scheme with minimal changesto pre-
`existing system conditions.
`In another aspect, the invention relates to a method for
`providing a constant time reference for operating system
`support for event scheduling, process scheduling, and other
`administrative purposes. The method further includes pro-
`viding a constant time reference when the system is chang-
`ing to a power save modeand also whenthe system is in a
`power save mode.
`In another aspect, the invention relates to a method for
`software to implement the power management scheme. The
`method includes software controlling the power manage-
`ment scheme by monitoring and determining when com-
`puter resources are idle and how the hardware should react
`to a designated power save mode request.
`Other aspects and advantages of the invention will be
`apparent from the following description and the appended
`claims.
`
`

`

`US 6,735,707 B1
`
`3
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 showsa typical prior art computer system.
`FIG. 2 is a block diagram of a power management scheme
`in accordance with an embodimentof the present invention.
`FIG. 3 shows a flow chart describing a process in accor-
`dance with an embodimentof the present invention.
`FIG. 4 is a block diagram of a power management system
`in accordance with an embodimentof the present invention.
`FIG. 5 is a high-level block diagram of a computer
`subsystem in accordance with an embodimentof the present
`invention.
`
`FIG. 6 is a low-level block diagram of a power manage-
`ment system in accordance with an embodiment of the
`present invention.
`FIG. 7 is a block diagram of a computer subsystem in
`accordance with an embodiment of the present invention.
`
`FIG. 8 shows a flow chart describing a process in accor-
`dance with an embodimentof the present invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The present invention relates to a system for implement-
`ing a power management scheme that conserves computer
`system power when computer resources are idle. The system
`also relates to a system for providing a constant
`time
`reference for operating system (“OS”) support using a
`peripheral component interconnect (“PCI”) interface when
`the computer system is changing between different CPU
`frequencies. In order to provide a constant absolute refer-
`ence of time to the operating system, embodiments of the
`present invention implement a scheme that uses the PCI
`frequency along with a CPU frequency to generate a con-
`stant time reference frequency.
`The PCI is a local bus standard that most modern com-
`puter systems incorporate within their respective systems to
`connect different system components. The PCI is a 64-bit
`bus, though it is usually implemented as a 32-bit bus. It
`usually operates at clock speeds of 33 or 66 MHz.
`In order to meet the Estar (“E*”) requirements mentioned
`above, a system must implement a method by which it can
`conserve power by lowering its CPU frequency. Table 1
`provides the estimated power consumption levels in differ-
`ent frequency modes of the UltraSparc-IIc microprocessor.
`
`TABLE1
`
`Power Consumption Levels in
`Different Frequency Modes of UltraSpare-Ic
`
`L* Mode
`None
`Power Save
`Power Save
`
`fopy (CPU frequency)
`1/1 = 500 MIIz
`1/2 = 250 MHz
`1/6 = 83.3 MHz
`
`Power Consumption
`12 W
`<6 W
`<3 W
`
`the
`To achieve the power consumption requirements,
`UltraSparc-Ile implements a power management scheme by
`changing the CPU clock to one-half (%) and one-sixth (%)
`of the normal operating frequency. Typically, the scheme
`specifications are programmable by system softwarc. Table
`2 provides the sequences the system software must go
`through to power down and powerup the system (discussed
`further below with reference to FIG. 3).
`
`10
`
`15
`
`20
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`
`TABLE 2
`
`Power Down/Up Sequence
`
`Current Mode
`al
`1/2
`1/6
`12
`
`Desired Mode
`1/2
`1/6
`1/2
`11
`
`Sequence
`1/1 -> 1/2
`1/2 -> 1/6
`1/6 -> 1/2
`1/2 -> 1/1
`
`The limitation of the % ratio is due to the internal PCI
`synchronizer’s requirementof fopy>=2 fexrernarpor One
`difference between a system operating at normal frequency
`and a system operating in power save modeis that all
`requests and interrupts are serviced at a lower clock rate
`when the system is in the power save mode. System software
`monitors the system traffic and can decide to switch the
`internal CPU clock back to any mode the software deems
`appropriate.
`FIG. 2 is a block diagram of an exemplary embodimentof
`the present invention. The figure showsa top-level hardware
`layout of a power management scheme which includes a
`power managementunit (30). The default operating mode of
`the power managementunit (30) is to operate at full power.
`When system software detects that a computer system has
`been idle for a certain period f of time, the software, by
`writing into an Estar Mode register (“ESTARMODE”)
`(not shown), commands system hardware to power down.
`Upon this command,
`the power management unit (30)
`sequences through a series of steps in order to power down
`to a designated power save mode. The power management
`unit
`(30)
`first programs synchronous dynamic random
`access memory (“SDRAM”) (32) to operate in self-refresh
`mode. The SDRAM(32)is a type of dynamic random access
`memory (“DRAM”) that can operate at much higher clock
`speeds than conventional memory. Prior to entering into the
`power save mode, the SDRAM (32) synchronizesitself with
`the computer system’s CPU bus and is refreshed continu-
`ously in order to function. However, whenentering into the
`power save mode, the power management unit (30) pro-
`grams the SDRAM (32) to operate in self-refresh mode so
`that the SDRAM (32) refreshes independent of the CPU
`clock. Further, the SDRAM (32) consumesless power when
`it
`is in self-refresh mode than when it
`is in a normal
`
`operation mode.
`The SDRAM (32) can be configured to operate in self-
`refresh mode by writing into a memory control register
`(“MCO0”) (not shown). The memory control register is a
`register which software writes to in order to indicate the
`desired status for a particular memory unit. When system
`software instructs the hardware to power down,the system
`software enables a self-refresh enable bit (MCO0[33]=1).
`Oncethis bit is enabled, the software generates a command
`to the hardware, which in turn, changes the operating mode
`of the SDRAM (32) to self-refresh mode, i.e., sleep mode.
`The hardware will automatically re-activate the SDRAM
`(32) on any incoming access to the SDRAM (32), i-e., when
`data needsto be retrieved from the SDRAM (32). Once the
`access is complete, the hardware puts the SDRAM (32) back
`into self-refresh mode. In order to return to normal SDRAM
`(32) operation, the system software must explicitly clear the
`self-refresh enable bit (MC0[33]=0).
`Once the SDRAM (32) is programmedto opcrate in sleep
`mode, the power management unit (30) lowers the CPU
`operating clock frequency to % or % of the normal operating
`frequency by generating a signal to a clock control unit (36).
`
`

`

`US 6,735,707 B1
`
`5
`The clock control unit (36) usually manages all clock
`signals, including CPU clocksignals and PCI clock signals.
`The power management unit (30) then proceeds with
`generating clock control signals via a general purpose output
`(“GPO”) unit (34) to the clock control unit (36) to lower or
`deactivate the operating frequency of certain external PCI
`devices. Two GPO pins (not shown) are provided to help
`instruct the clock control unit (36) to either slow down the
`clock from 33 MHz to 0 MHz orto increase the clock speed
`from 0 MHz to 33 MHz for external PCI devices.
`
`In order to generate a constant time reference signal to the
`operating system, the power management unit (30) incor-
`porates a PCI bus module (“PBM7”) (38). The PBM (38) is
`a main portion of a PCI interface between an external device
`and internal system hardware. The PBM (38) handles the
`timing of programmed input/output (“PIO”) requests as well
`as direct memory access (“DMA”)requests that are initiated
`by external PCI devices. PIO is a method of CPUinitiated
`data transfer between two devices. In embodiments of the
`
`present invention, the power managementunit (30) uses a
`portion of the PBM (38) to generate the constant
`time
`reference signal using a PCI clock and a CPU clock
`(discussed below).
`System software implements the power management
`scheme as illustrated by the flow diagram in FIG. 3. Table
`3 lists the necessary steps for each transition shown in FIG.
`3.
`
`TABLE 3
`
`Steps for Individual Transitions Between Operating Modes
`
`Transition Steps
`
`A
`
`B
`
`c
`
`D
`
`E
`
`qonm
`
`Program new SDRAM Refresh Count for fopu2
`Program 2 E* mode in ESTAR_MODE
`Wait for 16 clock cycles
`Program SDRAM Refresh count for fopy
`Program E* mode in ESTAR_MODE
`Wait for 16 clock cycles
`Program SDRAM Refresh count for fopy
`Reset SDRAM Self Refresh Enable bit and activate devices
`Program 2 E* mode in ESTAR_MODE
`Wait for 16 clock cycles
`Program new SDRAM Refresh count for fopry.
`Program E* mode in ESTAR_MODE
`Shutdown external devices
`Set SDRAM Self Refresh Enable bit
`Program SDRAM Refresh count for fopy2
`Reset SDRAM Self Refresh Enable bit
`Program E* mode in ESTAR_MODE
`Wait for 16 clock cycles
`Activate external devices
`Set SDRAMSelf Refresh Enable bit
`Reset SDRAM Self Refresh Enable bit
`Program SDRAM Refresh count for fupuys
`Program E* mode in ESTAR_MODE
`Wait for 16 clock cycles before transition
`
`
`
`Whenever a transition occurs from a higher mode to a
`lower mode, i.e., transitions A, D, and H, considerations
`need to be madein addition to the steps listed in Table 3. For
`transition A, system software must read an original auto-
`refresh count and program a new auto-refresh count (less
`than original auto-refresh count based on SDRAM
`specifications). Thereafter,
`it must wait (64*auto-refresh
`count cycles+new auto-refresh cycles) to ensure that the new
`refresh countis loaded into hardware. Referring to transition
`D, system software must read the original auto-refresh count
`and program a new auto-refresh count (less than original
`auto-refresh count based on SDRAM specifications).
`Thereafter,
`it must wait (64*% mode auto-refresh count
`
`6
`cycles+new auto-refresh count cycles) to ensure the new
`refresh count
`is loaded into hardware. Furthermore, for
`transition H, system software must read the original auto-
`refresh count and program a new auto-refresh count (less
`than original auto-refresh count based on SDRAM
`specifications).
`FIG. 4 is a hardware block diagram for a power manage-
`ment system of an exemplary embodiment of the present
`invention. The figure includes a PBM unit (40) with a
`portion of the PBM unit (40) designated to serve as a PBM
`synchronizer unit ((PBM_SYNC”) (42). The PBM_SYNC
`(42) serves to generate a constant frequency using a PCI
`frequency signal, i.e., int_PCI, and a CPU clock frequency
`signal, i.c., CPU clock. The PBM_SYNC(42) comprises a
`divide by 12 frequency counter (44) and a frequency syn-
`chronizer (46). The int_PCI frequency signal, which is the
`internal PCI clock frequency, is provided at the input of the
`divide by 12 frequency counter (44). The divide by 12
`frequency counter (44) divides the int_PCI frequency signal
`by 12 and then outputs a divided int_PCI frequency signal.
`The divided int_PCI frequency signal is then fed into the
`frequency synchronizer (46) which synchronizes the divided
`int_PCI frequency signal and the CPU clock frequency
`signal. For example,
`in one embodiment of the present
`invention, the int_PCI frequency signal is 66 MIIz and the
`CPU clock frequency signal is 500 MHz. Therefore the
`PBM_SYNC (42) outputs a 5.5 MHz frequency signal
`which is synchronized to the CPU clock frequency signal.
`The resulting synchronized output signal from the PBM
`SYNC (42) serves as a clock_enable signal for a STICKDP
`unit (48). The STICKDPunit (48) comprises circuitry that
`generates periodic interrupts to an operating system for
`event and process scheduling. The clock_enable signal that
`is provided as an input to the STICKDPunit (48) serves to
`give the STICKDP unit (48) a reference of time for its
`operations. Discussions below with reference to FIGS. 5 and
`6 explain in more detail the operation of the STICKDPunit
`(48).
`The STICKDP unit (48) passes twobits of data to a phase
`locked loop unit (“PLL”) (50). The two bits of data are
`passed on a two-bit bus, i.c., ESTARMODE[1:0] bus, and
`include the values of the two bits in the Estar Moderegister.
`The PLL (50) is used by the power management scheme to
`store specific power save mode values. For example, the
`PLL (50) comprises dividers (not shown) whichare assigned
`specific values indicating particular power save modes.
`Additionally, when certain conditions (discussed below) are
`met,
`the STICKDP unit (48) outputs a stick_alm signal
`whichservesto notify a trap (“TRAP”) unit (52) that a trap
`signal needs to be generated to the processor. A more
`detailed discussion of the aforementioned components is
`given below.
`FIG. 5 is a high-level block diagram for a STICKDPunit
`(60) of an exemplary embodimentof the present invention.
`The STICKDPunit (60) has input and output signals which
`are shown in FIG. 5 and described in Table 4.
`
`TABLE 4
`
`Signal and Bus Descriptions for FIG. 5
`
`10
`
`15
`
`20
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`Signal Name
`
`Input/
`Output Description
`
`65
`
`CPU clock
`pbm_sync_div
`Miu stick reg wr
`
`en
`
`Input
`Input
`Input
`
`CPU clock
`clock_enable for STICKDP
`STICK REGwrite enable
`
`

`

`US 6,735,707 B1
`
`7
`
`TABLE 4-continued
`
`Signal and Bus Descriptions for FIG. 5
`
`Signal Name
`
`Input/
`Output Description
`
`Miu_stick_regrd_en
`Miu_stick_cmp_wr_cn
`Miu_stick_cmp_rd_en
`Miu_estar_mode_rd_en
`Miu_estar_mode_wr_en
`Pdp_mcu_pio_data[31:0]
`stick_alm
`estar_mode[1:0]
`
`Input
`Input
`Input
`Input
`Input
`Input
`Output
`Output
`
`STICK__REG tread enable
`STICK__COMPAREwrite cnable
`STICK__COMPAREread enable
`ESTAR_MODEwrile enable
`ESTAR_MODE tread enable
`Data bus input
`Stick alarm output to TRAP block
`ESTAR MODEregister
`
`Referring now to FIG. 6, a low-level block diagram of an
`exemplary embodimentof the present invention is shown to
`illustrate the functions of the signals listed in Table 4. The
`figure also showscircuitry of a STICKDPunit (62) and its
`interfaces with the PBM_SYNC (70) and the TRAP unit
`(84).
`The PBM_SYNC(70) comprises, as mentioned above, a
`divide by 12 frequency counter (72) and a frequency syn-
`chronizer (74). An int_PCI frequency signal serves as an
`inputfor the divide by 12 frequency counter (72). The divide
`by 12 frequency counter (72) divides the int PCI frequency
`signal by 12 and outputs a divided int__PCI frequency signal
`to the frequency synchronizer (74) which synchronizes the
`divided int_PCI frequency signal with the CPU clock
`frequency signal. The frequency synchronizer (74)
`then
`outputs a pbm__sync__div signal that has a frequency of the
`int_PCI frequency signal divided by 12 and synchronized to
`the CPU clock frequency signal.
`The int_PCI frequency signal, as mentioned above, is the
`internal PCI clock.
`In one embodiment of the present
`invention, the int_PCI frequency signal has a frequency of
`66.67 MHz whenthe external PCI clock has a frequency of
`33.3 MHz. For the UltraSparc-IIe, the external PCI clock
`remainsfixed at all times irrespective of power save modes.
`The power save modes implemented through a power man-
`agement scheme only change the CPU core frequency and
`leave the PCI clock unaltered for all power save modes
`supported by the scheme.
`For an embodimentof the present invention which imple-
`ments the UltraSparc-IIe microprocessor, the int_PCI fre-
`quency signal should not exceed 66 MHzif Estar mode Y%
`is to be supported.
`‘This is due to the limitation of the
`interface between the CPU core frequency and the PCI core
`frequency, which requires that fopy>=2 fexrernar_pcr
`Estar mode % is chosen for a processor running at 500 MHz
`in normal mode so that
`the value of % of the normal
`
`operating frequency, 83.3 MHz, still comports to the
`fopu>=2 lexrernat_pcr Tequirement.
`The CPU clock frequency signal referenced in FIG. 6 is
`the CPU core internal clock frequency, which typically has
`a value of 500 MHz or more.
`
`To help an operating system keep track of time for process
`aod event scheduling in a frequency changing environment,
`i.e., entering and exiting power save modes, embodiments of
`the present invention include a STICKDP unit (62) which
`comprises an Estar Moderegister (““ESTAR__MODE”) (78),
`a stick compare register (“STICKCOMPARE”) (80), a
`stick register (“STICKREG”) (82), and additional cir-
`cuitry uscd by the powcr management system. STICK__
`COMPARE(80) and STICK_REG (82) serve to provide
`periodic interrupts to the operating system regardless of
`whether the CPU clock frequency signal is changing. In
`
`15
`
`20
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`other words, STICK__COMPARE(80) and STICK_REG
`(82) are implemented to prevent
`interrupt periods from
`varying and causing indeterministic event scheduling as the
`CPU clock frequency signal changes when entering and
`exiting power save modes.
`STICK__REG (82) is a 64-bit register that serves as a
`counter for the operating system and provides a constant
`time reference for issuing interrupts and process requests.
`The most significant bit in STICK_REG (82) (STICK_
`REG[63)) is always‘1’ and this bit location is not written to
`or read from by the processor. The remaining 63 bits keep a
`current count for the operating system. STICK__REG (82)
`starts counting after a system reset.
`STICK__COMPARE(80)is a 64-bit register that can be
`written to and read from by the processor. STICK_
`COMPARE(84) holds the data value which is compared to
`the data value in STICK__REG(82)atthe rate of the internal
`PCI clock divided by 12.
`In other words, STICK_
`COMPARE(80) is provided to store the timeout value that
`gets compared with the incrementing STICK_REG (82).
`In an embodimentof the present invention, the registers,
`STICK COMPARE(80) and STICK REG (82), operate at
`5.5 MHz(internal PCI clock divided by 12). However, those
`skilled in the art will appreciate that other embodiments may
`use different frequency values depending on the PCI fre-
`quency.
`
`The discussed pbm__sync__div signal, upon being output-
`ted by the PBM_SYNC (70), is ORed (76) with a miu_
`stick_reg_wr_en signal. The miu_stick_reg__wr_en sig-
`nal is generated by a memory interface unit (“MIU”) (not
`shown). The MIU is where the address of STICK REG (82)
`is decoded for read/write access. The miu_stick_reg__wr_
`en signal serves as an enable signal for performing a write
`operation into STICK_REG (82). The output signal from
`the OR gate (76) serves as a clock enable signal for
`STICK_REG (82) which, in effect, determines whether or
`not STICK__REG(82) increments. The primary purpose of
`ORing (76) the pbm sync div signal and miu_stick_reg__
`wr__en signal is to ensure that STICK__REG (82) does not
`increment whena write process occurs to STICK__REG(82)
`by the processor. When the miu_stick_reg_wr_en signal
`is simultancously active with the pbm_sync_div signal, the
`output signal from the OR gate (76) serves to disable the
`clock enable input of STICK__REG(82),i.e., STICK_REG
`(82) is not allowed to increment. When the miu_stick_
`reg__wr_en signalis not active, the OR gate (76) outputs an
`active signal which enables the clock enable input
`to
`STICK_REG (82), ie., STICK__REG (82) is allowed to
`increment.
`
`ESTAR_MODE(78) (discussed above) is a register used
`by power management software to enable or disable a power
`save mode. Theregister is primarily used to enter the various
`power save modes (% and 4% modes) or to remain in the
`normal operating frequency mode (%4 modc). ESTAR_
`MODE(78)is 64 bits wide, but only the twoleast significant
`bits are used. The valuesof the twobits are sent toa PLL unit
`(discussed below with reference to FIG. 7). Those skilled in
`the art will appreciate that other embodiments may use a
`different number of power save modesordifferent values for
`the power save modes.
`A miu_estar_mode_wr_en signal serves as an input to
`ESTAR_MODE(78) andis used as a clock enable input for
`ESTAR_MODE(78). ESTAR_MODE(78) also inputs the
`CPU clock frequency since ESTAR_MODE(78)operates
`at the CPU frequency. The miu__estar_mode__wr_en signal
`comes from the MIU (not shown), which decodes the
`
`

`

`US 6,735,707 B1
`
`9
`address of ESTARMODE(78). In order to select a power
`save mode, the processor has to write two bits into ESTAR__
`MODE (78) via a pdp_mcu_pio[62:0] bus. The pdp_
`mceu__pio[ 62:0] bus is an internal bus used by the processor
`to write into ESTAR_MODE(78) and otherregisters. When
`the miu_estar_mode_wr_en signal is active,
`the clock
`enable input of ESTAR_MODE (78) is enabled and
`LSTAR_MODE(78) latches in the two bits from the pdp
`mcu__pio[62:0] bus at the rate of the CPU clock frequency.
`When the miu__estar_mode__wr_en signalis notactive, the
`clock enable input of ESTAR_MODE(78)is disabled and
`it retains the values of the bits residing in the register.
`The pdp__mcu_pio[62:0] bus is also used by the proces-
`sor to write data to STICK__REG (82). The data is multi-
`plexed (88) with an incremented value (89) and the multi-
`plexor (88) then outputs data to STICK_REG (82). For
`example, if the processor necds to write specific data valucs
`into STICK_REG(82), the processor sends the data via the
`pdp_mceu_pio[62:0] bus to the input of the multiplexor
`(88), which outputs the data to STICK__REG(82). STICK_
`REG (82) thereafter continues to increment based on the
`data it receives from the processor. When STICK__REG(82)
`increments based on data already residing in STICK_REG
`(82),
`the incrementer (89) increments the data value in
`STICK_REG (82) and then passes it to the input of the
`multiplexor (88), which in turn outputs the incremented data
`value to STICK_REG (82). STICK_REG (82) uses the
`CPU clock frequency whenit is latching in data from the
`processor.
`The pdp__mcu__pio[62:0] bus is also used by the proces-
`sor to write data to STICK_COMPARE(80). STICK_
`COMPARE(80) uses a miu_stick_cmp__wr_ensignal to
`serve as ils clock enable input. The miu_stick_cmp__wr_
`en signal is generated by the MIU (not shown). The MIU
`(not shown) decodes the address of STICKCOMPARE
`(80) and generates the miu_stick_cmp_wr_en signal.
`When the miu_stick_cmp_wr_en signal
`is active,
`it
`enables the clock enable input of STICK__COMPARE(80),
`and STICK_COMPARE(80) is allowed to read in data
`from the pdp_mcu__pio[62:0] bus at the rate of the CPU
`clock frequency.
`The values of STICKCOMPARE (80) and STICK_
`REG (82) are compared at the rate of the pbm__sync_div
`frequency signalsincethat is the rate at which STICK_REG
`(82) increments. The data values of STICK_COMPARE
`(80) and STICK__REG(82) serve as inputs to an exclusive
`OR gate