United States Patent
`Parikh et al.
`
`115
`
`JANNANATAC
`5,181,231
`Jan, 19, 1993
`
`(11)
`
`[45]
`
`Patent Number:
`
`Date of Patent:
`
`US005181231A
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`
`[22]
`
`[51]
`[52]
`[58]
`
`[56]
`
`NON-VOLATILE COUNTING METHOD AND
`APPARATUS
`
`Inventors: Harsh B. Parikh, Houston; Robert
`M.Crosby, Missouri City, both of
`Tex.
`
`Assignee: Texas Instruments, Incorporated,
`Dallas, Tex.
`
`Appl. No.: 620,499
`Filed:
`Nov. 30, 1990
`Int. CLS ooo ceececceccceeseceeeneeeeeneretones HO3K 21/40
`US. Ch. coceccctesestcsssssesetensensteaens 377/26; 377/24.1
`Field of Search 0.0... cece 377/24.1, 26
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,663,770
`4,757,522
`4,803,707
`
`5/1987 Murrayet al. on. cee 377/24.1
`7/1988 Kieselstein .....csecceessees, 377/241
`2/1989 Cordan, Jr.
`.csssseceseseee 377/24.1
`
`
`6/1989 Warner ow.
`4,839,909
`» 377/241
`
`8/1989 Carroll
`...csscsenes
`4,860,228
`. 377/241
`4,947,410 7/1990 Lippmannetal. ...........6 377/24.1
`
`Primary Examiner—John S. Heyman
`Assistant Examiner—Scott A. Ouellette
`Attorney, Agent, or Firm—Rose K. Castro; Robby T.
`Holland; Richard Donaldson
`
`ABSTRACT
`(57]
`A non-volatile counter memoryis provided by using a
`gray codescale to store counter valuesin a plurality of
`counter memories (34) comprising a counter memory
`group (38). Each counter memory comprises a plurality
`of units which store a gray coded value. The weighting
`of the units is changed after a predetermined number of
`write operations such that the numberof bit transitions
`is spread out among the units.
`
`27 Claims, 4 Drawing Sheets
`
`TI IG/eR
`TE
`TIPWM
`
`I|
`
`
`
`14
`
`
`
`INT2
`
`XTAL2/
`XTAL
`
`MC
`
`TIMER!
`_---- tee
`
`|L
`
`INTI
`
`ee
`
`INTS
`
`
`
`ev
`RAM/REGISTER]-
`SPISOMI
`SERIAL
`|
`FILE
`PERIPHERAL
`SPISIMO
`
`INTERFACE
`[}¢-®
`SPICLK
`pata eepromL~'®
`ROM (TMS370COtx)
`EEPROM (TMS37@C81x)
`
`
`30
`
`26
`
`y,
`Yee
`
`r—
`
`I— Veg
`
`oe a
`
`Google Exhibit 1032
`Google Exhibit 1032
`Google v. Valtrus
`Google v. Valtrus
`
`

`

`U.S. Patent
`
`Jan. 19, 1993
`
`Sheet 1 of 4
`
`5,181,231
`
`FIG.
`RESET
`MC
`XTALI MAL?/
`INT3.
`INT2.
`INTL
`.
`yyy J
`32
`1
`
`I
`t
`
`/
`
`|
`|
`
`RAM/RECISTER
`
`119
`SPISOMI
`SERIAL
`|
`SPISIMO
`PERIPHERAL
`SPICLK
`[}*-®
`INTERFACE
`!
`i|ROM (TMS370COtx)||DATA EEPROM
`|_|
`!
`EEPROM (TMS370CBIy)
`|
`18
`!
`
`7
`
`10
`
`T1KA
`THC /CR
`TIPWM
`
`
`
`
`
`|I2
`
`I
`
`8 PORT
`4
`At
`ee tf eeeeee f eee
`
`= Yc
`|
`ss
`
`P15
`
`1F14.s1F13.—sAF12.—=s«*AFA
`
`SAFI
`
`CNTRI
`
`1F25
` 1F24 —1F23.—1F22—F2t
`AF20
`amoft FIG. 3
`1F35 1F340s1F33)=1F32)—sTF3ss1F30
`
`
`CNIRS
`
`[counterMEwoRy1|MEMORY1
`
`
`
`[COUNTERMEMORY2|MEMORY 2 [counTeRMEWORY3]MEMORY 3
`
`FIC. 4
`
`

`

`U.S. Patent
`
`Jan. 19, 1993
`
`Sheet 2 of 4
`
`5,181,231
`
`memory=|8
`
`COUNTER
`MEMORY
`2
`
`COUNTER
`MEMORY
`GROUP 1
`
`memory|738
`
`3
`
`COUNTER
`MEMORY
`2
`
`COUNTER
`MEMORY
`2
`
`COUNTER
`
`MEMORY
`
`COUNTER
`MEMORY
`GROUP 2
`
`COUNTER
`MEMORY
`| GROUP 3
`
`\3p
`
`

`

`U.S. Patent
`
`Jan. 19, 1993
`
`Sheet 3 of 4
`
`5,181,231
`
`40
`
`“
`
`44
`
`FIG. 5
`
`NO
`
`
`INITIALIZE LOCATIONS] a
`
`IN EEPROM 10 BE
`USED
`
`
`WRITE 1, 2, AND S|ap
`AT LOCATIONS IF1@
`IF2@h AND [F3@h
`
`YES
`
`CHECK SEQUENCE
`OF 3 NUMBERS
`
`WAIT FOR SIGNAL
`TO_INCREMENT
`
`INCREMENT
`TO NEXT
`HIGHER NUMBER
`
`GO TO NEW
`GROUP OF
`REPROGRAM|yes
`EEPROM AND
`WRITE OLD
`GO TO START
`THE BAD
`COME FROM
`NUMBER
`RESET?
`VALUES IN NEW
`LOCATION -
`66
`
`74
`
`70
`
`
`
`
`64
`
`
`
`NEWLOC
`
`

`

`U.S. Patent
`
`Jan. 19, 1993
`
`Sheet 4 of 4
`
`5,181,231
`
`80
`
`BEGIN
`
`R2 FROM R3
`
`FIG. 6
`
`<Efree
`
`D
`
`Bh
`
`NO
`
`>
`
`B6
`
`-2?
`
`OR
`
`YES
`
`88
`92~[~SUBTRACT
`2 ERO RO
`SET FLAG Fife-{SET FLAG F4
`
`
`ES
`See"
`98
`102
`104
`
`HALTFOR|"[RI-SMALLEST [NO SET FLAG F2}e-SET FLAG F5
`
` 122
`
`
` YES
`
`
` NO
`R3-SMALL [NO
`R2—LARGE
`(SEQCOM3)
`|
`No
`REPROGRAM
`YES
`ri R1_WITH_R3+1 CEND)
`
`
`
`
`118-71 (END)YETR2 WITH Rit! 494 MID23 >
`
`REPROGRAM
`NO
`_[REPROGRAM
`R3 WITH R3+1 CEND)
`YES
`128
`130
`
`94
`
`72
`
`OR
`
`-23
`
`
`
`R1-LARGE
`(SEQCOM2)
`116
`
`110
`
`MID3I
`
`SET FLAG F6
`
`6
`
`MID
`
`154
`ROUTINE FOR
`IRRECOVERABLE ERROR}~60
`BERROR
`
`MIDxx ROUTINE
`
`
` TO APPROPRIATE
`
`

`

`1
`
`5,181,231
`
`NON-VOLATILE COUNTING METHOD AND
`APPARATUS
`
`NOTICE: (C) Copyright, Texas Instruments Incor-
`porated 1990. A portion of the disclosure of this patent
`documentcontains material which is subject to copy-
`right protection. The copyright owner has no objection
`to the facsimile reproduction by anyone of the patent
`document or the patent disclosure, as it appears in the
`Patent and Trademark Office patentfile or records, but
`otherwise reserves all copyrights whatsoever.
`TECHNICAL FIELD OF THE INVENTION
`
`to electronic cir-
`This invention relates in general
`cuits, and moreparticularly to a non-volatile counting
`method and apparatus.
`BACKGROUND OF THE INVENTION
`
`In manyapplications, it is desirable to store the out-
`put of a counter in a non-volatile memory, such that if
`poweris lost, the last count will be retained. For exam-
`ple,
`in an automobile odometer, the accrued mileage
`must be retained even during loss of power in order to
`reliably reflect the mileage of the automobile. Hence, in
`order to implementa digital electronic odometer, some
`type of non-volatile memory backup is necessary. Simi-
`larly, an electronic power meter would need some non-
`volatile memory backup, since loss of usage data would
`mean a loss in revenue.
`EEPROMs areoften used for non-volatile storage of
`data, because they may be electronically erased. In a
`counting application, however, it
`is desirable to store
`each incremented counter value in order to prevent the
`loss of any data. As a result, the least significant bits of
`an EEPROM memory undergo many morebit transi-
`tions than do the most significant bits. The least signifi-
`cant bit changes from a “one” to a “zero” or from a
`“zero” to a “one” on each count. The mostsignificant
`bit will undergo a transition from a zero to a one only
`once during the entire range of values output by the
`counter.
`
`Eachtransition between logic states creates stress on
`the associated bit. EEPROM memorycells are typically
`rated to withstand over 10,000 bit transitions. After
`10,000 transitions, an EEPROM memorycell is consid-
`ered unreliable. Consequently, if a counter sequences
`through 10,000 binary outputs, the least significant bit
`of a EEPROM memorystoring each output will be-
`comeunreliable for data storage. Therefore,if an appli-
`cation requires a sequence of numbers greater than
`10,000, the EEPROMwill ceaseto be a reliable storage
`medium. Furthermore,in practice, a cell may fail before
`the rated number of transitions; consequently,
`if an
`application, such as an odometer, requires a reliable
`storage mechanisms, the EEPROM rating cannot be
`relied upon.
`,
`One solution to the aforementioned problem is to
`shift to a new group of memorylocationsafter a prede-
`termined number of writes. For example, for a 24-bit
`counter, three memory locations would be needed. If
`locations 100; to 102/ (“‘h” denotes a hexadecimal num-
`ber representation) were used to store the output of the
`24-bit counter, after 10,000 transitions, locations 103to
`105h would be used to store the output. This solution,
`however, wastes memory since memory location 101/
`has had only moderate use and memory location 102/
`has had nouse.
`
`5
`
`- 0
`
`ra 5
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`60
`
`2
`Therefore, a need has arisen in the industry to pro-
`vide a method and apparatus for reliably storing the
`output of a counter in a non-volatile memoryand for
`detecting and correcting errors.
`SUMMARYOF THE INVENTION
`
`In accordance with the present invention, a method
`and apparatus for storing the output of a counter is
`provided which substantially eliminates the disadvan-
`tages with prior methods and apparatus.
`In the present invention, a sequence of numbers is
`stored in a non-volatile memory comprising a plurality
`of predefined units each operable to storea portion of a
`number. The order in which the portions of the number
`are stored in the memoryunits is varied, such that the
`bit
`transitions are spread out over a plurality of the
`units.
`technical
`invention provides several
`The present
`advantages over the prior art. Because of the order in
`which the portions of the number are stored in the
`memory units are varied, the numberofbit transitions
`may be averaged over a plurality of units. Conse-
`quently, the EEPROM memoryis efficiently used to
`maximize the number of counts which maybereliably
`stored.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`For a more complete understanding of the present
`invention, and the advantages thereof, reference is now
`made to the following descriptions taken in conjunction
`with the accompanying drawings, in which:
`FIG. 1 illustrates a block diagram of a counting cir-
`cult;
`FIG. 2 illustrates a block diagram of the counting
`groups used in a preferred embodiment of the present
`invention for a 24-bit counter;
`FIG.3 illustrates a block diagram of a single memory
`group;
`FIG. 4 illustrates a block diagram of the sequence of
`storage within a single counting group;
`FIG.5 illustrates a flow chart describing a sequence
`of operations to be used in the present invention; and
`FIG. 6 illustrates a flow chart detailing the flow of
`operations for checking the sequence of numbersstored
`by a counting group.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The preferred embodiment of the present invention
`and its advantages are best understood by referring to
`FIGS.1-6 of the drawings,like numerals being used for
`like and corresponding parts of the various drawings.
`FIG. 1 illustrates a preferred embodiment of a mi-
`crocontroller which may be used to implement
`the
`present invention. The microcontroller 10 includes a
`CPU 12, a RAM/Registerfile 14, a data EEPROM 16
`and a program memory 18, which may be a ROM ora
`EEPROM.A bus 20 couples the CPU 12, RAM/Regis-
`ter file 14, data EEPROM 16 and program memory 18.
`A serial peripheral interface 22 couples the bus 20 with
`external signals, shown as SPISOMI(Slave Out, Master
`In), SPISIMO (Slave In, Master Out) and SPICLK
`(Clock). A timer circuit 24 is coupled to the’ bus 20 and
`to external signal T1C1/CR (Counter Reset), TIEVT
`(External Event Input) and TIPWM (Pulse Width
`Modulation output). A watchdog timercircuit 26 is also
`coupled to the bus 20. Port A 28 and Port D 30 provide
`an 8-bit and 5-bit port to the bus 20 which maybe pro-
`
`

`

`3
`grammed as either a digital input or a digital output.
`Control circuitry 32 handles interrupts (INT1, INT2
`and INT3), external clocks
`signals
`(XTAL1 and
`XTAL2/CLKIN)and control signals MC (Made Con-
`trol) and RESET.
`The microcontrollerillustrated in FIG. 1 is based on
`the TMS370 family sold by Texas Instruments Incorpo-
`rated of Dallas, Tex. Various members of the TMS370
`family have different or additional features and capaci-
`ties. The CPU is a 8-bit processor with status register,
`program counter, and stack pointer internal to the CPU -
`module. The CPU 12 uses the RAM/Register file 14 as
`working registers, accessed on the bus 20. The bus 20
`also allows access to the memories 16 and 18 and the
`peripheral interfaces 22. The registerfile portion of the
`RAM/Register file 14 provides 256 registers to the
`CPU 12. The other RAM modules are mappedafter the
`register file. The data EEPROM 16 contains 256 bytes
`of electrically erasable programmable read-only mem-
`ory. The EEPROM can be programmed and erased
`under program control. The program memory 18 con-
`tains four kilobytes of memory, and may be a ROM or
`an EEPROM. Thetimercircuit 24 may be programmed
`to count events, compare the counter contents to a
`preset value, or time-out after a preset interval. The
`results of these operations can generate an interrupt to
`the CPU 12,setflag bits, reset the timer-counter, toggle
`an I/O line, or generate pulse-width-moduled (PWM)
`outputs. The watchdog timer circuit 26 can be pro-
`grammed to generate a hardwarereset upon time-out. If
`not needed as a watchdog, this timer can be used as a
`general purpose timer. The serial peripheral interface
`facilitates communication between the CPU and exter-
`nal peripheral devices.
`For purposes ofillustration, it will be assumed that
`the microcontroller 10 is coupled to an external sensor
`via INT1. The sensor generates an interrupt to the CPU
`12 on a predetermined interval. For example,
`in an
`odometerapplication, the sensor maygenerate an inter-
`rupt every tenth of a mile. Alternatively, in a power
`meter application, the sensor may generate an interrupt
`for every tenth of a kilowatt hour. Upon receiving the
`interrupt, the microcontroller reads a count value from
`the data EEPROM 16 and increments the count, as
`discussed in greater detail hereinbelow. Other methods
`for providing the count could also be used, for example,
`receiving the count from an external counter.
`FIG. 2 illustrates the organization of the EEPROM
`memory 16 into counter memories and counter memory
`groups. For purposes of illustration, FIG. 2 assumes
`that the portion of the EEPROM memory16 used for
`the counter memories starts at address, 1F10h (all ad-
`dresses being described in hexadecimal notation). Each
`counter memory 34 comprises six bytes 36. Hence,
`counter memory1 comprises the bytes at the locations
`4F10-1F15. For programming ease, the boundary for
`each counter memory begins on a hexadecimal bound-
`ary. Therefore, counter memory2 begins at address
`1F20, counter memory3 begins at address 1F30 and so
`on.
`
`Each counter group 38 comprises three counter
`memories. Hence, counter group1 comprises
`the
`counter memoriesstarting at locations 1F10, 1F20 and
`1F30, counter memory group2 comprises the counter
`memories beginning at 1F40, 1F50 and 1F60, and so on.
`Within each counter memory 34, each byte stores the
`value of a single hexadecimal digit. Thus, the six bytes
`
`— 0
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`60
`
`65
`
`5,181,231
`
`4
`store six hexadecimal digits, which corresponds to a
`24-bit counter.
`FIG. 3 illustrates. the bytes comprising a counter
`memory group 38, using counter memory group! of
`FIG. 2 as an example. FIG. 4 illustrates the order of
`writing into the counter memories 34 of a counter mem-
`ory group 38. Referring to FIGS. 1, 2, 3 and 4, the
`output of the sensor is successively stored in the three
`counter memories 34 of a counter memory group 38.
`Thus, for the sequence of numbers from “1” to “6”, “1”
`would be stored in counter memory], “2” would be
`stored in counter memory2, “3” would be stored in
`counter memory3, “4” would be stored in counter
`memory], “5” would be stored in counter memory2 and
`“6” would be stored in counter memory3. Conse-
`quently, from the viewpoint of a single counter mem-
`ory, the value stored therein increments by three on
`each write cycle to that memory. For example, counter
`memory 1 would store values one, four, seven, and so
`on, incrementing by three on each cycle through the
`three counter memories 34.
`TABLE1
`
`Gray Code Scale for Increment by 3
`Hexadecimal
`Binary
`Value
`Representation
`00000000
`11111000
`OO1111)11
`0000000!
`11110000
`01111111
`00000011
`11100000
`11212121711
`00000111
`11000000
`11121110
`00001111
`10000000
`11111100
`00011111
`
`
`
`NAMInHOOWroesUnEBWNHeod
`
`TABLE1 illustrates a gray code scale for an incre-
`ment by three to denote each hexadecimal value stored
`in the bytes 36. As can be seen from TABLE 1, each
`incrementby three results in a transition of only 1-bit. In
`the TMS370, for example, a single bit of the EEPROM
`memory 16 can be addressed for programming oreras-
`ing. In writing gray coded counter values to the EE-
`PROM memory 16, a transition of the stored contents
`of a byte from “1” to “4” changes the bit data from
`“41111000” to “11110000”. Hence,
`the fourth bit
`changesfrom oneto zero, and all other bits remain the
`same. Consequently, for each count only one bit need be
`changedin one byte of the counter memoryto account
`for the transition. If the transition of the counter value
`results in a transition of the next highest hexadecimal
`digit (for example, from “OQ0000D”to 000010”), then at
`most, two bits will change, each in a separate byte. The
`gray codes can be stored in the memoryas a look-up
`table.
`If gray coding were used as the sole means to reduce
`the bit stress of the EEPROM memorycells, the bytes
`storing the least significant hexadecimal digits would
`wear out significantly before the bytes storing the most
`significant hexadecimal digits. For example, after stor-
`ing a sequence of 10,000 numbers, counter memory1
`would undergo 3,334 transitions (since it stores one out
`of every three numbers) spread out over eight bits of
`each of three bytes. Thus, each bit of the least signifi-
`
`

`

`5,181,231
`
`5
`cant byte would have been stressed 416 times. The bits
`of the adjacent byte would be stressed only twenty-six
`times. The next byte would have bits which were
`stressed at most two times. Consequently, the byte hold-
`ing the least significant digit would wear out far before
`the moresignificantdigits.
`In the preferred embodiment, five of the six bytes
`defining the count are swapped after a predetermined
`number of write cycles. For example, the bytes may be
`swapped after every 10000h counts. By using 10000h as
`the swapping criteria, the swapping can occur every
`time the fifth most significant digit changes.
`TABLE 2
`
`
`6
`counter value, or if a bit failure occurs in one of the
`counter memories 34, one byte in the set of three
`counter memories may have been corrupted. An error
`detection routine notes an incongruence in the count
`sequence and makes a correction by determining the
`proper numberbased on the contents of the other two
`sets in the group. If a byte is corrupted during normal
`operation of the counter (i.e., without a powerfailure),
`the program movesto the next counter memory group.
`If, on the other hand, corrupted data is found after a
`system reset, the EEPROMlocation mightstill be use-
`ful and the correction value is restored into the cor-
`rupted byte, based on the values in the other two
`counter memories of the group.
`Digit Swapping Table
`FIG. 5 illustrates a flow chart depicting overall oper-
`Weight of Each Location Within
`Fixed Byte
`ation of the 24-bit counter. The counter operations can
`a Counter Memory
`Content
`be controlled by the CPU 12 in conjunction with the
`1Fx4h0IFx5h IFxX¢h IFx3h 1FX2h 1IFXih IF xOh
`
`program memory 18.
`0
`6
`5
`4
`3
`2
`i
`Start block 40 denotes the beginning of the counter
`1
`4
`5
`3
`2
`!
`6
`operation. In block 42, a memory location denoted as
`2
`3
`5
`2
`1
`6
`4
`3
`2
`5
`1
`6
`4
`3
`“FLAG”is read. For example, FLAG could have an
`4
`1
`5
`6
`4
`3
`2
`address of 1F1F of the EEPROM memory 16. FLAG is
`5
`6
`5
`4
`3
`2
`1
`set to a predetermined value, such as 55h after the EE-
`6
`4
`5
`3
`2
`1
`6
`PROMlocations used for the counter have been initial-
`7
`3
`5
`2
`1
`6
`4
`8
`2
`5
`1
`6
`4
`3
`ized. In decision block 44, it is determined whether or
`9
`1
`5
`6
`4
`3
`2
`not the FLAGequals the predetermined number.If not,
`A
`6
`5
`4
`3
`2
`1
`the EEPROM locations are initialized in block 46 by
`B
`4
`5
`3
`2
`I
`6
`setting all the bytes in each counter memoryto “zero”.
`Cc
`3
`5
`2
`I
`6
`4
`D
`2
`5
`1
`6
`4
`3
`In block 48,initial counter values of one, two and three
`E
`1
`5
`6
`4
`3
`2
`are written at locations 1F10, 1F20 and 1F30,thefirst
`
`6 5 4 3 2F 1
`
`
`
`
`
`bytes of the three counter memories of counter memory
`group 1.
`In block 50, the value §5h is written into
`FLAGto denotethat the initialization subprogram has
`been performed. In block 52, the value FF is written in
`a second FLAGlocation (for example, EEPROM loca-
`tion 1F17), denoted as the CFLAG. The CFLAG is
`used to determine which counter memory group is
`active.
`Afterinitialization blocks 46-52 or if FLAGisset to
`55h in block 44, operation continues at block 54. In
`block 54,
`three numbers are loaded from the three
`counter memories of the active counter memory group.
`In block 56, it is determined whether or not the three
`numbers comprise a valid sequence. In decision block
`58,if it is determined that at least two numbersare bad,
`operation switches to an error routine in block 60 for an
`irrecoverable error. In this instance, it cannot be deter-
`mined which,if any, of the counter memories contains
`the correct counter value.
`If less than two numbersare bad in decision block 58,
`operation continues to decision block 62 whereit is
`determined whether or not one of the three counter
`memories contains an incorrect value. If so, operation
`continues to decision block 64 whereit is determined
`whether or not the system has comefrom reset. If so,
`the bad numberis reprogrammedin block 66 and opera-
`tion loops back to block 54. If there is one number bad
`in decision block 62 and the system has not come from
`reset in block 64, then the counter memory groupis
`chosen(since it appears that one of the EEPROM mem-
`ories in the active counter memory group has failed)
`and the old values are written into the new locations of
`the new counter memorygroup (block 68). In block 70,
`operation is transferred to start block 40.
`If, in decision block 62, the sequence of three values
`is correct; operation continues to block 72 where the
`CPU waits for the counter signal to increment. Once
`the counter increments (block 74),
`the new counter
`
`TABLE2 illustrates a digit swapping table, where
`the number“1” indicates that the associated byte stores
`the least significant digit of the counter value and the
`number“6” indicates that it is the most significant digit.
`The fifth digit is always stored in the same memory
`location since it defines the weighting of the other
`bytes.
`For example, when the contents of the byte repre-
`senting the fifth digit (at address 1F24 for counter mem-
`ory 2 of counter group 1) contains a zero, then thefirst
`byte (1F20) contains thefirst (least significant) digit, the
`next byte (1F21) contains the seconddigit, the next byte
`(1F22) contains the third digit,
`the next byte (1F23)
`contains the fourth digit, the next byte (1F24) contains
`the fifth digit, and the next byte (1F25) contains the
`sixth digit. After 10000h counts, the fifth digit will tran-
`sition from a zero to a one. Atthis point, the values of
`the bytes will be swapped suchthatthefirst byte (1F20)
`stores the sixth (most significant) digit, the next byte
`(1F21) contains the first digit,
`the next byte (1F22)
`contains the seconddigit, the next byte (1F23) contains
`the third digit, the next byte (1F24) containsthe fifth
`digit, and the next byte (1F25) contains the fourth digit.
`Thefifth digit remainsin the samebyte,sincethis digit
`defines the weighting for all other bytes. The weighting
`will remain the same for another 10000h counts, at
`which time the weighting of the bytes will be swapped
`again as shown in TABLE2.
`Consequently, the gray code results in distributing bit
`transitions evenly overall the bits of a byte andthedigit
`swapping distributes the bit transitions over each byte
`of the counter memory(althoughthefifth byte doesnot
`experience as manybit transitions as the other bytes).
`The use of three counter memories 34 per counter
`memory group 38, as shown in FIG.4, guaranteesbet-
`ter data integrity. If the power is lost while writing a
`
`15
`
`20
`
`25
`
`30
`
`40
`
`45
`
`65
`
`

`

`5,181,231
`
`8
`a plurality of units comprising the counter memory,
`such that no one unit receives the bulk of the bit transi-
`tions.
`The present invention could be implemented using
`more or less counter memories per counter memory
`group. For example, a single counter memorycould be
`used, but this implementation would sacrifice the secu-
`rity of the two out of three voting scheme. If a single
`counter memoryis used, the gray code scale shownin
`TABLE 3 would be used.
`
`7
`value is stored into the appropriate counter memory
`after translation into the gray code. In decision block
`76, it is determine whetherthe fixed byte (fifth byte) has
`changed; if so, digit swapping is performed in block 78
`as discussed in connection with TABLE 2. Thereafter,
`operation continues from program block 54.
`FIG. 6 illustrates a flow chart of the operation for
`checking the sequence of three numbers. In this flow
`chart, it is assumed that the numbersretrieved from the
`counter memoriesare stored in registers R1, R2 and R3,
`respectively. Operation begins at block 80. In block 82,
`R2 is subtracted from R3. In decision block 84, it is
`determined whether R3 is greater than R2 by one. If
`not, in decision block 86, it is determined whether the
`difference is equal to two or minus two.If so, flags F4
`and F1are set in blocks 88 and 90. If not, flag F1 is set
`in block 90. After setting the appropriate flags, or if the
`difference is one in decision block 84, then operation
`continues at block 92 which subtracts R1 from R2.
`Decision block 94 determines whether R2 is greater
`than R1 bya difference ofone.If not, decision block 96
`determines whether the difference is two or minus two.
`If so, flags F5 and F2are set in blocks 98 and 100. If not,
`flag F2 is set in block 100. If the R2—R1=1 in decision
`block 94, then in decision block 102, it is determined
`whether F1is set. If F1 is not set, then it may be deter-
`mined that R1 contains the smallest number and R3
`contains the largest number and the numbers are in
`sequence (block 104). Operation then continues to block
`72 of FIG. 5. If, on the other hand, flag F1 is not set in
`decision block 102, or if program operation is flowing
`from block 100, then R1 is subtracted from R3 in block
`106. In decision block 108, it
`is determined whether
`R3—R1=1. If so,in decision block 110, it is determined
`whetherflag F1 is set. If not, it may be determined that
`R2 contains the smallest value, R1 contains the largest
`value, and the countis in sequence (block 112). Opera-
`tion again shifts to block 72 to wait for the signal to
`increment.If in decision block 110, flag F1 is set, then it
`is determined whether flag F2 is set in decision block
`114.If flag F2 is not set, it may be determined that R2
`contains the largest value and R3 contains the smallest
`value in block 116 and operation shifts to block 72 to
`wait for the signal to increment. If flag F2 is set, then
`there is one bad number, which is reprogrammed in
`block 118. If in decision block 108, R3—R1< >1, then
`it is determined whetherthe difference is two or minus
`two in decision block 120, If so, flag F6 is set in block
`122. Operation continues to decision block 124 whereit
`is determined whetheror notflag F1 is set. If not, R1 is
`reprogrammed with the value equal to R3+1 (block
`126). If flag F1 is set in block 124, then it is determined
`whetherflag F2 is set in decision block 128. If not, R3
`is reprogrammed with the value equal to R3 +1 in block
`130. If flag F2 is set
`in block 128,
`it
`is determined
`whetheranyofthe flags F4, F5 or F6 are set in decision
`block 132. If not, operation is transferred to block 60 of
`FIG. 5 where the routine for an irrecoverable error is
`executed. If one of theflagsis set, it can be determined
`that two of the numbers are in sequence and an appro-
`priate routine is executed to reprogram the third num-
`ber (block 134).
`From the foregoing, it can be seen that the preferred
`embodiment provides several technical advantages over
`the prior art. Counter values are stored in the non-
`volatile counter memories using a scheme which mini-
`mizesthebit transitions for each write operation to the
`counter memories and by spreading the increments over
`
`15
`
`30
`
`35
`
`45
`
`30
`
`55
`
`60
`
`65
`
`TABLE3
`
`HEXADECIMAL
`VALUE
`0
`1
`2
`3
`4
`5
`6
`7
`8
`9
`A
`B
`Cc
`D
`E
`F
`
`BINARY
`REPRESENTATION
`00000000
`0000000}
`00000011
`00000111
`00001111
`00011111
`00}11111
`Olr1i1tl
`}111i1111
`11111110
`1171111100
`11111000
`11110000
`11100000
`11000000
`10000000
`
`©
`
`While the present invention has been described in
`connection with a counter which stores a sequence of
`numbers which increment by one on eachinterrupt, it
`should be noted that the counter could also effectively
`store any sequence, either incrementing or decrement-
`ing, regardless of the incremental value. For example, a
`count which decrements by 4 on each count could be
`easily implemented.
`The counter described herein could be used in a vari-
`ety of applications, such as an odometer, utility meter,
`printer, or any other application where a reliable non-
`volatile counter is required.
`Although the present invention and its advantages
`have been described in detail, it should be understood
`that various changes, substitutions and alterations can
`be made herein without departing from the spirit and
`scope of the invention as defined by the appended
`claims.
`Whatis claimed is:
`1. A methodofstoring a count in a non-volatile mem-
`ory comprising the steps of:
`storing a number in a non-volatile memory section
`comprising a plurality of predefined memoryunits
`each operable to store a portion of said number;
`and
`varying the order in which said portions are stored in
`said memory units; and
`translating each of said portions prior to said storing
`step such that the numberofbits stressed by each
`storing step is minimized.
`2. The method of claim 1 wherein said translating
`step comprises accessing a translated value from a
`lookuptable.
`3. The method of claim 1 wherein each ofsaid units
`comprises eight bits operable to store a translated hexa-
`decimal digit.
`4. The method of claim 1 and further comprising the
`step of reading said memory section to detect possible
`storage errors.
`,
`
`

`

`9
`5. The method of claim 4 and further comprising the
`step of storing subsequent numbers to another memory
`section after detecting a storage error.
`6. The method of claim 1 wherein said step of varying
`the order comprises the steps of:
`storing a predetermined portion in a predetermined
`one of said units; and
`storing otherof said portions in other ofsaid units in
`a predetermined order corresponding to the value
`stored in said predetermined unit.
`7. The method of claim 1 wherein said translating
`step involves changing only one bit in one portion to
`accomplish the translation and minimize the number of
`bits stressed by each storing step.
`8. The methodof claim 1 wherein each memoryunit
`comprises n memories, and further wherein a value
`stored within each n memory increments by n on a
`write cycle to said n memory.
`9. A methodofstoring a count in a non-volatile mem-
`ory comprising the steps of:
`receiving a sequence of numbers;
`rotatably storing each number in a group of non-
`volatile memory sections each comprising a plural-
`ity of predefined memory units, each memory unit
`operable to store a portion of said number; and
`varying the order in which said portionsare stored in
`said memory units, such that the numberofbit
`transitions associated with said storing step are
`evenly distributed over a plurality of said units.
`10. The method of claim 9 and further comprising the
`step of translating each of said portions prior to said
`storing step such that the number ofbits stressed by
`each storing step is minimized.
`11. The method of claim 10 wherein said translating
`step comprises accessing a translated value from a look-
`up table.
`12. The method of claim 10 wherein each ofsaid units
`comprises eight bits operable to store a translated hexa-
`decimal digit.
`13. The method of claim 9 and further comprising the
`step of reading said memorysections to detect possible
`storage errors.
`14. The method of claim 13 and further comprising
`the step of storing subsequent numbers to another group
`of memory sections after detecting a storage error.
`15. The method of claim 9 wherein said step of vary-
`ing the order comprises the steps of:
`storing a predetermined portion in a predetermined
`one of said units of the memory section to which
`the numberis being stored; and
`storing otherof said portions in other of said units of
`such memory section responsive to the value
`stored in said predetermined unit.
`16. Non-volatile counter circuitry comprising:
`counting circuitry for generating a sequence of num-
`bers;
`a non-volatile memory comprising a plurality of
`memory sections comprised of a plurality of prede-
`fined memory units each operable to store a por-
`tion of a generated number from said counting
`circuitry; and
`control circuitry operableto;
`
`10
`
`20
`
`25
`
`30
`
`40
`
`45
`
`30
`
`35
`
`60
`
`65
`
`5,181,231
`
`10
`receive said generated sequence of numbers;
`store each numberin said non-volatile memory such
`that portions of said number are stored in associ-
`ated memory units;
`vary the order in which said portions are stored in
`said memory units; and
`translate each of said portions prior to said storing
`step such that the numberofbits stressed by each
`storing step is minimized.
`17. The circuitry of claim 16 wherein said non-
`volatile memory comprises an EEPROM memory.
`18. The circuitry of claim 16 wherein each of said
`memory units comprises n memories, each n memory
`comprising a byte containing multiple bits, and further
`wherein the valve stored within each said memory
`increments by n on each write cycle to said memory.
`19. The circuitry of claim 16 wherein said control
`circuitry is further operable to read said non-volatile
`memory to detect possible storage errors.
`20. The circuitry of claim 19 wherein said control
`circuitry is further operable to store subsequent num-
`bers to another memoryafter detecting a storage error.
`21. The circuitry of claim 16 wherein said translating
`step involves changing only one bit in one portion to
`accomplish the translation and minimize