United States Patent
`Davies, Jr. et al.
`
`119
`
`AQUATICAATA
`
`US005283792A
`[11] Patent Number:
`[45] Date of Patent:
`
`.
`5,283,792
`Feb, 1, 1994
`
`[54]
`
`[75]
`
`[73]
`
`[21]
`(22)
`
`POWER UP/POWER DOWN CONTROLLER
`AND POWERFAIL DETECTOR FOR
`PROCESSOR
`
`Inventors: William F. Davies, Jr., Carrollton;
`Ronald T. Taylor, Grapevine, both of
`Tex.
`
`Assignee: Benchmarg Microelectronics, Inc.,
`Carrollton, Tex.
`
`Appl. No.: 601,248
`Filed:
`Oct. 19, 1990
`Tt, CLS ..cscssecssescensecteessesseatscersers GO6F 11/00
`
`USS. Ch. wets
`371/66; 395/575 -
`Field of Search ............cccccssscsesceseees 371/66, 57.1;
`307/269 R; 364/273.4, 273.5, 268.5, 268.2,
`285.1; 395/575
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,096,560 6/1978 Footh 20.0...ee eseeeseeeneeee 395/575
`4,122,359 10/1978 Breikss ......csscssccsaseesseeees 307/66
`
`4,203,153
`5/1980 Boyd..........
`364/200
`1/1981 Minecket al.
`....ecsscccserseneees 363/41
`4,245,289
`4,327,410 4/1982 Patel et al.
`.
`.
`4,422,163 12/1983 Oldenkamp...
`4,453,307
`7/1984 McAnlis et al... 364/200
`4,645,943
`2/1987 Smith, Jr. et al.
`ee 307/150
`4,730,121
`3/1988 Lee et al. uccccesecsecesseeresees 307/66
`4,812,677
`3/1989 Perry .....cee
`.. 307/269 R
`4,816,862
`3/1989 Taniguchi et al... 354/412
`
`4,819,237 4/1989 Hamilton et al. ccs 371/66
`4,907,150 3/1990 Arroyoet al. 371/66 X
`
`
`
`
`
`4,959,774 9/1990 Davis ..ersccscccarsesersereresreres 371/66 X
`§,012,406 4/1991 Martin 00...eee 371/66 X
`
`Primary Examiner—Robert W.Beausoliel, Jr.
`Assistant Examiner—Ly V. Hua
`Attorney, Agent, or Firm—Ross, Howison, Clapp &
`Korn
`
`ABSTRACT
`[57]
`A powerfail control system for a CPU (10) and external
`memory (16) utilizes a controller (18). The controller
`(18) is operable to detect an early powerfail situation
`and output an interrupt to the CPU (10). The CPU (10)
`then goes into a power down sequence andstorescriti-
`cal instructions in an internal memory array (30) consti-
`tuting a hidden memory during the power down se-
`‘ quence. An. out oftolerance detector detects when the
`powersupply voltage has fallen below a predetermined
`threshold and then generates reset signal. The reset
`signal is input to the CPU (10) to indicate that no further
`instructions are executable. In addition, a Chip Enable
`_ Switch (46) is operated to inhibit memory control sig-
`nals from being transferred from the CPU (10) to the
`memory (16). The internal hidden memory(30) is also
`inhibited from having data written thereto in the pres-
`ence of the reset signal. A backup battery (22) is pro-
`vided which is connected to one side of a switch. The
`other side of the switch is connected to the power sup-
`ply voltage. When the power supply voltage falls below
`the battery voltage, the battery is connected to supply a
`current to the external memory (16).
`
`40 Claims, 9 Drawing Sheets
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`U.S. Patent
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`Feb. 1, 1994
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`U.S. Patent
`
`Feb. 1, 1994
`
`Sheet 2 of 9
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`5,283,792
`
`30
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`

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`U.S. Patent
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`Feb. 1, 1994
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`U.S. Patent
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`Feb. 1, 1994
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`U.S. Patent
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`

`1
`
`5,283,792
`
`POWER UP/POWER DOWN CONTROLLER AND
`POWERFAIL DETECTOR FOR PROCESSOR
`
`TECHNICAL FIELD OF THE INVENTION
`
`5
`
`2
`signal. A Write protect circuit Write protects the exter-
`nal memoryin response to the generation of the out of
`tolerance signal. A backup battery is provided with an
`associated backup circuit that is operable to connect the
`battery to the powersupply inputofat least the external
`memory when the powersupply is less than a predeter-
`mined backup voltage.
`In another aspect of the present invention a Chip
`Enable switch is provided for receiving on an input
`thereto memory control signals from the central pro-
`cessing unit that control the operation of the external
`memory. The Chip Enable switch is operable to route
`the memorycontrol signals to the memory in the ab-
`_ Data processing systems are conventionally config-
`sence of the out of tolerance signal and to inhibit the
`ured with some type of central.processing unit such as
`memory controlsignals from being input to the memory
`a microprocessor at the center thereof. During process-
`ing, instructions are executed and variouslevels of data
`in the presence of the out of tolerance signal.
`are stored in internal registers. Some of these instruc-
`In yet another aspect of the present invention, a hid-
`tions and the data associated with the processing opera-
`den memoryis provided for storing critical instructions
`_tion are. stored in memory, which can be volatile. or
`utilized by the central processing unit. Access circuitry
`non-volatile. It has beenrecognized that power supply
`allows the central processing unit to access the hidden
`failure in systemsofthis type results in loss of the vola-
`memory when the central processing unit is powering
`tile instructions which are being executed by the micro-
`downin response to the powerfail signal. The hidden
`processor and also loss of data in the volatile memory
`memory is Write protected such that writing of data
`storage devices. The.loss of data stored in external vola-
`thereto is inhibited when the out of tolerance signal is
`tile memory storage devices has been solved by provid-
`generated.
`ing battery backed-up systems that write protect the
`In a yet further aspect of the present invention, the
`memory and then attach a back-up battery or some
`equivalent supply thereto. In this manner, the informa-
`hidden memory has an address space that occupies a
`tion which is stored in the memory prior to the write
`predetermined portion of the address space of the exter-
`protect operation is maintained. However,this does not
`nal memory. During the power down sequence, the
`necessarily address the power down problem that exists
`address space of the hidden memoryis inserted into the
`with respect to the loss.of power to the microprocessor.
`address space of the externa] memory so as to replace
`_ The entire microprocessor system does not need the
`" power maintained thereto,since only a small number of 35 the corresponding portion of the address space. In this
`manner, the central processing unit accesses the hidden
`registers are involved with storage of the various in-
`memory by accessing its own address space.
`structions that are being executed, and since the amount
`of powerdrain associated with a microprocessor would
`BRIEF DESCRIPTION OF THE DRAWINGS
`be too great for a long-term battery back-up system.
`For a more complete understanding of the present
`’ Therefore, systems have been developed to download
`invention and the advantagesthereof, reference is now
`‘thevolatile memory information during a powerfailure.
`madeto the following description taken in conjunction
`In these prior systems, early powerfailure is detected
`and then sufficient time is provided to execute an or-
`_ with the accompanying Drawings in which:
`' dered shutdown routine, thereby leaving the system in
`FIG.1 illustrates a block diagram of the controller of
`45
`condition for recovery ofits interrupted operation on a
`the present invention interfaced with a CPU and a bank
`‘restart after the power has been restored to the system.
`of volatile memory;
`Onetype of system that providesa solution to this prob-
`FIG.2illustrates a block diagram of the controller;
`lem is disclosed in U.S. Pat. No. 4,458,307, issued Jul. 3,
`FIG,3 illustrates a diagrammatic view of the CPU
`1984 to J. C. McAnilis, et al. This system relates to a data
`address space in the hidden memory address space;
`processing system with a volatile main memory wherein
`FIG.4 illustrates a schematic diagram of the power
`_an early powerfailure is detected and the volatile infor-
`down controlcircuitry;
`mation downloaded to the main memory. If power
`FIG. 5 illustrates a block diagram of the powerfail
`’ deficiency persists, the main memory is backed up by a
`detect circuitry for both the RST signal and the NMI
`powersource only if the data saving operation has been
`signal;
`:
`completed.
`FIG. 6 illustrates a block diagram of the memory
`SUMMARYOF THE INVENTION
`array and control register of FIG.2;
`FIG.7 illustrates a detailed diagram of the memory:
`array;
`FIG.8 illustrates a schematic diagram of one of the
`static memory cells;
`FIG, 9 illustrates a logic diagram of the address latch
`state machine;
`FIG.10 illustrates a logic diagram for the Chip En-
`able decoder; and
`FIGS. 11 and 12 illustrate timing diagrams for the
`operation of the controller.
`
`The present invention disclosed and claimed herein
`comprises a method and apparatus for controlling the
`_ operation of the central processing unit and associated
`external memory during powerfailure of an associated
`powersupply. An early power fail detection circuit is
`provided for detecting a potential power supply failure
`in the power supply of the processor and generating a
`powerfail signal for output to the processor. An out of 65
`tolerance detection circuit is provided for detecting
`when the powersupply to the central processing unit is
`out of tolerance and generating an out of tolerance
`
`_The present invention pertains in general to power
`fail detect circuitry for microprocessors, and more par-
`ticularly, to a powerfail detect circuit that protects vital
`instructions in a microprocessorinstruction sequence in
`the event of a power failure and stores these instructions
`in a non-volatile memory for the power up operation.
`BACKGROUND OF THE INVENTION
`
`30
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`3
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`5,283,792
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`Referring now to FIG.1,there is illustrated a block
`diagram of a system utilizing the present invention. A
`Central Processing Unit (CPU) 10 is provided that is a
`conventional microprocessor. The CPU 10is driven by
`micro-instructions that are executed in a particular se-
`quence. The micro-irstructions and the sequence of —
`—_ 0
`execution is defined by the programmerof thesystem,
`whichis achieved in a conventional manner. The CPU
`10 has a data input DO-D7 thatis interfaced with a data
`bus 12.The CPU 10 also has an address output A0-A15
`that is interfaced with a sixteen-bit address bus 14..A
`Non-Maskable Interrupt input (NMI) is provided for
`receiving an external interrupt signal. A Reset Input
`(RST) is also provided for receiving a reset signal: A .
`Chip Enable (CE) output is provided for generating an
`external mémory control signal to allow the memory to
`be enabled. A Write Output (WR) and a Read Output
`(RD) are also provided for controlling the external
`memory.
`:
`An external memory 16 is provided which is com-
`prised of volatile memory. The memory 16 may be
`comprised of Static Random Access Memory (SRAM)
`or Dynamic Random Access Memory (DRAM). The
`memory 16 has a Data Input/Output D0-D7 interfaced
`with data bus 12 and also an Address Input A0-A15
`interfaced with the address bus.14. Memory 16 also
`receives a Chip Enable Input, a Write Enable Input and
`an Output Enable Signal. Whenever the Chip Enable
`Signal CEispresent and the Write Enable Signal WRis
`present, data is written into the Data Input/Output
`D0-D7in accordance with the address received on the ©
`Address Input AO-A15. Whenever the Chip Enable and
`Output Enable signals are present, data is accessed from
`the memory array within the memory 16 and output on
`the Data Input/Output DO-D7 to data bus 12. There-
`fore, the memory 16 is under the contro! of the CPU 10
`andis utilized to store data, instructions, etc. In general,
`any information requiredto be stored by. the CPU 10
`that cannotbe stored internal to the CPU 10 is stored in
`the memory 16. Most.conventional CPUs 10 haveinter-
`nal registers and storage areas for temporarily storing
`data, pointers, intermediate instructions, etc. However,
`only limited storage can be provided internal to the
`CPU 10. For mass storage, external memories, such as
`the memory 16, are provided. Further, non-volatile
`memory can also be provided and interfaced with the
`address bus 14 and the data bus 12.
`,
`A controller 18 is provided, which controller con-’
`tains an internal memory 20, which is illustrated in
`phantom. As will be described hereinbelow, this is a
`“hidden” memory and provides a storage location in
`whichto store certain sets of instructions utilized by the
`CPU 10 to resume operation after a powerfail situation
`has occurred and the CPU 10 is placed into a Power Up
`sequence. The controller 18 is generally operable to
`detect a powerfail situation prior to the power level
`decreasing below acceptable tolerances for the CPU 10
`and the memory 16. The CPU 10 has a specified operat-
`ing range, below which it will not reliably execute in-
`structions. In addition, the memory 16 also has an oper-
`ating voltage range over whichit will allow data to be
`written to the internal memory array, or allow data to
`be read from the internal memory array. However, the
`memory 16 also has a further minimum voltage, which
`is typically lower than that for reading and writing data
`
`4
`in the memory,that will allow data to be maintained in
`the memory. As will be described hereinbelow, this
`voltage level maintains the integrity of data in the mem-
`ory in a Write Protect situation. Such systems are de-
`- scribed as battery backed-up memory systems, one ex-
`ample of whichis illustrated in U.S. Pat. No. 4,645,943,
`issued to Smith, Jr., et al on Feb. 24, 1987.
`In operation, the controller 18 detects a power fail
`situation at an early stage via a user definable threshold
`input. Upon detection of the early power fail, a Non-
`Maskable Interrupt (NMI)signal is generated. A Reset
`(RST)is produced when the power supply decays to an
`out-of-tolerance condition, which is also user definable.
`The time period between generation of the Non-Maska-
`ble Interrupt and the Reset is utilized by CPU 10 to
`store critical
`information held in registers, counters,
`‘pointers, etc. into the memory 20. As will be described
`hereinbelow, this memory 20 resides transparent to the
`operating system memory map and is invoked at the
`user’s discretion by predetermined input codes pro-
`grammedinto the instruction sequence of the CPU 10.
`During an ensuing power-up sequence of the CPU
`10, the Reset output of controller 18 is held active for a
`sufficient time for the CPU 10 to stabilize, at which
`point the reset operation is terminated. The critical
`information stored in the memory 20 can then be re-
`trieved underthe control of the CPU 10 and processing
`begun at the point in the instruction sequence that ex-
`isted previous to the powerfail detection. Once infor-
`mation from the hidden memory 20 is recovered, the
`hidden memory 20 is exited and the normal power valid
`operation is resumed.
`The Non-Maskable Interrupt (NMJ) outputis utilized
`to warn the CPU 10 ofan impending powerfailure. An
`internal precision comparator monitors a Threshold
`Voltage Input (TV,) relative to an accurate voltage
`reference. Once the TV;pin falls below this reference
`voltage, the Non-Maskable Interrupt is forced active
`for a time period tam. The Threshold Voltage Input can
`be derived from the Vcc supply of approximately +5
`volts or from a higher D.C. voltage upstream of the
`supply. Since the comparator threshold voltage is user
`programmable perinternal control registers in the con-
`troller 18,
`the TV; input can be tied directly to the
`+Vee supply if no higher voltage supply is available or
`is not needed.If the higher voltage D.C.level is chosen
`for early powerfail detection, a simple resistor divider
`network can be utilized to set the voltage input to the
`desired threshold. An internalreference voltageis set to
`2.58 volts and, therefore, the value of the resistors in the
`resistor divider is derived by selecting the values of the
`resistors such that when the voltage TV;is at the de-
`sired detect threshold, the voltage input to the TV;
`input is approximately equal to 2.58 volts. Both an ac-
`tive high NMIoutput and an active low NMI output
`are made available to the user.
`The reset output (RST) is output whenever the sup-
`ply voltage Vec decays to an outof tolerance condition.
`A separate precision comparatoris provided that moni-
`tors the supply at the V.c pin relative to an internal reset
`voltage level Vies. During power down, the Reset out-
`put (RST) is forced active as the Voc supply decays
`below Ves, the RST output is held active as the supply
`continues to decay. Both an active high RST and an
`active low RST are made available to the user. The
`active high output will slew down with the supply.
`During powerup, the reset outputs will be held active
`for time tyes, after Vee rises above Vres. The level of Vres
`
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`5,283,792
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`24 is utilized to make the volatile memory 16 non-
`is user programmable at thresholds of 4.50 and 4.30
`volatile.
`volts.
`An NMIpowerfail detect circuit 28 is provided for
`An internal watchdog function is provided in the
`generating the NMIoutput. A threshold voltage Vina
`controller 18 to monitor processor execution during. a-
`which constitutes the 2.58 volt threshold, is input on
`power valid operation. The reset outputs will be forced
`one input to the powerfail detect circuit 28. The other
`active if the watchdog does not-receive a stimulus for
`input is the TV;input. As described above, the power
`time ty of a high-to-low transition at the Watchdog
`fail detect circuit 28 operates to warn the CPU 10 of an
`Strobe Input (WD). This transition must occur during
`impending powerfailure. It contains an internal preci-
`time t,y or the reset outputs will be forced active fortres.
`sion comparator that monitors the threshold voltage
`The watchdog timer can also-be reset under software
`TV;relative to the threshold voltage Vj;2.
`-
`control by executing a successful entry to the hidden
`The memory 20 is comprised of a hidden memory
`memory 20 followed by an exit from the hidden mem-
`array 30 which includes static random access memory
`ory 20. If thisentry andexit is completed before time .
`and a plurality of control registers 32 for storing control
`Trp, the timer will be reset and the outputs will not be
`bits to control the operation of the controller 18. The
`forced active. The time-out period T, is user program-
`‘memory array 30 is generally comprised of 2,040 bytes
`mable to 125 MS, 500 MS,2sec.orinfinity (ie., dis-.
`ofuser programmable non-volatile static RAM. This
`abled). The default condition maintains a disabled .
`memoryresides transparent, or hidden, from the normal
`watchdog monitor. The interrupt output from the
`operation system memory map. As will be described
`watchdog timer can be changedat user discretion to be
`hereinbelow, this memory is inserted into the address
`output on the NMIoutputinstead of the default condi-
`space of the CPU 10. This operation is invoked by the
`tion of the RST output.
`The volatile memory 16 is made non-volatile by uti-
`CPU 10issuing three consecutive Read cycles to a user
`definable address location in the system I/O map,
`lizing an external battery 22 thatis connected to the
`which address location is occupied by the address of the
`Veer input of controller 18. The controller 18 monitors
`hidden memoryarray 30. In a similar manner, data is
`the voltage level at the V.c input, whichis approxi-
`containedin thedata buffer 36 andis interfaced with the
`mately +5 volts. As this voltageinput decays during a
`data bus 12: As address inputs AO-A15 are held valid, a
`power failure, the conditioned Chip Enable Pin (CEcon)
`high-to-low transition on an address latch input AL will
`is forced inactive high independent of the memory ac-
`latch the 16-bit address location into a compare register
`cess Chip Enable Input (CE), which was received from -
`38 independent of the Chip Enable signal (CE). The
`the CPU 10.:This activity unconditionally Write pro-
`tects the volatile memory 16 as V¢c falls to Vres. Ifa
`compareregister 38 compares the received address with
`an internally generated value. If three consecutive
`- valid access is in process during power fail detection,
`matches are made, ensuing memory access cycles will
`that memory cycle will continue to completion before
`be directed to the hidden memoryarray 30 if the ad-
`the memoryis Write protected. If the memory-cycle is
`dresses correspond to the portion of the address space
`“not terminated, the CEco, output will unconditionally
`Write protect the memory within fourteen to forty-two
`of CPU 10 occupied by the hidden memory 30.In the
`preferred embodiment, the address space for the CPU
`microseconds. The voltage level defined as out-of-toler-
`10 is 65,536 bytes. The memory 30 can occupy either
`anceis the samelevelas set for the reset output Vyes. AS
`the lower 2,048 bytes of the memoryspace or the upper
`the supply continues to decay from Vyes, an internal -
`2,048 bytes of the memory space, as will be described
`switching device forces V out and CEcon to the voltage
`hereinbelow. The controlregister 32 is interfaced with
`of the external battery 22. The external battery 22 is
`a controller 42, which is interfaced with both a watch-
`* typically a three volt lithium cell. During power up,
`dog timer 44 and a Chip Enable Switch 46. The control-
`Vour and CE¢on are switched back to the plus supply
`ler 42 also is interfaced with the compare register 48.
`voltage level as Vee rises above the battery potential.
`The controller 42 is operable to control the internal
`The output CEco, is held inactive for approximately 50
`operation of the controller 18.
`_ms after the supply has reached V;es, this operation
`Once the hidden memory 30 has been accessed, the
`being independent of the CE inputto allow for proces-
`external memory mapfor the corresponding 2,048 byte
`sor stabilization. During normal operation with Vec at
`locations in the memory 16 will be disabled by an un-
`its normal voltage level, the CE inputis passed through
`conditional, inactive state of the CE¢o, output. Standard
`to the CEcon pin on controller 18 with a propagation
`SRAMaccess control will now be available in the hid-
`delay of 7 ns. If non-volatility is not required in the
`den memory30 utilizing the address inputs A0-A15 and
`memory 16, the Vour and CEcon outputs are disabled
`the 2,040 bytes from an address of 0000 to 07F7, for the
`through internal instructions.
`hidden memory 30 occupying the lower portion of the
`Referring now to FIG.2, there is illustrated a block
`address space. For simplicity purposes, all address to
`diagram for the controller 18. The Vac input is con-
`the hidden memory will be described assuming the
`nected to one-side of a two input switch 24, the other
`lower portion of the address space is occupied by hid-
`input of which is connected to the Vcc supply voltage
`den memory 30.
`input. The switch 24 provides the Vou; output, which is
`Any memory maplocation that falls outside the ad-
`connected to the memory16 for the purposes of provid-
`dress space occupied by the hidden memory 30 is auto-
`ing a back-up powersupply. A powerfail detect circuit
`matically routed to the memory 16. Once the hidden
`26 is provided for controlling the generation of the RST
`memory array 30 is invoked,it is the address received
`signal. The powerfail detect circuit 26 receives at one
`from the CPU 10 that determines whether the hidden
`input the voltage V,,, and at another inputthe threshold
`memoryarray 30 is accessed or the memory 16 is ac-
`voltage Vres. As described above, the threshold voltage
`cessed. This is all done transparent to the CPU 10,al-
`Vyesis user programmableat thresholds of 4.50 and 4.30
`though the CPU 10 mustinitially determine whether
`volts. The output of the power fail detect circuit 26 is
`the memory space of the hidden memory 30 is inserted
`also input to a power down control circuit 27 which
`into the memory space. As described above, the 2,048
`controls the switch 24. As described above, the switch
`
`35
`
`40
`
`45
`
`55
`
`60
`
`65
`
`

`

`-
`
`20
`
`25
`
`30
`
`©
`
`40
`
`45
`
`7
`byte hidden memory array 30 will also be available at
`the upper portion of the memory map from address
`F800 to FFFF. Theupper eight bytes of the 2,048 byte
`section comprise the storage area for the control regis-
`ters, and therefore, only 2,040 bytes are available for the.
`user programmable memory space.
`_
`When the hidden memory 30 is to be removed from
`the address space of the CPU 10,it is necessary to input
`three consecutive I/O Read cycles to the same address .
`that was utilized to invoke the hidden memory 30 into
`the address space of the CPU 10. A normal memory
`map operation will then be available for ensuing mem-
`ory accesses, provided the output CE from CPU 10 has
`returned to an inactive state. The invoke/exit I/O loca-
`tion is user definable and is stored in the control regis-
`ters 32. The default invoke/exit I/O locationis, in the
`preferred embodiment, 07FF.
`The hidden memory 30 is utilized to store critical
`’ settings during a power down cycle, or it can be used
`for any general memory map expansion, secure data
`field, or general data storage application.It is important
`to note that the integrity of the data stored in the hidden
`memory 30 is dependent upon the battery 22 being
`connected -to the Via; terminal. During a power down
`condition where the memory 16 is Write protected, the
`hidden memory 30 is also Write protected. Any valid
`memory access which occurs during a powerfail when
`Vecslews below Ves will continue to completion before
`the hidden memory 30 is Write protected.
`The control registers 32 reside at the eight uppermost
`address locationsin the 2,048 byte memory spaceof the
`hidden memory 30;
`that
`is, memory location O7F8
`through O7FF. Oncethe control registers 32 are config-
`ured, they will maintain valid settings in the event of
`powerloss, provided thereis a valid battery input to the
`Vor, input pin. If the upper 2,048 byte section memory
`is chosen for the address space of the hidden memory _
`30, the particular ones of the control registers 32 reside
`at locations FFFA through FFFF.These registers pro-
`vide control information for the controller 18 that can
`be input thereto by the CPU 10 and status information
`relating to the operation of the controller 18 for output
`to the CPU 10.
`The address locations O7F8 through 07FB contain
`access control information. All settings of registers at
`address locations 07FC through 07FF will be to a de-
`fault setting until the access control bytes are written to
`a specific pattern. Once a valid update pattern is writ-
`ten, new settings subsequently written into the upper
`‘four control registers will become. active as the hidden
`memory 30 is exited. Any other combinationofbits will
`cause the contents ofthe settings in the upper four bytes
`to be left unchanged, as the hidden memory 30 is exited,
`these being the current valid settings. The address loca-
`tions 07FC through O7FF can be read or written at any
`time, but will not be changed to other than current
`settings unless hidden memory 30 is exited with valid
`update settings at addresses O7FA through 07FB. Ad-
`dresses 07FA through 07FB will be cleared as the hid-
`den memory 30 is exited so that additional updates to
`control registers will require that valid update settings
`are rewritten. These access control bytes should be
`written last, prior to exiting the hidden memory 30, so
`that the other control bytes can be read and verified,
`and to avoid accidental update in case of a powerfail-
`ure.
`Addresses 07FC and 07FD contain the address loca-
`tion for the I/O invoke/exit of the hidden memory 30.
`
`5,283,792
`
`
`
`8
`The byte at address 07FD contains the most significant
`address location bits; that is, O7FD defines the 1/0
`address location for addresses A1s-Ag. Byte 07FC con-
`tains the address location for addresses A7-Ao. These
`two bytes can be read or written at any time while
`inside the hidden memory 30, but will not be updated
`unless the valid update pattern is present as hidden
`memory 30 is exited. Any new programmed I/O ad-
`dress location will become valid only after the hidden
`memory 30 has been exited. Thatis, the address location
`utilized to invoke the hidden memory 30 must also be
`utilized to exit.
`The address location 07FE controls the NMI thresh-
`old voltage value Vami, the out of tolerance voltage
`Vres, power fail sequencing, and the hidden memory
`location 30. The least significant bit, bit 0, is a user bit
`which can be read or written at any time while inside
`the cloaked memory. The status bit 3 determines the
`location of the 2,048 byte hidden memory 30 within the
`memory mapof the CPU 10.If this is set to a logical “1”
`(default), the hidden memory 30 will reside at addresses
`0000 through O7FF.Ifit is set to a logical “0”, the hid-
`den memory 30 address will be FA00 through FFFF.
`Bit three controls the automatic invoking of the hidden
`memory 30. If this bit is set to a logical “0”, hidden
`memory 30 will automatically be invoked on power
`down whenthe inputpin TV;falls below Vami. If this
`method of operation is chosen, and a valid access to
`memory is in process when powerfailure occurs, the
`hidden memory 30 will not be invoked until the user
`‘terminates the access to memory or the V,, supply
`reaches Vres. Subsequent memory cycles will be di-
`rected to hidden memory 30 only after memory access
`control signals, namely CE, have returned to an inac-
`tive state. The hidden memory 30 will also be invoked
`on subsequent power-up and mustbe exited for normal
`memory map allocation. The default condition of a
`logical “1”at bit three presents normal operation during
`power up/power down with the user invoking the hid-
`den memory30.
`Bit fouris utilized to contro! the sequencing of the
`RST and NMIoutputs. If bit four is set to the default
`condition of a logical “1”, these outputs behave as de-
`scribed previously.If this bit is set to a logical “0”, RST
`will not be forced active during power down,but rather
`will be forced active during time trs, as soon a8 Vec
`slews past Vyes. This sequencing allows for non-volatile
`processor applications. The NMIoutputs will be forced
`‘active during power downfor time tami, and then held
`inactive for subsequent power-up. When TV; slews
`above Vami, the NMI outputs will again be forced ac-
`tive for time tami. Therefore, either the RST outputs or
`the NMIoutputs will bring the processor out of the low
`power mode.If this method of sequencing is chosen,
`both NMI and RST will be held at a high level by the
`battery during powerfailure.
`Bit five of the byte at address O7FE is utilized to
`define the out of tolerance condition Vres. The default
`condition of a logical “1” in bit “five” defines Vres at
`4.30 volts. If a logical “O” is written into this bit, Vres
`will be 4.50 volts.
`Bits six and seven at the O7FE register provide the
`two most significant bits that are utilized to define the
`voltage value Vami When the Ty; input falls below
`Vami, the NMI output is forced active. The default
`setting value for Vami (2.