United States Patent 1
`Sotomeet al.
`
`US005761216A
`5,761,216
`[11] Patent Number:
`(45) Date of Patent:
`Jun. 2, 1998
`
`
`[56]
`
`S
`
`References Cited
`[54] BIT ERROR MEASUREMENT SYSTEM
`FOREIGNP
`DOC
`[75]
`Inventors: Tetsuo Sotome. Tatebayashi; Takayuki
`Japan .
`51-78679
`7/1976
`Nakajima. Minamikawara-mura;
`Japan .
`2-69687
`3/1990
`Kazutaka Osawa. Saitama; Kazuhiro
`Japan .
`2-201179
`8/1990
`Shimawaki; Kouichi Shiroyama. both
`Japan .
`4-95884
`3/1992
`Japan .
`del
`4/1992
`of Gyoda, all of Japan
`Primary Examiner—Vincent P. Canney
`[73] Assignee: Advantest Corp.. Tokyo, Japan
`Attorney, Agent, or Firm—Muramatsu & Associates
`[57]
`ABSTRACT
`[21] Appl. No.:
`732,303
`A bit error measurement system provides means for gener-
`[22] PCT Filed:
`Feb. 22, 1996
`ating test patterns, multiplexing means and meansfor speci-
`[86] PCT No.:
`PCT/JP96/00405
`fying and recording a pattern position. Inafirst aspect, a bit
`error measurement system has a pattern generator having M
`§ 371 Date:
`Feb. 10, 1997
`channels of pattern generation and a pattern generation
`controller 10 for controlling the pattern generation in the M
`§ 102(e) Date: Feb. 10, 1997
`,
`channels so that when one channelis selected to generate a
`[87] PCT Pub. No.: WO96/26451
`pattern the other channels are controlled to be waiting. In a
`second aspect, a clock frequency difference detector 150 is
`provided for counting a frequency of an input clock 111 and
`comparing the results with the frequency at the time of
`previous switching to detect whether the frequency change
`Foreign Application Priority Data
`[30]
`is greater than a predetermined value to judge whether the
`system is in a measurementstate and to permit or prohibit a
`Feb. 24,1995
`[JP]
`Japa .....cssesssersrsnnseceneerseonee 7-061712
`Feb. 24,1995
`[JP]
`Japan .... - 7063
`switching operation of a clock switch circuit. In a third
`aspect. a pattern position recording part 210 is provided to
`Apr. 4, 1995
`[JP]
`TaPat
`.caceasscssecenscenseeestcereasias F-102956
`
`[SL] Tante CUS ceeccccecscsccconsecssccessnsessensecseeessne GOG6F 11/00_store pattern position information of a reference pattern
`
`[52] US. CH. caceesssccsscessecssscencessesceeecensenserscereentenee 371/27.1|generator 262 when an error detection signal 265, is
`[58] Field of Search wicccccsenmnenunen 371/27.1, 27.7,
`*ceived from a comparator 265.
`371/28, 22.1, 5.4
`11 Claims, 15 Drawing Sheets
`
`PCT Pub. Date: Aug. 2, 1996
`
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`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 1 of 15
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`5,761,216
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`U.S. Patent
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`Jun. 2, 1998
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`Sheet 2 of 15
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`5,761,216
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`USS. Patent
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`Jun, 2, 1998
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`Sheet 3 of 15
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`5,761,216
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`FIG. 3
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`US. Patent
`
`Jun. 2, 1998
`
`Sheet 4 of 15
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`5,761,216
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`FIG. 5
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`U.S. Patent
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`Jun. 2, 1998
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`Sheet 5 of 15
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`U.S. Patent
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`Jun. 2, 1998
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`Sheet 6 of 15
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`5,761,216
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`US. Patent
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`Jun. 2, 1998
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`Sheet 7 of 15
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`5,761,216
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`U.S. Patent
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`Jun. 2, 1998
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`Sheet 8 of 15
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`5,761,216
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`US. Patent
`
`Jun. 2, 1998
`
`Sheet 9 of 15
`
`5,761,216
`
`FIG. 12 oy
`|BIT ERROR MEASUREMENT
`SIGNAL TO!
`MEASURE ©
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`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 10 of 15
`
`5,761,216
`
`ERROR
`
`ADDRESS
`
`FIG.14
`
`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 11 of 15
`
`5,761,216
`
`1
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`

`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 12 of 15
`
`5,761,216
`
`FIG. 16A
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`| PATTERN POSITION RECORDING =
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`FIG. /6B
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`

`

`USS. Patent
`
`Jun. 2, 1998
`
`Sheet 13 of 15
`
`5,761,216
`
`FIG. 17
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`

`U.S. Patent
`
`Jun. 2, 1998
`
`Sheet 14 of 15
`
`5,761,216
`
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`US. Patent
`
`Jun. 2, 1998
`
`Sheet 15 of 15
`
`5,761,216
`
`SIGNAL TO
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`2640
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`MEASURE
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`

`5,761,216
`
`1
`BIT ERROR MEASUREMENT SYSTEM
`
`TECHNICAL FIELD
`
`This invention relates to a bit error measurement system
`for testing a bit error rate, and moreparticularly,firstly, to a
`bit error measurement system which has a bit error test
`pattern generator and a bit error measurement apparatus for
`analyzing bit error rates of an output signal from a device
`under test by interchangeably switching between specific
`patterns and random patterns in real time. Secondly, this
`invention relates to a bit error test pattern generator which
`automatically switches clock edges of a multiplexing clock
`signal to be used for generating a high speed pattern by
`sequentially multiplexing parallel patterns generated by a
`pattern generator. Thirdly, this inventionrelates to a bit error
`measurement system which is able to specify and record
`positions of the pattern that involved in bit errors.
`
`BACKGROUND ART
`
`A first example of a conventional technology is show in
`the following.
`Namely, a bit error test pattern generator/bit error mea-
`surement apparatus in the conventional
`technology is
`described below in which a test pattern is generated by
`interchanging specific patterns and random pattern in real
`time to analyze bit errors in the output signal from a device
`under test.
`
`In a bit error measurement system, a test pattern of test
`speed up to several 10 GHz is applied to a device under test
`DUT.and performanceof the DUT is analyzed by measuring
`a bit error rate while changing the test conditions.
`In the conventional bit error measurement system,a test
`pattern to be given to the DUT is generated in either one of
`the two forms. One is a pseudo random binary sequence
`(PRBS)pattern generation and the other is a word pattern
`generation in which contents of a memory are repeatedly
`generated. This test pattern is supplied to the DUT, and the
`resultant outputs of the DUT is compared with expected
`pattern signals. The numberof bit errors is counted and an
`error rate is calculated and displayed.
`FIG. 5 shows an example of a test arrangementfor a bit
`error measurement system. A test pattern signal 71,,, and a
`clock signal 73 from a pattern generator 71 are provided to
`a DUT 74. The resultant output from the DUT 74 whichis
`a signal 61 to be measured and a clock signal 60 are provided
`to a bit error measurement apparatus 75 wherebya bit error
`is measured.
`
`FIG. 6 showsan internal structureof the pattern generator
`71. For generating a test pattern to be supplied to the DUT
`74, the pattern generator 71 includes a PRBS generator
`71,,,2; Which generates a PRBS (pseudo random binary
`sequence) pattern, and a WORD generator 71,,,,, which
`generates a word pattern based on the contents of a memory.
`Either oneofthe patternsis fixedly selected by a multiplexer
`(MUX) 71,, and is provided with a desired amplitude and
`offset voltage by a buffer amplifier 71,,,. Then the test
`pattern is applied to the DUT 74. The contents of the
`memory and other conditions for the pattern generation are
`set
`in advance through an external CPU (computer) to
`satisfy the desired test conditions.
`In receiving the test pattern signal, the DUT shown in
`FIG. 5 outputs pattern data. which for example, may be the
`same data received as input data. to the bit error measure-
`ment apparatus 75. The bit error measurement apparatus 75
`receives the output data from the DUT 74 and compares the
`
`10
`
`20
`
`25
`
`45
`
`50
`
`35
`
`65
`
`2
`data with expected pattern internally generated and counts
`the number of bits which do not match with one another,
`calculates a bit error rate, and displays the results.
`FIG. 7 shows an internal structure of the bit error mea-
`surement apparatus 75. The received signal 61 that is to be
`measured is compared, by a comparator 65, with a reference
`pattern from a reference pattern generator 62. The number of
`bits which do not match with one another are counted by an
`error counter 70.
`Since the position of the pattern sequence in the received
`signal 61 to be tested from the DUT 74 and the position of
`the bit sequence from the reference pattern generator 62 are
`undefined, the measurement apparatus includes a pattern
`synchronization part 66 for synchronizing pattern positions
`of both of the bit sequence. A synchronization detection
`counter 66, in the pattern synchronization part 66 is to detect
`whether the error rate is less than a predetermined value. For
`example, the synchronization detection counter 66, counts
`the number of mismatch bits 65,, for a fixed clock time
`period (for example, for a period of 16,384 clock pulses). A
`comparison test pulse 66,,, is given to a comparator 66,
`whereby the counted number of mismatch and a threshold
`value are compared. At the same time, the synchronization
`detection counter 66, is reset to an initial value to repeat the
`above detection procedure.
`If the results of the comparisonis greater than the thresh-
`old value from a threshold value register 66,. it is considered
`that the position of the both bit sequenceis still not aligned.
`Thus, a clock mask signal 67 is provided to the reference
`pattern generator 62 to suspend the pattern generation for
`one clock time so as to shift the bit sequence.
`This operation for the pattern synchronization detectionis
`repeated for every fixed clock period while shifting the bit
`sequence by one clock time until the pattern sequence
`coincide with each other. When the coincidence in the
`pattern sequence is detected, it is deemed that both of the
`patterns are synchronized and thus the operation for the
`synchronization detection is finished and an actual bit error
`measurementis undertaken.
`With respect to the internal structure of the reference
`pattern generator 62, the two generators. the PRBS generator
`62,,5; and the word generator 62,,,,, are identical to the
`generators in the test pattern generator 71 except for the
`clock mask function where the pattern is shifted by one
`clock time as noted above. The same type of the pattern
`generator now used in the pattern generator 71 is set in the
`reference pattern generator to generate the reference pattern
`62,2, which is supplied to the comparator 65.
`The above noted various data in the measurement system,
`the synchronization conditions, the measurement conditions
`and the like are set in advance through an external CPU to
`meet the desired test requirements.
`The second example of the conventional technology is
`described below.
`This examplerelates to a bit error measurement system of
`the conventional technology which produces a high speed
`test pattern by sequentially multiplexing parallel patterns
`generated by a pattern generator. In this bit error measure-
`ment system, edges of a clock signal for multiplexing the
`patterns are automatically switched.
`FIG. 11 shows a configuration of this wide band pulse
`pattern generator. The pulse pattern generator is mainly used
`to measure a bit error rate of a device under test (DUT) by
`providing the pulse pattern to the DUT.
`The pattern generator is formed of a pattern generation
`circuit 113, multiplexing circuits 114-114,an intermediate
`
`

`

`5.761.216
`
`3
`retiming circuit 127, % divider circuits 112,-112,, delay
`circuits 115 ,-115, and 115_. a clock switching circuit 128,
`and an approach detection circuit 131.
`An input clock 111 is an externally given clock signal
`having unknown clock rates. The frequency of the input
`clock 111 extends in a wide range. for example from 50 MHz
`to 10 GHz whichis freely set by a user in advance. However,
`the clock rate of the clock 111 must be constant when
`measuring the bit error of the DUT.
`Since it is necessary to correctly multiplex and retime the
`patterns for any clock rates of this wide range input clock
`111,
`the pattern generator includes the delay circuits
`115,-115,, for providing delay times (1), To4T1. To+T,+7...
`Tottytitty ts Tas Traettais Tyawtt,) to the clock signal
`equivalent to the delay times caused by propagation delays
`in the circuit components and wiring between the pattern
`generation circuit 113 and multiplexing circuits. In such a
`circuit arrangement,in the past, it is necessary for the delay
`circuits to have longer delay times in the later stages.
`Further. high quality clock with less jitters is required since
`the pattern generator operates in high speed. However, the
`circuit of FIG. 11 alleviates this requirements by having the
`intermediate retiming circuit 127, the clock switching circuit
`128, and the approach detection circuit 131 to cancel the
`delay times (T)+1,+..47,,_1) in the prior stages.
`The brief explanation is given in the following regarding
`the operations concerning the intermediate retiming circuit
`127,
`the clock switching circuit 128, and the approach
`detection circuit 131. The more detailed description is
`shownin Japanese patent application Ser. No. 218454-1990.
`The approach detection circuit 131 is formed of a coin-
`cidence circuit 132. an average circuit 133, a comparator
`134 and a T-type flip-flop 135.
`It is stated in the Japanese patent application Ser. No.
`218454-1990 that when a retiming clock for the intermediate
`retiming circuit 127 approaches too close to a transition
`point of the input pattern to the retiming circuit 127, a
`correct retiming will not be available. Thus, the Japanese
`patent application states, that when the retiming clock and
`the pattern transition point are too close with each other, that
`situation is detected by the approach detection circuit 131.
`Based on the detection signal, a phase of the clock, which is
`provided to the divider circuits to control the multiplexing
`operation.
`is switched. As a result,
`the delay times
`(To+T,+..+T,,-1) in the prior stages are canceled by the
`foregoing operation.
`the clock
`When adjusting the clock rate conditions.
`switching circuit 128 switches to a clock phase which is
`more stably retiming the patterns. During the measurement.
`the input clock rate must be constant, and thus the clock
`switching must not be taken place. This is because if the
`clock switching operation is taken place, it is not possible to
`test the bit error.
`
`technology is
`
`The third example of the conventional
`described in the following.
`This example relates to a bit error measurement system of
`conventional technology which specifies and records a posi-
`tion of a pattern where a bit error is produced.
`FIG. 17 shows an example of test arrangements in which
`a bit error measurement system is used. For testing a device
`274, a test pattern signal 272 and a clock signal 273 from a
`pattern generator 271 are provided to the device under test.
`274. The resultant output from the device under test 274
`which is a signal 261 to be measured and a clock signal 260
`are provided to a bit error measurement apparatus 275
`whereby a bit error is measured. In this situation,
`it
`is
`
`10
`
`20
`
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`
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`
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`
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`necessary to measure the bit error by setting the test pattern
`272 and a reference pattern generated by the bit error
`measurement apparatus 275 identical with one another.
`When the test speed is extremely high, 10 GHz for
`example. the device under test 274 may generate an abnor-
`mal serial pattern at the timing when the operation of the
`device under test is unstable. The bit error measurement
`system analyzes such pattern conditions that have caused the
`bit error.
`Here, a serial process of the bit error measurement is
`shown in the following.
`FIG. 18(a) is a block diagram of a conventional bit error
`measurement apparatus for explaining the process of bit
`error measurement. The bit error measurement apparatusis
`formed of a reference pattern generator 262. a comparator
`265, an error counter 270. a pattern synchronization part
`266. The pattern synchronization part 266 is provided for
`synchronizing patterns between the signal 261 to be mea-
`sured and the reference pattern generator 262. The pattern
`synchronization part 266 is formed of a synchronization
`detection counter 266,, a threshold value register 266, and
`a comparator 266...
`The pattern synchronization within in this context means
`that evenif bit errors exist to a certain extentin the unknown
`signal 261 to be measured, synchronization is deemed to be
`established. In other words,if the error rate is lower than a
`certain level such as shownin the threshold register 266,it
`is deemed to be synchronized. The synchronization detec-
`tion counter 266, is a counter which counts the number of
`bit errors for every predetermined time period. After the
`predetermined time period, the counted value and the data
`from the threshold register 266, are compared by the com-
`parator 266.. When the comparator 266, detects that the
`number of bit errors is less than the threshold value. a clock
`mask signal 267 is no longer generated therefrom.
`The reference pattern generator 262, when receiving the
`clock mask signal 267, delays the output phase of the
`reference pattern signal 262, by one bit to generate the next
`reference pattern. This process is continued consecutively
`until the reference pattern 262a matches with the input
`signal 261 to be measured. When the reference pattern 262,
`matches with the input signal, the clock mask signal 267
`from the comparator 266, is no longer generated. and thus,
`the reference pattern 262, is maintained in the synchronized
`situation. In this manner, a pattern synchronization is estab-
`lished between the signal 261 to be measured and the
`reference pattern generator 262.
`Thereafter, under this synchronization situation. the real
`bit error measurementis carried out.
`
`The comparator 265 compares the signal under test 261
`for every bit. and detects the resultant bit errors. The error
`counter 270 counts up the bit errors. The counted value is
`read by the CPU at every predetermined time period to
`calculate the error rate, and the number of errors will be
`output, for example, by means of a display.
`Here, a parallel process of the bit error measurementis
`shown in the following.
`FIG. 18() is a block diagram showing an example of a
`conventional bit error measurement apparatus for a parallel
`process. In this case, an ultra high speed signal 261 to be
`measured is converted to a low speed parallel signal before
`the measurement. The bit error measurement apparatus is
`formed of a demultiplexes (DEMUX) 264, a reference
`pattern generator 262, a divider 263, a comparator 265, an
`error counter 270 and a pattern synchronization part 266.
`As in the foregoing explanation, the pattern synchroniza-
`tion part 266 generates a clock mask signal when the
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`synchronization state is not reached. The divider 263. in
`receiving the clock mask signal, suspends a divided clock
`263, by one bit. The DEMUX 264 receivesthe divided clock
`263,. and will not fetch the input signal to be measured when
`the divided clock 263, is suspended. The reference pattern
`generator maintains the reference pattern 262, when the
`divided clock 263, is suspended. Therefore. a phase diifer-
`ence between a signal under test at the comparator 265
`which is an output signal 264, of the DEMUX and the
`reference pattern signal 262, shifts corresponding to the
`time (one bit) during which the divided clock 263,
`is
`suspended. The relationship between the DEMUX output
`264, and the reference pattern signal 262, in this situation is
`shown in FIG. 19.
`
`By repeating this process, the synchronization is estab-
`lished.
`
`the real bit error
`After reaching the synchronization,
`measurementis initiated. Since this example operates in a
`16-bit parallel manner, the error counter 270 is formed of 16
`counters each of which corresponds to one of the 16 bits.
`The CPU reads the numberof errors in the 16 counters and
`adds the results to display the same.
`Three problems exist in the conventional technology in
`the above to be solved by the present invention, which are
`as follows:
`
`First, as shownin the bit error measurement system which
`can specify the pattern position which caused thebit errors,
`the conventional bit error measurement system selects and
`generates either one of the word pattern generator or the
`PRBSpattern generator. Although the PRBS pattern gen-
`erator can generate a long period pattern, it is not able to
`generate a specified bit sequence. On the other hand,
`although the word pattern generator can generate a desired
`bit sequence, it is not able to generate a long period pattern
`since there is a limit in the capacity of the memory.
`As a consequence, it is not possible to fully test commu-
`nication devices by generating a mixed test pattern of along
`period and pseudo random pattern which is similar to
`transmission frames (such as STM, SDH, ATM)in an actual
`communication network. Thus, the conventional bit error
`Incasurement system is not appropriate for evaluating this
`type of communication devices.
`Second. as noted above, in the conventional bit exror
`measurement system which includes the bit exror pattern
`generator which is able to automatically switch clock edges
`of the clock signal to sequentially multiplex the parallel
`patterns to form the high speed test pattern, the approach
`detection circuit 131 is constantly in operation even when
`the system is in the bit error measurement process. This
`means that the approach detection circuit 131 detects such
`an approach between the retiming clock and the pattern
`transition point which is caused by minor changes in the
`clock rate of the input clock which is produced by tempera-
`tures changes and the like. In such a situation of the clock
`rate changes, in most cases, the multiplexing operation of
`the patterns is performed properly. Nevertheless, the clock
`phase is switched in such a situation in the conventional
`technology.
`This clock switch causes the bit stream of the outputtest
`pattern an instant indeterminate state. This indeterminate
`state in the pattern increases unstable parameters in the bit
`error measurement and may adversely affect
`the
`measurement, which is not proper to fully use the measure-
`ment system.
`Third, as noted above with respect to the bit error mea-
`surement system which specifies and records the position of
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`the test pattern which caused the bit errors, the error infor-
`mation acquired by the error counter 270 is not enough to
`fully analyze and specify the real cause of the error in the
`signal under test. To dothis, in the conventional technology.
`the contents of the test pattern, i.e., the contents in the
`pattern generator 271 and the reference pattern generator
`262 have been changed in various manners to see corre-
`sponding changes in the bit errors. such as increase or
`decrease. In this manner, the causes of the bit errors such as
`pattern conditions, pattern categories are identified,
`As has been foregoing. the error counter 270 is sufficient
`to find the bit errors but is not sufficient to fully analyze and
`specify the pattern conditions which caused the bit errors,
`which is inconvenientin the use of the bit error measurement
`system.
`Therefore, there are three objects of the present invention
`as follow. First, it is an object of the present invention to
`provide a bit error measurement system which is capable of
`multiplexing and generating specified bit sequence patterns
`and long period random patterns so that the bit error mea-
`surementis available based on this test patterns. Second,it
`is an object of the present invention to provide a bit error
`measurement system which is capable of allowing or inhib-
`iting the operation of the clock switch circuit 128 based on
`whether the measurement system is in the measurement
`process or not by monitoring the clock rate of the clock 111.
`Thus, it is able to provide a stable, wide band pulse pattern
`generator which can suppress the unstable operation based
`on the clock switching. Third. it is an object of the present
`invention to provide a bit error measurement system which
`facilitates the error analysis for the bit errors by recording
`the address information of the reference pattern generator
`262 so as to identify the position of the reference pattern in
`which the bit error is detected. Thus. the pattern position
`which produced the bit errors are easily identified and thus
`the error analysis for finding the cause of the error is
`performed more easily.
`DISCLOSURE OF THE INVENTION
`
`The solution of the above noted problems in accordance
`with the first invention is described below.
`This invention includes a bit error test pattern generator/
`bit error measurement apparatus which is able to switch
`between specific patterns and random patterns in real time
`and analyze the bit errors in the output signal from the
`device under test.
`
`FIG. 1 is a block diagram showing a first solution by the
`first invention.
`
`To solve the above noted problems. the first invention
`includes a pattern generator having M channels of pattern
`generation. The channels of pattern generation are sequen-
`tially switched in real time. A pattern generation controller
`10 is provided to control the pattern generator so that while
`one channel ofthe pattern generator is selected to output the
`test pattern, the operation of the other channelof the pattern
`generator is controlled.
`Asaresult, a test pattern generator to be usedin a bit error
`measurement is established which has M channels pattern
`generator where each of the channelsselectively outputs the
`test pattern.
`In case where the channel M is 2, the pattern generation
`controller 10, which selects the pattern generator in real
`time, includes a program counter (PGC) 12 which repeat-
`edly generates a frame period 12,..,. In receiving frame
`period data 12,,, from the PGC counter 12, a coincidence
`detector 14 generates detection signal which is provide to
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`two state means(such as an SR flip-flop) which generates a
`select signal 16,., for switching between time periods for
`multiplexing the two channels of the pattern generator. The
`pattern generation controller 10 also includes a period
`counter 18 which provides the number of frames during
`which the patterns will be repeatedly generated.
`FIG. 2 is a block diagram showing a second solution by
`the first invention.
`
`To solve the above noted problem.the configuration of the
`bit error measurementapparatus includes a pattern generator
`having M channels of pattern generation corresponding to a
`received pattern signal 61 to be tested which has the M
`selective patterns. The pattern generator generates a select
`signal corresponding to each of the patterns in the received
`signal 61 to be tested. Each of the M channels of the pattern
`generator is sequentially switched by this select signal and
`the selected pattern is provided to a comparator 65. When
`one channel of thetest pattern is output, the other channel of
`the test pattern is controlled by a pattern generation con-
`troller 10. A multiplexing means is provided which receives
`the select signal from the pattern generation controller 10
`and sequentially switches M channel output patterns from
`the pattern generator and provides the selected pattern to the
`comparator 65. The bit error measurement apparatus further
`includes an M channel pattern synchronization part which
`detects synchronization of patterns for each channel when
`receiving the select signal from the pattern generation con-
`troller 10. When detecting that the patterns compared are not
`in the synchronization state, the M channel pattern synchro-
`nization part sends a clock masksignal to the corresponding
`pattern generator.
`Therefore, the bit error measurement apparatus is estab-
`lished which generates M channel selective patterns and
`provides the selected patterns to the comparator to be
`compared with the signal to be measured and thus measures
`the bit errors in the received signal.
`The bit error measurement system is thus established
`which has the above noted bit error pattern generator and the
`bit error measurement apparatus in which the M channel
`selective patterns are selectively provided to the device to be
`tested by the bit exror pattern generator and the resultant
`output signal from the device under test is received and the
`bit error is measured by thebit error measurement apparatus.
`As a more specific example, the pattern generator of the
`present invention preferably includes at least one channel of
`word pattern generator or at least one channel of PRBS
`pattern generator. There are two pattern generation modes,
`one is a word generator 71,,.., which generates a word
`pattern by reading the contents in a memory and a PRBS
`generation mode 71,,,, which generates a pseudo random
`pattern.
`Thebit error measurement system whichis able to specify
`the position of the pattern which caused the bit error
`functions as follows:
`
`(1) When M=2,the pattern generation controller 10 in the
`bit error pattern generator 20 controls to alternately switch
`two pattern generators in real time. Both of the PRBS pattern
`generator and the word pattern generator generate the pat-
`tern while only one of them being selected to output the
`pattern. Alternatively, while one pattern generator is gener-
`ating the pattern, the other pattern generator’s operation is
`suspended.
`(2) Similarly, the pattern generation controller 10 in the
`bit error measurement apparatus controls to provide thetest
`patterns to the comparator 65.
`(3) The reference pattern generator 34 generates the
`patterns for the comparison which are the same as the
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`patterns generated by the test pattern generators in the bit
`error test pattern generator 20. By receiving each clock mask
`signal from the word pattern synchronization part 31 and the
`PRBS pattern synchronization part 32,
`test patterns are
`generated which are in synchronism with the received signal
`61 when the apparatus is in the synchronization state.
`(4) The word pattern synchronization part 31 receives the
`select signal 16,., from the pattern generation controller 10,
`and determines whether the patterns are in the synchroni-
`zation state in a period T,,, for generating a word pattern. If
`the error rate is greater than a predetermined value, the word
`pattern synchronization part provides a clock mask signal
`31,,,, to the word pattern generator 62,,,,4 SO as to bring the
`word pattern into the synchronization state.
`(5) Similarly, the PRBS pattern synchronization part 32
`receives the select signal 16,., from the pattern generation
`controller 10, and determines whether the patterns are in the
`synchronization state in a period T,.,.24¢ for generating a
`PRBSpattern. If the error rate is