US005825674A
`5,825,674
`[11] Patent Number:
`(15
`United States Patent
`Jackson
`[45] Date of Patent:
`Oct. 20, 1998
`
`
`[54] POWER CONTROL FOR MOBILE
`ELECTRONICS USING NO-OPERATION
`INSTRUCTIONS
`
`:
`ir
`Inventor: Robert T. Jackson, San Jose, Calif.
`[75]
`[73] Assignee:
`Intel Corporation, Santa Clara, Calif.
`
`[21] Appl. No.: 563,493
`
`[22]
`
`Filed:
`
`Nov. 28, 1995
`
`Related U.S. Application Data
`
`[63] Continuation-in-part of Scr. No. 537,146, Sep. 29, 1995.
`6
`[SL]
`Tint, CI ee ceeeeeneeen eee H02J 3/16
`[52] US. C1. cicccccceccseesssessses cesses 364/707; 395/200.18
`[58] Field of Search 0.0...ee 364/492, 707;
`395/750, 200.18, 882; 375/121
`.
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`5,254,992 10/1993 Keenet al. .
`5,369,771
`11/1994 Gettel ovceccccsssesesssssssnseesseonen 395/750
`
`5,392,437
`2/1995 Matteretal.
`. 395/750
`
`.....
`5,410,682
`4/1995 Sites et al.
`. 395/800
`5,546,568
`3/1996 Blandetal.
`. 395/550
`5,560,024
`9/1996 Harper et ab. woeeeeeeees 395/750
`Primary Examiner—James P. Trammell
`Assistant Examiner—Thomas Peeso
`Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor &
`Zafman
`
`[57]
`
`ABSTRACT
`.
`.
`.
`.
`.
`Asystem for regulating power in a mobile electronics device
`uses “hint” NOP instructions having a reservedfield of bits
`that generate control signals to affect an increase or decrease
`in powerdissipation. The control signals raise or lower the
`operating potential provided by a power supply and also
`adjustthe frequency of a clock signal in accordance with the
`information provided by the NOP instruction. Power is
`reduced for code sequences that could be executed more
`slowly, or the device is otherwise idle, without affecting the
`user’s perception of overall system performance.
`
`4,238,784 12/1980 Keenetal. .
`
`20 Claims, 5 Drawing Sheets
`
`100
`
`™
`
`PROCESSOR
`DIE
`‘PROGRAMMABLE
`REGULATOR
`
`
`
` CLOCK
`GENERATION
`CIRCUIT
`
`CONTROLLEA
`
`161
`
`THERMAL
`SYSTEM
`
`
`COMPARISON
`CONTROLLER
`LOGIC
`
`
`
`
`vo
`
`
`
`Google Exhibit 1040
`Google Exhibit 1040
`Google v. Valtrus
`Googlev. Valtrus
`
`

`

`U.S. Patent
`
`Oct. 20, 1998
`
`Sheet 1 of 5
`
`5,825,674
`
`POWER A
`
`0.9Fy
`
`Fy
`
`FREQUENCY(MHz)
`
`Ee”EG BL prion arr)
`
`POWER
`(W)
`
`VOLTAGE (V)
`
`FiA
`
`
`
`FREQUENCY (MHz)
`
`rioc
`
`

`

`U.S. Patent
`
`Oct. 20, 1998
`
`Sheet 2 of 5
`
`5,825,674
`
`
`
`
`
`LINDHIDAlddNSHAMOd
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`

`

`U.S. Patent
`
`Oct. 20, 1998
`
`Sheet 3 of 5
`
`5,825,674
`
`VO
`CONTROLLER
`
`CCV
`
`157
`
`156
`
`Feit <<
`
`
`

`

` HAS
`THERMAL
` LOW
`BAND BEEN
`EXCEEDED
`?
`
`NO-OP
`INDICATES
`7
`
`WALL POWER
`?
`
`
`IN
`
`IN
`DEMAND
`
`
`DE-TURBO
`"NLT" MODE
`
`MODE
`
`?
`?
`
`
`
` Is
`COMPUTATION
`
`USING ALL
`
`CPU RUN
`TIME?
`
`U.S. Patent
`
`Oct. 20, 1998
`
`Sheet 4 of 5
`
`5,825,674
`
`START
`
`
`
`
`
`
`RECEIVING ce
`
`
`
`
`
`
`
`RUN DEVICE
`RUN DEVICE
`AT "SLOWER"
`AT "FASTER"
`
`SPEED WITH
`SPEED WITH
`DECREASING
`INCREASING
`VOLTAGE
`VOLTAGE
`
`ik os
`
`

`

`17315
`
`420 MICROCODE
`
`VECTORS
`OR
`MICRO-OPS
`
`CONTROL
`SIGNALS
`
`il7
`
`U.S. Patent
`
`Oct. 20, 1998
`
`Sheet 5 of 5
`
`5,825,674
`
`a
`
`II
`
`! CHIPSET
`
`POWER
`SUPPLY
`
`CLOCKING
`
`

`

`5,825,674
`
`1
`POWER CONTROL FOR MOBILE
`ELECTRONICS USING NO-OPERATION
`INSTRUCTIONS
`
`RELATED APPLICATIONS
`
`This is a continuation-in-part application of Ser. No.
`08/537,146, filed Sep. 29, 1995, which is assigned to the
`assignee of the present application.
`
`FIELD OF THE INVENTION
`
`10
`
`The present invention relates to the field of electronic
`devices. More particularly, the present invention relates to
`methods and apparatus for controlling power consumption
`by an electronic device through voltage and frequency
`scaling.
`
`BACKGROUND OF THE INVENTION
`
`2
`mented with some non-CMOSelectronic devices which
`consume power but are frequency-independent (e.g., dis-
`plays for computer systems).
`This conventional frequencyreduction technique imposcs
`a numberof disadvantages. One paramount disadvantage is
`that the frequency reduction offers minimal conservation of
`battery life because the amount of energy required by the
`clectronic device undergoing frequency reduction to per-
`form a certain task can remain constant. In some situations,
`depending on the chosen configuration between frequency-
`dependent and frequency independent devices within a
`product like a laptop computer, frequency reduction may
`adversely effect battery life conservation. Thisis largely due
`to the fact that the electronic device, while operating at a
`slower frequency, requires extra operating time to complete
`the task. As a result, this cxtra operating time causes the
`frequency-independent devices within the product to con-
`sume more energy which, in some cases, will exceed any
`energy savings realized by reduced the operating frequency
`of the electronic device.
`
`Hence, it is desirous to create a power control circuit and
`develop a technique for reducing power consumption which
`can be utilized by any type of electronic device—especially
`mobile electronics devices—to more effectively control
`power consumption without substantially mitigating perfor-
`mance.
`
`Over the last few years, there have been many advances
`in semiconductor technology which have resulted in the
`development of improved electronic devices having inte-
`grated circuits operating at higher frequencies and support-
`ing additional and/or enhanced features. While these
`advances have enabled hardware manufacturers to design
`and build faster and more sophisticated hardware products
`(e.g., computers, peripheral devices, etc.), they have also
`imposed a disadvantage primarily experienced by battery-
`powered laptop or notebook style computers. In particular,
`these improved electronic devices consume more powerand
`dissipate more heat as a by-product than those past genera-
`tion electronic devices.
`
`Once hardwarecapability for controlling power consump-
`tion has been made available, another problem arises;
`namely, how to invoke such control in a simple, reliable
`manner. Although the use of thermal sensors for detecting
`excessive power consumption is well-known in the elec-
`tronics arts,
`these circuits lack intelligence and cannot
`respond to different software execution speed requirements.
`is well known that modern battery-powered laptop
`It
`That is, they are sensitive only to one physical parameter
`computers place a high premium on reducing power con-
`(e.g.,
`temperature) and are generally non-responsive to
`sumption to control component overheating and because
`changes in operating, system (OS) or applications program
`such reduction extends its battery life. Currently, one pri-
`(AP) software routines. For instance, whereas certain por-
`mary technique to reduce power consumption of laptop
`tions of code are optimally executed as fast as possible to
`computers is to lower the frequencyof the clocking signal
`maximize performance, other portions may be executed at a
`supplied to one of its electronic devices, namely its central
`much slower rate, thereby conserving power. Ideally, it is
`processing unit (“CPU”). This technique (referred to herein
`desirable to have the ability to dynamically control power
`as “frequency reduction’) usually is accomplished by
`consumption in a mobile electronic device—increasing or
`straightforward frequency reduction of the clocking signal
`decreasing power based on the demandsof currently execut-
`supplied to the CPU (ie.,
`the CPU clock) or,
`in the
`ing software—so as to extend battery life without compro-
`alternative, halting the clocking signal for brief time inter-
`mising system performance.
`vals so that the average operating frequency is reduced.
`Power management software programs that attempt to
`An alternative approach disclosed in U.S. Pat. No. 5,392,
`detect an “idle” central processing unit (CPU) currently
`437 involves clocking multiple functional units of an inte-
`exist. However, such programsare not always effective and
`grated circuit independently. When a particular functional
`lack the ability to discriminate between different types of
`unil is not in use,it is effectively powered downbydisabling
`software code. For example,
`there are certain software
`50
`the associated clock signal.
`routines or applications that maybe run atarelatively slow
`speed without adversely affecting the user’s perception of
`Referring to FIG. 1, a graph illustrating power savings
`performance. These typically go undetected by existing
`realized by a typical complementary metal-oxide semicon-
`power management software programs. Yet, it is precisely
`ductor (CMOS)electronic device based on the conventional
`these situations that afford the opportunity for significant
`frequency reduction technique is shown. It is well-known
`power savings. In a mobile environment, for example, such
`that electronic devices, in general, are designed to operate
`savings would greatly extend battery life, and hence, the
`within a specific frequency range. This frequency range 10
`usefulness of the electronics device.
`is represented as being between points A and B, where point
`A tepresents the minimum frequency required for the elec-
`tronic device to operate and point B represents the maximum
`frequency that the electronic device can support. In theory,
`power is directly proportional to frequency as presented
`herein. Thus, as shown through points C and D, a reduction
`in the operating frequency of the electronic device byten
`percent (10%) will reduce its total power consumption by
`ten percent (10%) from P1 to P2. Of course, true system
`power savings are not exactly proportional to frequency
`reduction because most every hardware product is imple-
`
`30
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`40
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`As will be seen, the present invention provides a simple,
`elegant way to control power in a mobile electronics envi-
`ronment. The invention allows operating system or applica-
`tion program software to increase or decrease power by
`including a special “no-operation” (NOP) instruction in the
`normal program flow. A reserved field of the NOPinstruc-
`tion provides “hint” information that is used to generate
`logic signals which either raise or lower power for subse-
`quent portions of code (ie., code following the NOP
`instruction).
`
`

`

`5,825,674
`
`3
`By way of further background, Applicant wishes to bring
`the reader’s attention to U.S. Pat. No. 5,410,682, which
`discloses a CPU that provides branch prediction hints. Also,
`application Ser. No. 08/530,614,filed Sep. 19, 1995, which
`is assigned to the assignee of the present application, dis-
`closes a method of modifying an instruction set architecture
`while maintaining backward compatibility.
`
`SUMMARYOF THE INVENTION
`
`The present invention overcomes the problems of the
`prior art by providing a system for regulating power in a
`mobile electronics device by the use of “hint” NOP instruc-
`tions. The hint HOPinstructionsare inserted into a software
`program, such as an operating system or applications
`program, which is executed on a microprocessor. The NOP
`instruction includes an opcode field and a reserved field of
`bits that, when executed, provide information to a logic
`circuit which generates control signals that affect an increase
`or decrease in powerfor the mobile electronic device. The
`control signals raise or lower the operating potential pro-
`vided by a power supply and also adjust the frequency of a
`clock signal in accordance with the information provided by
`the NOP instruction. In this way,
`the rate at which the
`processor (and the mobile electronic device) operates may
`be precisely controlled by software such that power is
`reduced for code sequences that can be executed more
`slowly without affecting the user’s perception of system
`performance.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The features and advantages of the present invention will
`become apparent from the following detailed description of
`the present invention in which:
`FIG. 1 is an illustrative diagram of theoretical power
`savings realized by a conventional frequency reduction
`technique.
`FIG.
`2a@ is an illustrative diagram of the theoretical
`“squared” relationship between voltage and power.
`FIG. 2b is an illustrative diagram of power savings
`realized by an electronic device whichis controlled through
`voltage and frequency scaling in accordance with the present
`invention.
`
`FIG. 3 is an illustrative block diagram of a power control
`circuit utilized in conjunction with the present invention .
`FIG. 4 is an illustrative block diagram of a plurality of
`registers employed within the I/O controller shown in IG.
`
`FIG. 5 illustrates the operations performed by the circuit
`of FIG.3.
`
`FIG. 6 is a block diagram of one embodiment of the
`system of the present invention.
`FIG. 7 illustrates the use of no-operation (NOP) instruc-
`tions to invoke powercontrol signals in accordance with the
`present invention.
`
`DETAILED DESCRIPTION
`
`The present invention describes a system and method for
`controlling power consumption of a mobile electronic
`device through both voltage and frequency scaling. The
`following descriptionis presented largely in terms of graphs,
`block diagrams and a flowchart whichcollectively illustrate
`the present invention in detail but does not discuss well-
`known circuits or process steps to avoid unnecessarily
`obscuring the present invention. The flowchart illustrates a
`
`10
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`4
`series of steps leading to a desired result. These steps require
`physical manipulations of physical quantities in the form of
`electrical or magnetic signals capable of being stored,
`transferred, combined, compared or otherwise manipulated.
`Referring to FIG. 2a, an illustrative graph of the relation-
`ship between voltage and poweris shown. As shownbythe
`equation below (whichis valid for manyelectronic devices,
`such as CMOSdevices) power has a “squared” law depen-
`dence with voltage which, in turn, has a generally propor-
`tional relationship with the operating frequency.
`
`Power=CxV?xFx(%Act)
`
`where
`
`C=total capacitance of the electronic device;
`V=total voltage supplied to the electronic device;
`F=operating frequency of the electronic device; and
`%Act=percenlage of gales of the electronic devices
`changing state in a given clock cycle.
`Note that the maximum operating frequency is approxi-
`mately proportional to V in the range V,2V=V>, where V,
`is the maximum operating voltage supported by the elec-
`tronic device.
`
`Thus, according to the above equation, a ten percent
`decrease (10%)in voltage results in about a nineteen percent
`(19%) decrease in power, since Cx(0.90 V)?xFxAct=(0.81)
`xPower.
`
`Referring now to FIG. 25, an illustrative graph of the
`powersaving realized by an electronic device by performing
`combined voltage and frequency scaling is shown. Similar
`to FIG. 1,
`the electronic device is operational within a
`voltage range 20 which is defined between point “A”
`(minimum operating voltage of the electronic device) and
`point “B” (maximum operating voltage). Furthermore,to be
`consistent with FIG. 1, points “C” and “D”represent the
`operational frequency of the electronic device at power
`levels P, and P, (P,=0.9P,), respectively. Thus,
`in the
`present invention, by decreasing the operational frequency
`and voltage ofthe electronic device (at point “C”) byslightly
`more than three percent (to point “D”), the power consumed
`by the electronic device is decreased by approximately ten
`percent, since
`
`Cx(0.966 V)?x(0.966 F)x(%Act)=(0.991)xPower
`
`While the realized power savingsis generally equivalent
`to that obtained through the conventional frequency reduc-
`tion technique, the operating frequency of the electronic
`device is diminished by only 3%, as opposed to 10%. It is
`contemplated that voltage and frequency scaling may occur
`in the voltage range 20, howeveronly frequency scaling may
`occurfor the electronic device along a low-voltage range 30
`up to point “A”. The reason for this is because voltage
`scaling in the low-voltage range 30 would cause the elec-
`tronic device to become inoperative.
`Referring to FIG. 3, one embodimentof a power control
`circuit employed within a computer system to control power
`consumption by an electronic device (e.g.,
`a
`microprocessor)
`is illustrated. Although the electronic
`device is shown as a microprocessor because ofits reputa-
`tion of being one of the main power consuming chips within
`a computer system, the power control circuit is capable of
`controlling power consumption by other types of electronic
`devices such as controllers.
`The computer system 100 comprises a central processing
`unit (“CPU”) 110, a system controller 120, a system bus 130,
`thermal comparison logic 140, an input/output (“1/0”) con-
`
`

`

`5,825,674
`
`5
`troller 150, a clock generation circuit 160 and a power
`supply circuit 170. After the computer system is powered-on
`and the user has selected a software application from main
`memory, mass storage memory device (e.g., IDE device) or
`an external disk drive to perform a certain task, the I/O
`controller 150 is configured by thermal managementsoft-
`ware stored within the CPU 110 to facilitate voltage and
`frequency scaling of the CPU 110 if at least one of two
`conditions occurs; namely, the temperature of the CPU 110
`exceeds a thermal band or the CPU 110 is experiencing
`excessive idle time. As will be discussed in more detail
`shortly, the present invention provides an additional mecha-
`nism of control, namely, direct software control.
`The “thermal band” is represented by an absolute hard-
`ware limit (requiring immediate device shut-off if exceeded)
`and programmable software upper and lower limits. These
`software limits represent thermal limits where, if exceeded,
`“throttling” (i.e., decreasingly scale voltage and frequency)
`or “dethrottling” is recommended.
`As shown, a temperature sensing component(e.g., ther-
`mistor and the like) 111 is coupled to a processor die 112 of
`the CPU 110 in order to monitor the temperature of the
`processor die 112 through thermaldissipation results, and to
`detect when the temperature has exceeded the thermal band.
`Thereafter, the temperature sensing component 111 trans-
`mits an analog or digital signal to the thermal comparison
`logic 140 via control line 113. The thermal comparison logic
`140 receives the signal. If the signal is analog, the thermal
`comparison logic converts it into a digital signal. The digital
`signal is input into the I/O controller 150 via a temperature
`control line 141. This digital signal, when asserted, indicates
`to the I/O controller 150 that the CPU 110 is operating at a
`temperature outside its thermal band. As a result, the I/O
`controller 150 needs to perform an operation to reduce the
`temperature of the processor die 112 within the CPU 110.
`To reduce the temperature of the processor die 112, the
`1/0 controller 150 programsa register 164 within the clock
`generation circuit 160 by propagating user-configured, pro-
`grammable information stored within the I/O controller 150
`into the register 164 via control line 151. The programmed
`information indicates how much (usually in a percentage
`value) the operating frequency of the clocking signal, sup-
`plied to at least the CPU 110 by the clock generation circuit
`160 via clock lines 161,
`is to be altered. In some CPU
`implementations as shown, the clocking signal utilized by
`the system bus 130 must bear a fixed relationship with the
`clocking signal input into the CPU 110 (i.e., CPU clock).
`As a result, the clocking signals of the system controller
`120 and the system bus 130 are reduced in proportion to the
`CPU clock. The clock generation circuit 160 monitors the
`valuc of the register 164 and appropriatcly modifics the
`frequency of the clocking signals transferred through clock
`lines 161-163. It should be understood that the clock gen-
`erator is designed such that the rate at which frequency is
`changedis sufficiently slow so that all of the phase-locked
`loops (PLLs) in the system remain locked.
`After determining that the operating frequency has been
`reduced though any well knowntechnique (e.g., signaling,
`preset delay time, etc.), the I/O controller 150 generates a
`voltage modification control signal
`to the power supply
`circuit 170 via control line 152. The power supply circuit
`170 includes a switching regulator 171 and a programmable
`regulator 172. Although not shown, the powersupply circuit
`170 includes a sensing circuit to indicate to the I/O controller
`150 whether poweris provided to the computer system 100
`from a wall socket or from a battery source. The program-
`mable regulator 172 receives the voltage modification con-
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`trol signal from the I/O controller 150 which indicates the
`amount of CPU core voltage, which is transferred to the
`processor die 112 by the programmable regulator 172
`through powerline 173, is reduced. The switching regulator
`171, however, is unaffected by the voltage modification
`control signal and continues to provide power(3.3 V, 5 V, 12
`V, ctc.) to power plancs of the computer system 100.
`Thus, in order to optimally diminish power consumption
`by the CPU 110 without a proportionate sacrifice of its
`speed, the CPU 110 first experiences frequency reduction
`and then voltage reduction. This order of scaling guarantees
`that the CPU 110 does not experience failure. Conversely,
`dethrottling the CPU 110 (ie., increasing its voltage and
`frequency) requires the CPU core voltage to be appropri-
`ately increased before the operating frequency is increased.
`The second condition, 1e.,
`the CPU is experiencing
`excessive “idle” time, typically occurs when the computer
`system 100 is running a software application that does not
`require optimal performance of the CPU 110 such as, for
`example, various legacy software applications, word pro-
`cessing programs, etc. Thus, power consumption can be
`optimally reduced by monitoring the amount of idle time
`experienced by the CPU 110.
`that power management
`It
`is well known in the art
`software such as Advanced Power Management (“APM”)
`software, which is stored within the main memory of the
`computer system and operates transparently to the user,
`monitors whether the CPU 110is idle or is performing useful
`computations. When the CPU 110 is idle, the power man-
`agement software in one implementation generates a HALT
`instruction and causes the CPU 110 to produce a halt
`acknowledgment cycle. The halt acknowledgment cycle is
`propagated through the system controller 120 onto the
`system bus 130. Upon detecting that the CPU 110 is pro-
`ducing the halt acknowledgment cycle, the I/O controller
`150 sets its halt cycle detect (“HCD”) storage element 155
`as shown in FIG. 4. Thereafter,
`the power management
`software periodically scans the HCD storage element. In the
`event that the HCD storage elementis set frequently(e.g.,
`5%-10% ofits run time) the computer system is throttled to
`perform voltage and frequency scaling. In such case, the I/O
`controller 150 performs the voltage and frequencyscaling
`operations in the same manner as discussed above with
`respect to the first condition.
`Referring now to FIG. 4, an embodiment of the I/O
`controller 150 is shown. ‘The I/O controller 150 includes the
`HCDstorage element 155, a clock speed (“CS”) storage
`element 156 and a CPU core voltage (“CCV”) storage
`element 157. The HCD storage element 155 is a single bit
`register indicating dynamically how frequently the CPU is in
`normal or idle state. More specifically, the HCD storage
`element 155 is set when the CPU is idle and is reset when
`
`the CPU is in its normal operating state. Thus, power
`management software requests the I/O controller 150 to
`perform voltage and frequency scaling when the HCD
`storage element 155 is frequently set and return the CPU to
`its maximum operating frequency and corresponding volt-
`age when the HCDstorage element 155 is frequently reset.
`The CS storage element 156 is configured as a “n”bit
`register (“n” being an arbitrary whole number) to incorpo-
`rate a frequency slewing constant which is used to throttle
`the frequency of the CPU. This is accomplished by trans-
`ferring the frequency slewing constant from the CS storage
`element 156 into the register 164 of the clock generation
`circuit. Similarly, the CCV storage element 157 is config-
`ured to incorporate a voltage slewing constant which is used
`to incrementally throttle the CPU core voltage provided by
`
`

`

`5,825,674
`
`7
`the power supplycircuit. The voltage stewing constant is
`transferred into the programmable regulator of the power
`supply circuit as shown in FIG. 3.
`Referring now to FIG. 5, an illustrative flowchart featur-
`ing the operational steps of the circuit shown in FIG. 3. In
`Step 200, the temperature of the electronic device is moni-
`tored to ascertain whetherit has exceeded the thermal band.
`If the predetermined thermal threshold has been exceeded,
`the electronic device undergoes both voltage and frequency
`scaling to reduce its power consumption (Step 225)orif the
`imposed low thermal bandis exceeded,the device is capable
`of operating at a higher voltage and frequency subject to
`software control by NOP instructions (Step 235). If the
`electronic device has not exceeded its thermal band, a
`determination is made as to whether the electronic device is
`receiving alternating current (“AC”) power from a conven-
`tional wall socket or is receiving direct current (“DC”)
`power through a battery power supply (Step 205). If the
`electronic device is receiving power from the conventional
`wall socket, no voltage and frequency scaling is performed
`on the electronic device as shown in Step 230, provided the
`condition according to Step 200 is not met.
`Alternatively, if the electronic device is receiving power
`fromthe battery power supply, a determinationis required as
`to whether at least one of three power saving modes to
`reduce power consumption by the electronic device is in
`effect. The first power mode to be checked is whether the
`hardware product is in “De-turbo mode” (Step 210). In
`De-turbo mode, the user selectively sets (in user setup) a
`desired operating frequency of the clectronic device to be
`less than the maximum operating frequency. This can be
`performed in laptop computers by depressing a switch
`located on the computer. If the hardware product employing
`the electronic device is in De-turbo mode, the voltage and
`frequency of the electronic device is appropriately scaled as
`configured (Step 225).
`However, if that hardware product is not configured to
`support the De-turbo mode, a second determination is made
`as to whether direct software control by NOPinstructions is
`in effect (Step 235). If software control is not in effect, a
`third determination id made as to whether the user has
`enabled a third power saving mode, referred to as a
`“Demand Non-Linear Throttling” (“DNLT”) mode (Step
`215). In this mode, if enabled by the user, software will
`transparently alter the voltage and frequency of the elec-
`tronic device based on amountofidle time experienced by
`the electronic device (Step 225), provided the conditions
`associated with Steps 200 and 210 do not
`indicate the
`contrary. If the DNLI mode is disabled, no voltage and
`frequency scaling is performed. Otherwise, when DNLT
`mode is enabled and the electronic device is frequently
`cxpericneing idle time thercby indicating that the device is
`not being utilized to its full capability, voltage and frequency
`scaling is performed on the electronic device until it is
`operatingat its maximum capability (Steps 220, 225). In the
`event that the DNLT mode is enabled and the electronic
`device is operating at its full capability, no voltage and
`frequency scaling is performed on the electronic device
`(Steps 220, 230). This process is continued to monitor the
`electronic device to optimize its performance and especially
`reduce its power consumption.
`FIG. 6 illustrates a block diagram of the power reduction
`system of the present invention. System 300 may be incor-
`porated into a variety of mobile electronic devices, but is
`particularly well-suited for use in portable computer
`systems—such as laptop or notebook computers—where
`conservation of battery power is an important design con-
`sideration.
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`A persistent problem in mobile electronic devices has
`been the inability of a device’s central processing unit
`(CPU) to differentiate between program instructions that
`should to be executed at full speed, and others that could be
`executed at a slower speed without adversely affecting
`overall system performance. For example, many operating
`system (OS) or application programs contain “idle” loops.
`An idle loop typically consists of code that the program
`cycles through while waiting for the occurrence of some
`external system event or interrupt. Such program loops
`present one of the worst cases for system powerdissipation.
`As discussed below, the present invention overcomes the
`shortcomings and achieves precise power regulation by the
`use of special NOP instructions.
`Referring to FIG. 6, an operating system or applications
`program is represented by ellipse 305 and arrow 306 for
`running on processor 310. System 300 also includes a power
`supply 330 and signal generator 320. Power supply 330
`provides a supply or operating potential for the electronic
`device via line 331, which, by way of example, is shown
`coupled to processor 310. This is a typical configuration in
`a portable computer system.
`System 300 also includes a signal generator 320 which
`provides clocking for both processor 310 and other system
`components such as a chipset 315. ‘he processor clock
`signal is shown in FIG. 6 being provided to processor 310
`along line 322, whereas the system clock is shown being
`provided to chipset 315 on line 321. Chipset 315 may
`include a variety of conventional system components such
`as memory 316, input/output (1/0) devices 317, bus con-
`troller 318, etc. System components within the chipset 315
`communicate information to and from processor 310 along
`bus 312.
`
`It will be appreciated by ordinary practitioners in the art
`that a great variety of different system configurations are
`possible for a mobile electronics device. Therefore FIG. 6
`should not be construed as limiting the invention to any
`particular embodiment or mobile electronic device configu-
`ration.
`
`The present invention improves powercontrol by the use
`of special NOP instructions. These instructions are true
`no-operation instructions; that is, execution of the instruc-
`tion does not change the architectural state (.e., register
`files) of the processor. Instead, the NOPinstruction includes
`a reserved field of bits that provide information to hardware
`control unit 319. Transfer of this information from processor
`310 to control hardware unit 319 is conceptually depicted by
`line 311 in FIG. 6 . Of course,this bit field information may
`be transferred in different ways such as over bus 312.
`Alternatively, the hardware control logic 319 may also be
`incorporated on the same integrated circuit as processor 310.
`In response to the bit pattern provided by the NOP
`instruction, the control logic 319 generates one or more
`control signals for adjusting the operating potential and
`frequency of the clocking signals provided by supply 330
`and signal generator 320, respectively. In FIG. 6,
`these
`control signals are shown being provided to power supply
`330 and clocking signal generator 320 along lines 335.
`Although FIG. 6 shows a single set of lines (e.g., a bus)
`commonly coupled from control unit 319 to units 330 and
`320,
`it is appreciated that separate, dedicated lines may
`alternatively be used. That is, a variely of connections and
`control signals are within the scope of the invention depend-
`ing uponthe level of control desired. Both the power supply
`330 and the clocking signal generator 320 are responsive to
`the control signals to either increase or decrease the oper-
`ating potential and clock frequencyprovided at their respec-
`tive outputs.
`
`

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`9
`To better appreciate the operation of the system of FIG. 6,
`consider the following example. Assumethat an operating
`system (i.e., DOS) is running on processor 310 and includes
`anidle loop. In accordance with the invention,a first special
`NOPinstruction may be inserted by the compiler at the point
`in the program prior to execution of the DOSidle loop. For
`cxample, the NOP instruction may comprise a previously
`invalid instruction in the processor’s instruction set archi-
`tecture (ISA). The decode logic of the processor, however,
`may be modified such that the previously invalid instruction
`is now recognized as valid although it has no effect on the
`machine from an architectural standpoint. Rather,
`the
`reserved bits of the instruction inform control
`logic to
`generate appropriate control signals for the power supply
`and clocking signal generator to effect an increase or
`decrease in power.
`the first special NOP
`Continuing with our example,
`instruction