19)
`United States Patent
`5,077,686
`[11] Patent Number:
`Rubinstein
`[45] Date of Patent:
`Dec. 31, 1991
`
`
`[54] CLOCK GENERATOR FOR A COMPUTER
`SYSTEM
`
`
`
`4,423,383 12/1983 Svendsen oo... ccesseccrseseerees 328/63
`4,523,274 6/1985 Fukunagaetal.
`.. 364/200
`4,556,984 12/1985 Genrich.....
`. 377/47
`4,695,804 9/1987 Bardi et al.
`328/62 X
`Jon Rubinstein, Palo Alto, Calif.
`[75]
`Inventor:
`4,773,031
`9/1988 Tobin ............
`we BTI/AT OM
`:
`4,893,271
`1/1990 Davis et al.
`caccecscesseneenen 364/900
`Stardent Computer, Newton, Mass.
`{73] Assignee:
`4,943,787
`7/1990 Swapp ....cecccsceereecennesenenes 331/2
`{21] Appl. No.: 472,749
`Primary Examiner—Michael R. Fleming
`[22] Filed:
`Jan, 31, 1990
`Assistant Examiner—Glenn A. Auve
`5
`Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor &
`Py Int. “ seerereseavenecreecssnsene mares rey2
`af;
`CD cere eteeeeeeneerenneaes
`;
`23
`364/934.71; 364/270.4; 364/DIG.1,364/DIG.
`2;,377/47
`~—«57)
`ABSTRACT
`[58] Field of Search ...........0.... 364/200, 900; 377/48,
`A clock frequency multiplication circuit. A circuit is
`377/47, 43; 328/60, 61, 62, 63
`described for receiving a clock signal of a first fre-
`References Cited
`quency X and multiplying the frequency of the signal
`by a multiple N to produce a signal of frequency N
`U.S. PATENT DOCUMENTS
`times X. The circuit is particularly useful in, for exam-
`ple, computer systems in which it is desired to upgrade
`certain components such as 4 processor to operate at an
`increased clock speed without modifying the clock
`speed of the system clock and whereit is further desired
`to provide synchronization between the system clock
`and the processor clock.
`
`[56]
`
`9/1976 Bredart et al. ........ceeee. 364/200
`3,980,993
`6/1978 Morimoto.....
`.
`4,095,267
`328/63
`7/1978 Aihara etal. .
`4,101,838
`
`.. 3647900
`4,231,104 10/1980 St. Clair ........
`
`4,249,070 2/198] Miller... .ssssesscsceecssetereteeers 235/92
`wee STT/4AT X
`4,331,924
`5/1982 Elliott et al.
`
`5/1983 Hoffman ........cceseeessenenreee 364/565
`4,383,303
`
`5/1983 O'Brien oo. secssessenerees 364/200
`4,386,401
`4,413,350 11/1983 Bond et al. 0.00.0... eee 377/47
`
`13 Claims, 5 Drawing Sheets
`
`PROGRAMMABLE INPUTS
`507
`
`
`
`
`
`4X
`DELAY LINE
`
`PHASE
`
`
`CLOCK
`
`
`FREQUENCY
`
`DELAY LINE
`SHIFTER
`
`GENERATOR
`MULTIPLIER
`
`
`
`
`502
`504
`503
`
`
`
`
`
`
`PHASE
`
`DETECTOR
`
`506 CLOCK
`
`
`GENERATOR 500
`
`
`
` 4 PHASE CLOCKS
`
`4X CLOCK OUTPUTS
`
`
`
`2X CLOCK
`PROCESSOR
`gle
`LINE
`
`
`Divie By 2|
`514
`OUTPUT 5); |
`
`
`Google Exhibit 1041
`Google Exhibit 1041
`Google v. Valtrus
`Googlev. Valtrus
`
`

`

`U.S. Patent
`
`Dec. 31, 1991
`
`Sheet 1 of 5
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`

`

`U.S. Patent
`
`Dec. 31, 1991
`
`Sheet 2 of 5
`
`5,077,686
`
`rT
`
`BACKPLANE 202
`
`LINE 203
`
`1
`
`DIVIDE
`DIVIDE
`BY 2
`BY 2
`212
`213 214
`
`
`
`
`
`
`
`
`
`INTEGER
`INTEGER
`INTEGER
`INTEGER
`UNIT
`UNIT
`UNIT
`UNIT
`
`
`
`
`
`132
`
`(33
`134
`131
`
`Fi2
`
`3l2
`
`1X CLOCK LINE
`30!
`
`CLOCK
`GENERATOR
`310
`
`2x CLOCK
`LINE
`
`4X CLOCK
`
`322
`
`PROCESSOR
`Slt
`
`OTHER
`CIRCUITRY
`
`

`

`U.S. Patent
`
`Dec. 31, 1991
`
`Sheet 3 of 5
`
`5,077,686
`
`E"its
`
`
`
`<I cprior art)
`
`PROGRAMMABLE INPUTS
`407
`
`
`2x CLOCK
`pee|
`LINE
`
`
`DELAY LINE
`PROG.
`40!
`
`DELAY LINE
`GENERATOR
`
`
`
`402
`40
`
`
`
` 4 PHASE CLOCKS
`2x CLOCK PUTPUTS
`
`PHASE
`DETECTOR
`406
`
`
`CLOCK
`GENERATOR 400
`
`
`1X CLOCK
`LINE
`4l4
`
`Pile
`
`
`
`=m
`
`PROGRAMMABLE INPUTS
`507
`
`
`
`
`
`1X CLOCK
`
`
`LINE
`4x
`
`
`
`DELAY LINE
`PROG.
`
`
`50!
`PHASE
`CL OcK
`FREQUENCY
`
`
`
`
`SHIFTER
`DELAY LINE
`MULTIPLIER
`GENERATOR
`
`
`502
`
`503
`505
`
`
`
`PHASE
`DETECTOR
`
`
`—
`506
` CLOCK
`
`
`
`GENERATOR 500
`
`4 PHASE CLOCKS
`
`4x cLocK OUTPUTS
`
`
`
`2X CLOCK
`PROCESSOR
`
`LINE
`Sle
`
`Sia
`
`
`DIVIDE BY 2
`OUTPUT «)3 |
`
`
`

`

`U.S. Patent
`
`Dec. 31, 1991
`
`Sheet 4 of 5
`
`5,077,686
`
`gi
`
`£3
`
`x4
`
`26
`
`27
`
`28
`
`z9
`
`1X CLOCK
`60!
`
`2X CLOCK
`
`1X CLOCK
`60l
`
`2x CLOCK
`
`602
`
`45=X6£44 x7 48 29
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`
`
`

`

`U.S. Patent
`
`Dec, 31, 1991
`
`Sheet 5 of 5
`
`5,077,686
`
`- TG #
`
`4X CLOCK
`800
`
`CLOCK O1
`80l
`
`CLOCK O02
`802
`
`CLOCK O03
`
`803
`
`804JooUtLIL
`805
`
`CLOCK 04
`
`CLOCK OUT
`
`UNSPECIFIED
`DELAY
`806
`
`| | || |
`
`x0
`
`

`

`1
`
`CLOCK GENERATOR FOR A COMPUTER
`SYSTEM
`
`5,077,686
`
`25
`
`30
`
`35
`
`BACKGROUNDOF THE INVENTION
`1. Field of the Invention
`The present invention relates to the field of clocking
`apparatus for computer systems; more specifically, the
`present invention relates to circuitry for generation of
`clock signals in a multi-processor computer system.
`2. Description of the Related Art
`Modern day computer systems operate under the
`control of one or more “clocks” or signal lines carrying
`a signal of a predetermined frequency and duty cycle.
`Theclock signal is provided to various componentsin
`the computer system and these components typically
`carry out some operation or set of operations during
`one or more “clock cycles” or cycles of the signal. A
`crystal or other device is used to generate the clock
`signal, such crystals being capable of generating clock
`signals at predetermined frequencies such as 8 Mhz, 16
`Mhz, 32 Mhz and 64 Mhz.
`Of course, the various components of the computer
`system must be designed to match the clock speed or
`frequency. More properly put, the computer system
`must be designed to provide a clock signal of the appro-
`priate clock speed to circuits used in the computer sys-
`tem. The circuits are typically purchased or otherwise
`acquired by the computer system designer having a
`specified clock speed. It follows that should one of the
`components be changed or upgraded with a component
`having a different required clock input frequency that
`the computer system must be redesigned to provide for
`an additional clock input.
`This creates a special problem in multiple processor
`computer systems where it
`is desired to operate all
`components underthe control of a single clock and, for
`example, only one of the processor modules is upgraded
`with a higher speed processor. Alternatively, all proces-
`sors may be upgraded but other components in the
`system maystill require a lower speed clock. One solu-
`tion to this problem may be to provide a higher speed
`systems clock (e.g., upgrade the system clock from
`being a 32 Mhz clock to being a 64 Mhz clock) in order
`to the satisfy the needs of the processors and then to
`provide clock division circuitry to divide the clock
`speed to the frequency required by the other compo-
`nents.
`However, in the computer system of the present in-
`vention the system clock is provided on a backplane
`with which numerouscircuit boards, such as processor
`boards, are coupled. Replacement of the backplane, or
`the clock circuitry on the backplane,
`to provide a
`higher speed clock is expensive and, further, would
`require field service of each installed system to accom-
`plish the desired replacement.
`Therefore, what is desired is to develop clock genera-
`tion circuitry which provides increased clock speed
`without the requirementof replacing the system clock.
`It should be noted that the preferred embodiment of 60
`the present invention is designed for implementation on
`a computer system available from Stardent Computer,
`Inc. of Newton, Mass. FIG. 4, which will be explained
`in greater detail below,illustrates certain clock genera-
`tion circuitry of a prior art computer system available
`from Stardent Computer, Inc. under the tradename
`TITAN.Theprior art TITAN computerutilizes a mi-
`croprocessor manufactured by MIPS Computer Sys-
`
`45
`
`50
`
`55
`
`2
`tems, Inc. of Sunnyvale, Calif. under the tradename
`R2000. The R2000 microprocessor requires a 32 Mhz
`clock signal. In the preferred embodimentof the present
`invention, processor boards may utilize a microproces-
`sor available from MIPS Computer SystemsInc. under
`the tradename R3000. The R3000 microprocessor re-
`quires a 64 Mhz clock signal.
`SUMMARYOF THE INVENTION
`
`The present invention relates to a clock generation
`circuit for a computer system. Specifically, the clock
`generation circuit accepts as an input a clock signal of a
`first frequency X (the system clock) and provides as an
`output a clock signal of a second frequency N time X.
`This circuit has particular application in, for example, a
`computer system having a system clock speed of X and
`in which the system clock is distributed to a plurality of
`components. In such a computer system it may be desir-
`able to replace one of such plurality of components with
`a components operating at a higher clock speed. For
`example, a processor operating at 32 Mhz maybere-
`placed by a processor operating at 64 Mhz.
`In such a case it is desirable to provide the new pro-
`cessor operating at 64 Mhz with a 64 Mhzclock signal
`synchronized with the system clock. The circuit of the
`present invention provides such a clocksignal.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 1s a block diagram illustrating an overall block
`diagram of the computer system of the present inven-
`tion.
`FIG,2 is a block diagram illustrating the computer
`system of the present invention with particular illustra-
`tion of clock signal lines utilized by the present inven-
`tion.
`FIG.3 is a block diagram illustrating a processor
`module.as may be utilized by the present invention.
`FIG.4 is a block diagram illustrating a prior art clock
`signal generation circuit.
`FIG. § is a block diagram illustrating a clock signal
`generation circuit of the present invention.
`FIG. 6 is a timing diagram illustrating a timing se-
`quence for clock signals as may be seen in the present
`invention at system power-up time.
`FIG. 7 is a timing diagram illustrating a timing se-
`quence for clock signals as may be seen in the present
`invention after phase locking has occurred.
`|
`FIG.8 is a timing diagram illustrating four phase
`clock inputs as may be utilized by the present invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`A clock generation circuit for a computer system is
`described. In the following description, numerous spe-
`cific details are set forth such as specific circuits, etc., in
`order to provide a thorough understanding of the pres-
`ent
`invention. It will be obvious, however,
`to one
`skilled in the art that the present invention may be prac-
`ticed without these specific details. In other instances,
`well-knowncircuits, structures and techniques have not
`been shown in detail in order not to unnecessarily ob-
`scure the present invention.
`.
`OVERVIEW OF THE COMPUTER SYSTEM OF
`THE PRESENT INVENTION
`
`Referring first to FIG. 1, an overview of the com-
`puter system of the present invention is shown in block
`
`

`

`5,077,686
`
`- 5
`
`30
`
`35
`
`3
`diagram form.It will be understood that while FIG, 1 is
`useful for providing an overall description of the com-
`puter system ofthe present invention,a numberofde-
`tails of the system are not shown. As necessary for
`disclosure of the present invention, further detail is set
`forth with reference to the other figures provided with
`this specification. Further, the present invention is de-
`scribed with reference to its preferred embodiment;
`alternative embodiments which may be conceived by
`one ofordinary skill in the art are considered within the
`scope ofthe claims set forth below.
`The computer system of the preferred embodiment
`may be described as a multiprocessor vector processing
`system. In one embodiment, up to forr ~~ntral process-
`ing units, CPU 1101, CPU » 102, CPU 3 103 and CPU
`4 104 are all coupled to a common bus 106. The bus
`comprises two portions labeled as RBUS 107 and SBUS
`108. RBUS107 is utilized in the present invention exclu-
`sively for vector read traffic (thus, the name RBUS).
`SBUS108 is utilized for all other transactions including
`vector writes and accesses by integer processors
`131-134, the graphics subsystem 151 and the 1/O sub-
`system 152.
`Each CPU comprises a vector unit (such as vector
`units 121, 122, 123 and 124 corresponding to CPU’s1-4,
`respectively) for performing vector operations; an inte-
`ger unit (such as integer units 131, 132, 133 and 134
`corresponding to CPU’s 1-4, respectively); and cache
`memory (such as cache memory 141,142, 143 and 144,
`respectively).
`The system further comprises interleaved memory
`109 coupled with the bus 106. The interleaved memory
`109 is coupled to both the RBUS 107 for providing
`vector data from the memory 109 and the SBUS 108 for
`all other memory accesses. Access to memory 109 is
`shared by the CPU's 1-4, the graphics subsystem 151
`and the I/O subsystem 152.
`The graphics subsystem 151 includes a graphics
`board 155 for interface to an external device through
`external interface 156. In the preferred embodiment at
`least one additional expansion graphics board may be
`provided (not shown). As stated above, the graphics
`board mayinterface with one or more external devices
`170.
`The I/O subsystem 152 includes I/O board 157
`which provides, for example, SCSI channels, keyboard
`interface, networking interface, RS-232 interface, audio
`interface, cursor control interface, etc. The I/O board
`157 is coupled through external interface 158 to one or
`more of external devices 170.
`External devices 170 includes such devices as a dis-
`play and keyboard 171, 1/O devices 172 (tape drives,
`disk drives, etc.) and other devices 173 (printers, cursor
`control devices, etc.).
`DESCRIPTION OF CLOCK SIGNAL
`DISTRIBUTION IN THE PREFERRED
`EMBODIMENT
`Referring now to FIG.2, a clock signal generator 201
`is provided on an I/O board coupled with a backplane
`202 of the computer system of the present invention.
`The clock signal generated by the clock generator 201
`is distributed over the backplane 202 to each ofa plural-
`ity of plug-in modules (only processor modules 101,
`102, 103 and 104 are shown. The clock signal generator
`preferably provides a clock at a frequency of 32 Mhz,
`however,as will be understood by one ofordinary skill
`jn the art other frequencies may be utilized without
`
`4
`departure from the present invention. Whatis important
`is that the clock frequency of the processors on modules
`101-104 are is a multiple of the frequency of the signal
`generated by clock generator 201. As will be seen, in
`the preferred embodiment, the clock rate of the integer
`units 131-134 is 64 Mhz (2 timesthe system clock rate of
`32 Mhz).
`It is worthwhile mentioning the clock generator 201
`is labeled 2X CLOCK in FIG.2. In the system of the
`preferred embodiment, a number of circuits require a
`clock rate of 16 Mhz. Therefore, in this description of
`the preferred embodiment, a 1X clock will refer to a
`clock rate of 16 Mhz, a 2X clock refers to a clock rate
`of 32 Mhz,and a 4X clock refers to. a 64 Mhz clockrate.
`It is of course understood that alternative embodiments
`mayutilize other clock rates and other multiples. For
`example, a system may require an 8 Mhz clock which
`may be termed a 1X clock, a 16 Mhz clock which may
`be termed a 2X clock, a 32 Mhz clock which maybe
`termed a 4X clock and a 64 Mhz clock which may then
`be termed an 8X clock.
`Each of the processor modules 101-104 comprise a
`DIVIDE BY2 circuit 211-214 which is coupled with
`line 203 (which carries the 32 Mhz system clock signal)
`of the backplane. The DIVIDE BY 2 circuits 211-214
`act to divide the 32 Mhz clocking frequency by two,
`thus providing a clock at a frequency of 16 Mhz on the
`plug-in boards 211-214, Frequency division circuits
`such as DIVIDE BY2 circuits 211-214 are well known
`in the applicable art.
`The clock signal is coupled through DIVIDE BY 2
`circuits 211-214 to integer processing units 131-134.
`The circuitry of integer processing units 131-134 is
`described in greater detail with reference to FIG.3.(It
`should be noted that integer processing units 131-134
`are also referred to as scalar processors 131-134 herein.)
`While the integer units 131-134 mayutilize the 16 Mhz
`clock provided from DIVIDE BY2 circuits 211-214 in
`the manner which will be described below,it should be
`noted that other circuitry on processor boards 101-104
`may utilize the 16 Mhz clock signal without any modifi-
`cation in the clock frequency. Further, in alternative
`designs certain circuitry on processor boards 101-104
`may be provided with the 32 Mhz clock while other
`circuitry is provided with the 16 Mhz clock.
`DESCRIPTION OF THE INTEGER PROCESSOR
`MODULE OF THE PREFERRED EMBODIMENT
`FIG.3 illustrates an integer processor module 302 of
`the present invention in greater detail. While FIG. 3
`illustrates only a single integer processor, it is pointed -
`out that the circuitry of this processor is duplicated on
`each processor module 101-104 in the system. (The
`integer processor 302 corresponds with integer units
`101-104 of FIG. 2.)
`The integer unit 302 receives a 1X clock signal on line
`301. Line 301 is coupled to provide the 1X clock to
`clock generator 310. Clock generator 310 provides 4
`phase offset 4X clock outputs on lines 322 to processor
`311. Clock generator 310 is further coupled to receive a
`2X clock input from processor 311 on line 321 for phase
`detection. Thecircuitry of clock generator 310 will be
`described in greater detail with reference to FIG. 5.
`However, in summary it may be said that clock genera-
`tor 310 functions to receive a clock signal of a first
`frequency N and to provide phase adjusted clock sig-
`nals as output of at a frequency of some multiple X of N.
`
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`5,077,686
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`6
`
`Clock Generation in the Preferred Embodiment
`
`5
`Specifically, X is greater than 1 and, in the preferred
`embodiment, N is 16 Mhz and X is equal to 4.
`Processor 311 is preferably a RISC processor devel-
`oped by MIPS Computer Systems, Inc. of Sunnyvale,
`Calif. running at a clock rate of 64 Mhz andavailable
`under the tradename R3000. As wasstated earlier, prior
`versions of the computer system of the preferred em-
`bodiment utilize other versions of the MIPS micro-
`processor which run at slowerclockrates, i.e., 32 Mhz.
`In order to maintain board level compatibility with such
`prior versions of the TITAN computer system,
`the
`circuitry described herein was developed.
`In the preferred embodiment, the integer unit 302, of
`course, comprises other circuitry 312. Further detail on
`the additional circuitry 312 is not essential to an under-
`standing of the present invention and, therefore, such
`detail will not be described here.
`
`The clock generation circuitry of the preferred em-
`bodimentis illustrated with reference to FIG. 5. In the
`preferred embodiment, a 1X clock signal is provided on
`line 501 of clock generator 500 to programmable delay
`line 502. Programmable delay line 502 is adjustable in
`two nanosecond steps to provide a delay in the signal
`received on line 501 of up to one-half of a clock cycle
`by adjusting the inputs on programmable inputs 507.
`Programmable inputs 507 are preferably implemented
`as dip switches or jumpers located on the PC board
`embodying the circuitry of the processor modulesof the
`present invention, such as processor modules 101-104.
`The programmable delay line 502 utilized by the pre-
`ferred embodimentis available commercially from En-
`gineering Components Company of San Luis Obispo,
`Calif. The programmable delay line 502 is utilized by
`the system of the preferred embodiment because the
`preferred processor 512 may require some unspecified
`propagation delay in the clock signal provided to it.
`Therefore, programmable delay line 502 is provided to
`Phase Shifting in the Prior Art Titan Computer
`allow for providing this delay after a particular micro-
`processor unit is selected for the processor board. The
`Prior to describing the clock generation circuitry of
`delay is adjusted after the microprocessoris installed by
`the preferred embodimentin detail, it may be useful to
`adjusting the dip switches or jumpers on the processor
`provide description of clock generation circuitry used
`board as discussed above.
`in the prior art TITAN computer. This is done with
`The delayed signal is provided to frequency multi-
`reference to FIG. 4. As stated above, the prior art
`plier 503 which acts to multiply the frequency of the
`TITAN computerincludes a processor which operates
`input clock signal by a multiple, e.g. four. In the pre-
`at a clock speed of 32 Mhz. Therefore, the system clock
`ferred embodiment, the frequency multiplier 503 multi-
`provided by 2X clock generator 201 of FIG.2 is pro-
`plies the 16 Mhz clock frequency by four providing a 64
`vided at the correct frequency for operation of the
`Mhz clock signal at the output. The frequency multi-
`processorin this prior art TITAN computer. However,
`plier 503 utilized by the preferred embodimentis avail-
`clock generation circuitry 400 is provided in the prior
`able from Engineering Components Company of San
`art TITAN computerto allow for proper phase shifting
`Luis Obispo, Calif.
`of clock signals provided to processor 412.
`The output of frequency multiplier 503 is coupled to
`In the prior art TITAN computer system, a 2X clock
`phase shifter 504 which provides for synchronization of
`signal (32 Mhz) is received by clock generator 400 on
`the input clock with the clocking of the microproces-
`line 401. As can be appreciated, this 2X clock signal is
`sor. Such synchronization is required in order to pro-
`provided from the backplane 202 on line 203 (shownin
`vide for a synchronized clock signal at system start-up
`FIG.2) and is not divided by a DIVIDE BY2circuit,
`or otherinitialization time. Phase shifter $04 is further
`such as circuits 211-214. The 2X clock signal is pro-
`coupled to receive information from phase detector 506
`vided to programmable delay generator 402. Program-
`detailing how many degrees out of phase the clock
`mable delay generator 402 provides for up to a one-half
`signal on line $01is from the clocking signals of proces-
`clock cycle delay in the clocking signal on line 401 and
`sor 512. More specifically, phase detector 506 is cou-
`is controlled by programmable inputs 407. The resulting
`pled to receive the 1X clock signal from line §01 and a
`signal is provided to phase shifter 404.
`2X clock signal provided from processor 512 on line
`Simultaneously, the clock signal on line 401 is pro-
`514. The 2X clock signal on line 514 is generated by the
`vided to phase detector 406. Phase detector 406 is fur-
`processor 512 through a DIVIDE BY 2 outputcircuit
`ther coupled to receive a 1X clock signal on line 414
`which divides the 4X clock signal utilized by the pro-
`from processor 412. The phase detector 406 determines
`cessor 512 by 2. The DIVIDE BY2 outputis a standard ©
`whetherthe clock signal on line 401 is in phase or out of
`output provided by the MIPS R3000 microprocessor
`phase with the clocking signal of processor 412, Phase
`utilized by the preferred embodiment of the present
`detector 406 is coupled to provide information to phase
`invention. The timing and synchronization of the 2X
`shifter 404 regarding the numberof degrees outof phase
`signal on line $14 and the 1X signal on line 501 will be
`better understood with reference to FIGS. 6 and 7 and
`the clock signal on line 401 is from the clock signal on
`414, Phase shifter 404 then phase shifts the clock signal
`with reference to the description of these figures set
`forth below.
`from line 401 to bring it into phase with the clock signal
`The phase shifter 504 utilized by the preferred em-
`from the processor.
`The output of phase shifter 404 is coupled to delay
`bodiment comprised of standard off-the-shelf TTL
`clock generator 405 which provides 4 phase offset 2X
`products, the construction of which will be obvious to
`clock signals on lines 411 to processor 412.
`one of ordinary skill in the art.
`The microprocessorutilized by the prior art TITAN
`The phase shifter 504 is coupled to provide the syn-
`chronized 4X clock signal to delay line clock generator
`computer (a MIPS 32 Mhz R2000 microprocessor)is
`505. The processor 512 of the preferred embodiment
`designed to receive the 4 phase offset 2X clock signals
`requires 4 phase-shifted clock signals as inputs andit is
`on lines 411 and to provide a 1X clock signal online 414
`the function of the delay line clock generator 505 to
`from DIVIDE BY 2 output circuit 413.
`
`DETAILED DESCRIPTION OF THE CLOCK
`GENERATION CIRCUITRY OF THE
`PREFERRED EMBODIMENT
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`delay line 502 is provided to allow synchronization of
`provide these 4 phase shifted clocks to the processor
`CLOCKOUTsignal 805 with the 1X clock signal 800.
`512. The delay line clock generator 505 provides the 4
`The programmable inputs 507 are adjusted to provide
`phase shifted 4X clocks on lines 511; the timing of these
`delays in the generation of clock 01 signal 801 until
`signals will be described in greater detail with reference
`CLOCK OUT 805 is synchronized with the 1X clock
`to F1G. 8.
`signal 800.
`As stated above, processor 512 of the preferred em-
`It should be noted that the specifications of the MIPS
`bodimentis available as from MIPS Computer Systems,
`R3000 microprocessor provide CLOCK OUT 805is
`Inc. of Sunnyvale, Calif. and operates at 64 Mhz.
`delayed by an unspecified interval from the clock 01
`Thus, what has been described is a circuit which
`signal 801. Although the delayis unspecified, the delay
`provides a clock signal (or plurality of clock signals) at
`is fixed for any particular R3000 microprocessor unit.
`a multiple of the system clock frequency allowing for
`Therefore, during manufacturing, assembly andtest of
`design of a computer system having processor synchro-
`the processor boardsof the preferred embodiment, the
`nized with a system clock and allowing the processors
`dip switches or jumpers (programmable inputs 507)
`to run at a clock speed which is some multiple of the
`controlling the programmable delay line 507 are ad-
`system clock speed. Thus, a multiple processor com-
`justed to provide for appropriate delay for the particu-
`puter system may have someofits processors upgraded
`Jar R3000 microprocessor unit utilized.
`to higher speed processors while retaining some of the
`Thus, a clock generation circuit has been described.
`original, lower speed, processors in the system and the
`Whatis claimedis:
`higher speed processors are run in lock step with system
`1. A computer system comprising:
`clock and, thus, in lock step with the lower speed pro-
`(a) system clock generation means for generating a
`cessors.
`first clock signal of frequency X;
`The described circuit is not only useful whereit is
`(b) processor means for processing information, said
`desired to operate a multiprocessor computer system
`processor means requiring a second clocking signal
`having certain processor running at a first speed and
`of a frequency N time X;
`certain other processors running at a second speed
`(c) frequency multiplier means for multiplying said
`while retaining synchronization between the proces-
`first clock signal by an integer N and providing
`sors. It is also useful where, as in the case of the pre-
`said processor means with said second clocking
`ferred embodiment, the system clock is provided on a
`signal;
`backplane or the like and circuitry provided on an add-
`(d) a first line coupling said system clock generation
`on board (such as a processor board) requires a higher
`means with said frequency multiplier means;
`speed clock signal than the existing system clock. The
`(e) a second line coupling said frequency multiplier
`circuit of the present invention provides such a higher
`means with said processor means; and
`speed clock without requiring replacement of the clock
`(f) frequency division means, coupled to said system
`signal generator on the backplane.
`clock generation means, dividing said first clock
`DESCRIPTION OF CLOCKING SIGNALS OF
`signal by a factor M and for providing a third clock
`signal of frequency X/M,said frequency division
`THE PREFERRED EMBODIMENT
`means coupled to provide said third clock signal to
`It is useful to an understanding of the present inven-
`said frequency multiplier means.
`tion to described certain clocking signals in greater
`2. The computer system as recited by claim 1 wherein
`detail. FIG. 6 illustrates a timing diagram showing the
`X is equal to 32 Mhz.
`1X clock signal 601 as it may appearon line 501 and the
`3. The computersystem as recited by claim 1 wherein
`2X clock signal 602 as it may appear on line 514 when
`N is equal to 4.
`the computer system of the preferred embodiment is
`4. The computer system as recited by claim 3 wherein
`initially powered-up. Asillustrated by FIG.6, the 1X
`M is equal to 2.
`clock 601 (which is in synchronization with the system
`5, A multiple processor computer system comprising:
`clock) may be initially out of phase with the 2X clock
`(a) a clock signal generator coupled with a backplane,
`602 provided from DIVIDE BY 2 output 513 of the
`said clock signa) generator for generating a first
`processor $12, (In the illustration of FIG. 6, 1X clock
`clock signal of frequency X;
`601 is shown as being 180° out of phase with the 2X
`(b>) meansfor distributing said first clock signal along
`clock signal 602.) Therefore, as discussed above, both
`said backplane;
`the 1X clock 601 and the 2X clock 602 are provided as
`(c) a first processor module having a first processor -
`inputs to phase detector 506 which detects whether
`operating at a frequency Fl, said first processor
`these clock signals are out of phase. If an out of phase
`module coupled to said backplane to receive said
`condition is detected, the phase shifter 504 is controlled
`first clock signal; and
`by the phase detector 506 to shift the phase ofthe input
`(d) a second processor module coupled to said back-
`clock signal 601. FIG.7 illustrates clock signals 601 and
`plane to receive said first clock signal, said second
`602 in phase after being affected by phase shifter 504.
`processor module comprising:
`Ofcourse,initialization of the system mayfind signals
`(1) asecond processor operating at a frequency F2;
`601 and 602 in phase; in such a case, the phase of signal
`(2) frequency multiplication means for multiplying
`601 is not shifted.
`said first clock signal frequency by a multiple N,
`FIG.8 is provided to illustrate the timing of the four
`said frequency multiplication means further cou-
`phase shifted clock signal labeled as clock 01 801, clock
`pled to provide a second clock signal of fre-
`02 802, clock 03 803 and clock 04 804 provided on lines
`quency F2to said second processor.
`511 to processor 512 as well as the 1X clock 800. The
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`6. The computersystem as recited by claim 5 wherein
`output signal from DIVIDE BY2output 513 is shown
`X is 32 Mhz.
`as CLOCK OUT 805and is delayed some unspecified,
`1. The computer system as recited by claim 6 wherein
`butfixed, time interval from clock 01 signa! 801 as indi-
`N is 4.
`cated by the unspecified delay 806. The programmable
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`8. The computer system as recited by claim 7 wherein
`F2 is 128 Mhz.
`9. The computer system as recited by claim 8 wherein
`F1 is 32 Mhz.
`10, The computer system as recited by claim 8
`wherein said second processor is a MIPS R3000 proces-
`sor.
`
`10
`second clock signal, said second clock signal hav-
`ing a frequency N times X;
`(e) said phase shifting means coupled with said multi-
`plication means to receive said second clock signal
`and coupled with said phase detection means to
`receive an indication of the relative phase of said
`first signal and said third signal, said phase shifting
`means providing as an output said phase adjusted
`clock signal.
`13. A computer system comprising:
`(a) system clock generation means for generating a
`first clock signal of a frequency X;
`(b) processor means for processing information, said
`processor means requiring a second synchronized
`clock signal of a frequency N times X, and receiv-
`ing said second synchronized clock signal from a
`synchronization means, said processor means fur-
`ther providing a third clock signal as an output,
`said processor means requiring said second syn-
`chronized clock signal to be synchronized with
`said third clock signal;
`(c) said synchronization meansfor synchronizing said
`first clock signal and said third clock signal and
`creating said second synchronized signal, said syn-
`chronization means coupled to receive said first
`clock signal from said system clock generation
`means, a fourth multiplied clock signal from a mu!l-
`tiplication means and said third clock signal from
`said processor means; and
`(d) multiplication means coupled to said system clock
`generation means, said multiplication means for
`multiplying the frequency of said first clock signal
`by a factor N and for providing as an output said
`fourth multiplied clock signal, said fourth multi-
`plied clock signal having a frequency N times X.
`*
`*
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`*
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`11. The computer system as recited by claim 5
`wherein said second processor module further compris-
`ing frequency division means coupled to receive said
`first clock signal for dividing said first clock signal by a
`factor M, said frequency division means