UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICROSOFT CORP.
`(“Microsoft”),
`Petitioner
`
`v.
`
`THROUGHPUTER, INC.
`(“ThroughPuter”),
`Patent Owner
`
`Case IPR2022-01566
`Patent No. 11,036,556
`
`DECLARATION OF JEFFREY S. CHASE, Ph.D.
`
`1
`
`MICROSOFT 1003
`
`

`

`
`
`TABLE OF CONTENTS
`
`Introduction ....................................................................................................... 5
`I.
`II. Qualifications .................................................................................................... 6
`III. Level of Ordinary Skill in the Art ..................................................................... 9
`IV. Materials Considered and Relied Upon .......................................................... 11
`V. Legal Standards ............................................................................................... 13
`A.
`Legal Standards for Prior Art .............................................................. 13
`B.
`Legal Standard for Priority Date ......................................................... 14
`C.
`Legal Standard for Obviousness ......................................................... 14
`VI. Overview of the ’556 Patent ........................................................................... 17
`A.
`Subject Matter Overview .................................................................... 17
`B.
`File History of the ’556 Patent ............................................................ 20
`C.
`Interpretation of the ’556 Patent Claims at Issue ................................ 21
`VII. Overview of the Cited References .................................................................. 22
`A. Kupferschmidt ..................................................................................... 22
`B.
`Tuan ..................................................................................................... 27
`C.
`Brent .................................................................................................... 30
`D.
`Sandstrom-501 ..................................................................................... 34
`VIII. Kupferschmidt in Combination with Tuan Renders Obvious Claims 1,
`2, and 4-8 ....................................................................................................... 36
`A.
`Combination Overview ....................................................................... 36
`B.
`Claim Element Analysis ...................................................................... 46
`
`
`
`2
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`

`

`1.
`
`2.
`
`[1.P] A system for processing a set of computer program
`
`[1.1] receiving, by hardware logic and/or software logic,
`requests to perform different tasks on behalf of
`instances of a plurality of programs managed by a
`
`Independent Claim 1 ................................................................. 46
`instances, comprising: .................................................... 47
`data processing system; .................................................. 50
`respective instance; ......................................................... 58
`
`[1.2] identifying, by the hardware logic and/or software
`logic for each of the instances, communication
`interdependencies between different processing
`stages of a set of processing stages of the
`
`[1.3] based on conditions in the data processing system,
`dynamically varying, by the hardware logic and/or
`software logic, structures of field-programmable
`gate arrays used to process different tasks of the
`instances of the plurality of programs, the
`
`structures being dynamically varied by .......................... 65
`requesting instances of respective programs, ................. 72
`
`[1.4] identifying available field-programmable gate
`arrays of the data processing system that are
`available to process different processing stages of
`
`[1.5] based at least on the conditions in the data
`processing system, identifying selected field-
`programmable gate arrays from the available field-
`programmable gate arrays to execute the different
`processing stages of the requesting instances of the
`
`respective programs, ....................................................... 78
`respective requesting instance, and ................................ 82
`network in the data processing system. .......................... 85
`Claim 2 ...................................................................................... 90
`
`[1.6] configuring the selected field-programmable gate
`arrays to process a respective processing stage of a
`
`[1.7] configuring certain selected field-programmable
`gate arrays to support communicating, by the task
`executing on the respective field-programmable
`gate array, final results to a requesting client over a
`
`
`
`3
`
`

`

`Claim 4 ...................................................................................... 92
`3.
`Claim 5 ...................................................................................... 93
`4.
`Claim 6 ...................................................................................... 94
`5.
`Claim 7 ...................................................................................... 97
`6.
`Claim 8 ...................................................................................... 97
`7.
`IX. Kupferschmidt in Combination with Tuan and Brent Renders Obvious
`Claims 1-8 ...................................................................................................... 98
`Combination Overview ....................................................................... 98
`A.
`B.
`Claim Element Analysis ....................................................................100
`1.
`Claims 1, 2, and 4-8 ................................................................100
`2.
`Claim 3 ....................................................................................101
`X. Kupferschmidt in Combination with Tuan and Sandstrom-501 Renders
`Obvious Claim 4 ..........................................................................................101
`Claim Element Analysis ....................................................................102
`A.
`1.
`Claim 4 ....................................................................................102
`XI. Kupferschmidt in Combination with Tuan, Brent, and Sandstrom-501
`Renders Obvious Claim 4 ............................................................................104
`XII. Additional Remarks ......................................................................................105
`
`
`
`
`
`
`
`
`
`4
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`

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`I, Jeffrey S. Chase, Ph.D. of Durham, North Carolina, declare that:
`
`I.
`
`Introduction
`
`1. My name is Jeffrey S. Chase, and I have been retained by counsel for
`
`Petitioner Microsoft Corp. (“Microsoft” or “Petitioner”) as an expert witness to
`
`provide assistance regarding U.S. Patent No. 11,036,556 (“the ’556 Patent”).
`
`Specifically, I have been asked to consider the validity of claims 1-8 of the ’556
`
`Patent (the “Challenged Claims”) in view of prior art and obviousness considerations
`
`from the perspective of a person of ordinary skill in the art at the time of the invention
`
`(“POSITA”) as it relates to the ’556 Patent.
`
`2.
`
`I am being compensated for my time at my standard consulting rate. I
`
`am also being reimbursed for expenses that I incur during the course of this work.
`
`My compensation is not contingent upon the results of my study, the substance of
`
`my opinions, or the outcome of any proceeding involving the challenged claims. I
`
`have no financial interest in the outcome of this matter or on the pending litigation
`
`between Petitioner and Patent Owner.
`
`3. My analysis here is based on my years of education, research and
`
`experience, as well as my investigation and study of relevant materials, including
`
`those cited herein.
`
`4.
`
`I may rely upon these materials, my knowledge and experience, and/or
`
`additional materials to rebut arguments raised by the Patent Owner. Further, I may
`
`
`
`5
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`

`

`also consider additional documents and information in forming any necessary
`
`opinions, including documents that may not yet have been provided to me.
`
`5. My analysis of the materials produced in this proceeding is ongoing and
`
`I will continue to review any new material as it is provided. This declaration
`
`represents only those opinions I have formed to date. I reserve the right to revise,
`
`supplement, and/or amend my opinions stated herein based on new information and
`
`on my continuing analysis of the materials already provided.
`
`II. Qualifications
`
`6.
`
` I have 35 years of experience as a software developer, researcher, and
`
`professor in the field of computer science, with emphasis on operating systems and
`
`systems for networked storage and data sharing, and other network services.
`
`7.
`
`In 1982, I began working as a systems programmer at Dartmouth
`
`College building software tools for an early multi-user operating system (“OS”). At
`
`Dartmouth, I also worked on embedded network router software and Internet
`
`Protocol implementations. I received my Bachelor of Arts with a double major in
`
`Mathematics and Computer Science from Dartmouth College in 1985.
`
`8.
`
`In July 1985, I began working as a software engineer for Digital
`
`Equipment Corporation’s Unix (“Ultrix”) Engineering Group (“DEC”)
`
`in
`
`Merrimack, New Hampshire. At DEC, I worked primarily on Unix operating system
`
`kernel software for file systems and storage systems, including network file systems.
`
`
`
`6
`
`

`

`I helped develop the Network File System software for DEC’s Unix operating
`
`system (Ultrix), and served as the lead developer for file system elements of DEC’s
`
`first multiprocessor Unix kernel. In 1991 I worked with a DEC development group
`
`in Redmond, Washington, to integrate software for hierarchical storage management
`
`into the file system support in the multiprocessor Ultrix kernel.
`
`9.
`
`I continued to be employed by DEC after I began graduate study in
`
`Computer Science at the University of Washington in Seattle in September of 1987.
`
`I earned my Master of Science in Computer Science in 1989, and my PhD degree in
`
`1995, both from the University of Washington in Seattle (“UW”). My research there
`
`focused on operating system software for advanced computer architectures,
`
`distributed compute clusters, and networked data sharing.
`
`10.
`
`In my doctoral research I developed new techniques and software to
`
`manage and schedule tasks (threads) for parallel applications. Specifically, I
`
`developed a system called Amber for parallel-distributed applications whose tasks
`
`execute across a network of multiprocessor machines and interact with remote
`
`method invocation, a form of inter-task communication. Amber included techniques
`
`for adaptive task scheduling in which the machines and cores assigned to an
`
`application vary over time according to need. For my dissertation work I developed
`
`operating system software for emerging wide-address architectures based on the
`
`Mach microkernel, which was designed to support threads and large-scale
`
`
`
`7
`
`

`

`multiprocessors.
`
`11. Since 1995, I have been a faculty member in Computer Science at Duke
`
`University. I have conceived and led a number of research projects and published
`
`widely in leading research forums in the areas of operating systems, storage systems,
`
`and networked systems. I earned tenure at Duke University in 2002 and was
`
`promoted to Full Professor in 2006.
`
`12. At Duke, I teach courses for undergraduate and graduate students on
`
`operating systems, networking and networked systems, distributed systems, and
`
`Internet technology and society.
`
`13. My research has spanned a broad range of topics relating to networked
`
`computer systems and Internet systems in particular. I have published over 100 peer-
`
`reviewed papers on these topics over my research career. Much of my later research
`
`deals with communication, coordination, and data sharing mechanisms in networked
`
`systems. I am a named inventor on eleven US patents.
`
`14.
`
`I have served in a number of editorial and organizing roles for various
`
`academic forums and publications in these areas. For example, I have served on the
`
`editorial Program Committee for the ACM Symposium on Operating Systems
`
`Principles (SOSP) and ACM/USENIX Symposium on Operating System Design and
`
`Implementation (OSDI), the leading academic conferences on operating system
`
`technologies. I served as Program Chair for Systems Software for the
`
`
`
`8
`
`

`

`Supercomputing Conference (SC) 2005, and multiple times on the editorial
`
`committee for the IEEE Symposium on High Performance Distributed Computing
`
`(HPDC), most recently in 2020. I have had similar roles in many other related
`
`academic venues as reported on my Curriculum Vitae.
`
`15.
`
`In addition to my industry work, I have conducted a number of research
`
`projects related to the technical subjects at issue. Over the 1995–2004 period, my
`
`research team at Duke developed new techniques to manage high-speed
`
`communication, scalable data access, and adaptive execution of Internet/Web
`
`service software and other variable workloads in parallel across compute clusters
`
`and networks of clusters, focusing on techniques to manage server resources in
`
`datacenters under such massively parallel workloads.
`
`16. More recently I have conducted detailed performance studies of parallel
`
`file systems in petascale supercomputers and the impact of design choices on parallel
`
`computing applications.
`
`17. A detailed record of my professional qualifications, including a list of
`
`publications, awards, and professional activities, is attached as Appendix A to this
`
`report and summarized below.
`
`III. Level of Ordinary Skill in the Art
`
`18.
`
`In rendering the opinions set forth in this declaration, I was asked to
`
`consider the patent claims and the prior art through the eyes of a POSITA at the time
`
`
`
`9
`
`

`

`of the alleged invention, which I understand is asserted to be August 23, 2013—the
`
`filing date of a provisional application in the alleged priority chain of the ’556 Patent.
`
`I understand that the factors considered in determining the ordinary level of skill in
`
`a field of art include the level of education and experience of persons working in the
`
`field; the types of problems encountered in the field; the teachings of the prior art,
`
`and the sophistication of the technology at the time of the alleged invention. I
`
`understand that a POSITA is not a specific real individual, but rather is a hypothetical
`
`individual having the qualities reflected by the factors above. I understand that a
`
`POSITA would also have knowledge from the teachings of the prior art, including
`
`the art cited below.
`
`19. Taking these factors into consideration, on or before August 23, 2013,
`
`a POSITA relating to the technology of the ’556 Patent would have had a Master’s
`
`degree in computer science, computer engineering, or a related field, and 2-3 years
`
`of practical computer programming or engineering experience, including experience
`
`designing or researching parallel processing systems. Additional graduate education
`
`could substitute for professional experience, or significant experience in the field
`
`could substitute for formal education.
`
`20. Before August 23, 2013, my level of skill in the art was at least that of
`
`a POSITA. I am qualified to provide opinions concerning what a POSITA would
`
`have known and understood at that time, and my analysis and conclusions herein are
`
`
`
`10
`
`

`

`from the perspective of a POSITA as of that date.
`
`IV. Materials Considered and Relied Upon
`
`21.
`
`In reaching the conclusions described in this declaration, I have relied
`
`on the documents and materials cited herein as well as those identified in this
`
`declaration, including the ’556 Patent, the prosecution history of the ’556 Patent, and
`
`prior art references cited herein. These materials comprise patents, related
`
`documents, and printed publications. Each of these materials is a type of document
`
`that experts in my field would have reasonably relied upon when forming their
`
`opinions.
`
`22.
`
`I have also relied on my education, training, research, knowledge, and
`
`personal and professional experience in the relevant technologies and systems that
`
`were already in use prior to, and within the timeframe of the earliest priority date of
`
`the claimed subject matter in the ’556 Patent, which is August 23, 2013.
`
` EX1001: U.S. Pat. No. 11,036,556 (“the ’556 Patent”)
`
` EX1002: File History of the ’556 Patent (selected excerpts)
`
` EX1004: U.S. Pat. App. Pub. No. 2010/0333099 (“Kupferschmidt”)
`
` EX1005: Vu Manh Tuan, “A Study on a Multitasking Environment for
`Dynamically Reconfigurable Processors,” Doctoral Dissertation,
`School of Science for Open and Environmental Systems Graduate
`School of Science and Technology, Keio University (2009) (“Tuan”)
`
` EX1006: U.S. Pat. App. Pub. No. 2010/0131955 (“Brent”)
`
` EX1009: U.S. Pat. App. Pub. No. 2014/0245262 (“Hill”)
`
`
`
`11
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`

`

` EX1010: U.S. Pat. App. Pub. No. 2012/0079501 (“Sandstrom-501”)
`
` EX1011: Excerpts of Phillip A. Laplante, Dictionary of Computer
`Science, Engineering, and Technology, CRC Press (2001)
`
` EX1012: Excerpts of Alan Freedman, Computer Desktop
`Encyclopedia, 9th Ed. (2001)
`
` EX1013: Excerpts of McGraw-Hill Dictionary of Scientific and
`Technical Terms, Sixth Edition (2003)
`
` EX1014: Excerpts of Random House Concise Dictionary of Science
`and Computers (2004)
`
` EX1015: Excerpts of A Dictionary of Computing, Oxford University
`Press, Sixth Edition (2008)
`
` EX1016: Excerpts of The Facts on File Dictionary of Computer
`Science, Revised Edition (2006)
`
` EX1017: U.S. Pat. No. 5,542,055 (“Amini”)
`
` EX1018: U.S. Pat. No. 4,647,123 (“Chin”)
`
` EX1019: Jessica Scarpati, Definition of “host” (in computing),
`https://www.techtarget.com/searchnetworking/definition/host
`(retrieved September 18, 2022)
`
` EX1020: U.S. Pat. App. Pub. No. 2008/0244126 (“Hundley”)
`
` EX1021: U.S. Pat. No. 8,055,872 (“Biles”)
`
` EX1022: U.S. Pat. App. Pub. No. 2005/0044344 (“Stevens”)
`
` EX1023: Muhammad Yasir, Introduction to FPGA Technology (May
`12, 2011), available at
`https://www.fpgarelated.com/showarticle/17.php (retrieved September
`27, 2022)
`
` EX1024: Microsoft Timeline Webpage: First Version of Windows
`Announced, available at
`https://news.microsoft.com/announcement/first-version-of-windows-
`
`
`
`12
`
`

`

`announced/?return=https%3A%2F%2Fnews.microsoft.com%2Fabout
`%2F (retrieved September 28, 2022)
`
` EX1025: Dror G. Feitelson, Job Scheduling in Multiprogrammed
`Parallel Systems, IBM Research Report, Extended Version (Second
`Rev. August 1997)
`
` EX1026: U.S. Pat. No. 9,632,833 (“’833 Patent”)
`
`
`V. Legal Standards
`
`23.
`
`I am not a lawyer and do not provide any legal opinions, but I have been
`
`advised that certain legal standards are to be applied by technical experts in forming
`
`opinions regarding meaning and validity of patent claims. I have applied the legal
`
`standards described below, which were provided to me by counsel for the Petitioner.
`
`24.
`
`It is my understanding that assessing the validity of a U.S. patent based
`
`on a prior art analysis involves two steps. First, one must construe the terms of the
`
`patent claims to understand what meaning one of ordinary skill in the art would have
`
`given the terms. Second, after the claim terms have been construed, one may then
`
`assess validity by comparing a patent claim to the “prior art.” I understand that the
`
`teaching of the prior art is viewed through the eyes of a POSITA at the time of the
`
`invention. My analysis as to what constitutes a relevant POSITA is set forth above.
`
`A. Legal Standards for Prior Art
`
`25.
`
`I understand that a patent or other publication must first qualify as prior
`
`art before it can be used to invalidate a patent claim. For purposes of this declaration,
`
`
`
`13
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`

`

`counsel for Petitioner has instructed me to assume that each prior art reference cited
`
`in the combinations described below (i.e., Kupferschmidt, Tuan, Brent, and
`
`Sandstrom-501) qualify as prior art to the ’556 Patent.
`
`B.
`
`Legal Standard for Priority Date
`
`26.
`
`I understand that the “priority date” (or “earliest effective filing date”
`
`or “Critical Date”) of a patent is the date on which it is filed, or the date on which an
`
`earlier application was filed if the patentee properly claims the benefit of the earlier
`
`application’s filing date. For purposes of my analysis in this declaration, I have
`
`assumed that the ’556 Patent is entitled to a priority date of August 23, 2013.
`
`C. Legal Standard for Obviousness
`
`27. My understanding is that a patent claim is invalid as obvious only if the
`
`subject matter of the claimed invention “as a whole” would have been obvious to a
`
`POSITA at the time of the invention. To determine the differences between a prior
`
`art reference (or a proposed combination of prior art references) and the claims, the
`
`question of obviousness is not whether the differences themselves would have been
`
`obvious, but whether the claimed invention as a whole would have been obvious.
`
`Also, obviousness grounds cannot be sustained by mere conclusory statements.
`
`Rather, it is necessary to provide some articulated reasoning with rational
`
`underpinning to support the legal conclusion of obviousness.
`
`28.
`
`I understand that a patent claim that comprises several elements is not
`
`
`
`14
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`

`proved obvious by simply showing that each of its elements was independently
`
`known in the prior art. In my evaluation of whether any claim of the ’556 Patent
`
`would have been obvious, I considered whether the Petition, or any evidence
`
`submitted in this proceeding, presented an articulated reason with a rational basis
`
`that would have motivated a POSITA to combine the elements or concepts from the
`
`prior art in the same way as in the claimed invention.
`
`29.
`
`It is my understanding that there is no single way to define the line
`
`between true inventiveness on one hand—which is patentable—and the application
`
`of common sense and ordinary skill to solve a problem on the other hand—which is
`
`not patentable. For instance, factors such as market forces or other design incentives
`
`may be the source of what produced a change, rather than true inventiveness.
`
`30.
`
`I understand that the decision-maker may consider whether the change
`
`was merely the predictable result of using prior art elements according to their
`
`known functions, or whether it was the result of true inventiveness. And, the
`
`decision-maker may also consider whether there is some teaching or suggestion in
`
`the prior art to make the modification or combination of elements recited in the claim
`
`at issue. Also, the decision-maker may consider whether the innovation applies a
`
`known technique that had been used to improve a similar device or method in a
`
`similar way. The decision-maker may also consider whether the claimed invention
`
`would have been obvious to try, meaning that the claimed innovation was one of a
`
`
`
`15
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`

`

`relatively small number of possible approaches to the problem with a reasonable
`
`expectation of success by those skilled in the art.
`
`31.
`
`I have been instructed by counsel that if any of these considerations are
`
`relied upon to reach a conclusion of obviousness, the law requires that the analysis
`
`of such a consideration must be made explicit. I understand that the decision-maker
`
`must be careful not to determine obviousness using the benefit of hindsight and that
`
`many true inventions might seem obvious after the fact. I understand that the
`
`decision-maker should consider obviousness from the position of a POSITA at the
`
`time the claimed invention was made, and that the decision-maker should not
`
`consider what is known today or what is learned from the teaching of the patent.
`
`32.
`
`I understand that in order to determine whether a patent claim is
`
`obvious, one must make certain factual findings regarding the claimed invention and
`
`the prior art. Specifically, I understand that the following factors must be evaluated
`
`to determine whether a claim is obvious: the scope and content of the prior art; the
`
`difference or differences, if any, between the claim of the patent and the prior art;
`
`the level of ordinary skill in the art at the time of the claimed invention; and, if
`
`available, the objective indicia of non-obviousness, also known as “secondary
`
`considerations.”
`
`33.
`
`I understand that the secondary considerations include: commercial
`
`success of a product due to the merits of the claimed invention; a long felt need for
`
`
`
`16
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`

`

`the solution provided by the claimed invention; unsuccessful attempts by others to
`
`find the solution provided by the claimed invention; copying of the claimed
`
`invention by others; unexpected and superior results from the claimed invention;
`
`acceptance by others of the claimed invention as shown by praise from others in the
`
`field or from the licensing of the claimed invention; teaching away from the
`
`conventional wisdom in the art at the time of the invention; independent invention
`
`of the claimed invention by others before or at about the same time as the named
`
`inventor thought of it; and other evidence tending to show obviousness.
`
`34.
`
`I understand that, to establish a secondary consideration, the evidence
`
`must demonstrate a nexus between that secondary consideration and the claimed
`
`invention.
`
`VI. Overview of the ’556 Patent
`
`A.
`
`Subject Matter Overview
`
`35. The
`
`’556 Patent
`
`is
`
`titled “Concurrent Program Execution
`
`Optimization,” and discloses “[a]n architecture for a load-balanced groups [sic] of
`
`multi-stage manycore processors shared dynamically among a set of software
`
`applications.” EX1001, Abstract. Figure 2 depicts an embodiment of this
`
`architecture, which includes “hardware logic implemented capabilities for
`
`scheduling tasks of application program instances and prioritizing inter-task
`
`communications (ITC) among tasks of a given app instance.” EX1001, 10:10-13;
`
`
`
`17
`
`

`

`generally id., 10:7-11:16.
`
`
`
`EX1001, FIG. 2 (annotated).
`
`36. The specification states that “[i]n the architecture per FIG. 2, the multi-
`
`stage manycore processor system 1 is shared dynamically among tasks of multiple
`
`application programs (apps) and instances (insts) thereof.” Id., 10:29-32. “[F]or
`
`each of the apps, each task [is] located at one of the (manycore processor) based
`
`processing stages 300,” although “for any given app-inst, copies of same task
`
`software (i.e. copies of same software code) can be located at more than one of the
`
`processing stages 300 of a given system 1.” Id., 10:32-42, 6:23-33, 10:56-11:16.
`
`
`
`18
`
`

`

`Thus, each worker stage 300 can host a single task for each of one or more software
`
`applications. A worker stage 300 can further manage one or multiple instances of
`
`each hosted task for each application. Id.
`
`37. Each processing stage 300 includes an array 515 of processing cores
`
`520, and includes logic to periodically assign sets of app-task-instances to the cores
`
`for execution. EX1001, 20:7-63; generally id., 15:21-20:63, FIGS. 5-7. For
`
`example, for each core allocation period (CAP), scheduling logic can allocate a
`
`specific number of cores to each application, determine a prioritized list of app-task-
`
`instances, select the highest-priority task-instances of each application, and assign
`
`each selected app-task-instance to a respective core for execution during the CAP.
`
`Id.
`
`38.
`
`I understand that the claims of the ’556 Patent further include
`
`limitations directed to field-programmable gate arrays (FPGAs). See, e.g., [1.1]-
`
`[1.7]. The specification mentions FPGAs at col. 20:21-29, which states that “[a]ny
`
`of the cores 520 of a processor per FIG. 7 can comprise any types of software
`
`program and data processing hardware resources, e.g. central processing units
`
`(CPUs), graphics processing units (GPUs), digital signal processors (DSPs) or
`
`application specific processors (ASPs) etc., and in programmable logic (FPGA)
`
`implementation, the core type for any core slot 520 is furthermore reconfigurable
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`per expressed demands of its assigned app-task.” EX1001, 20:21-291.
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`B.
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`File History of the ’556 Patent
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`39.
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`I have reviewed portions of the file history of the ’556 Patent, which
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`has been submitted as Exhibit 1002 in this proceeding. Based on this review, I
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`understand that the application that later issued as the ’556 Patent (i.e., U.S. Patent
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`Application Serial No. 17/195,174) was filed March 8, 2021. The Examiner issued
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`no rejections of claims of the ’174 Application before the application was allowed
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`on May 14, 2021. EX1002, 9-19. The Examiner’s statement of reasons for
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`allowance explained that the claims were “considered allowable because no prior art
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`or combination of prior art references disclose or suggest the combination of
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`limitations specified in the independent claims.” Id., 15.
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`40. Nonetheless, I understand that neither Kupferschmidt nor Tuan are
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`cited in the file history as having previously been considered by the Examiner with
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`respect to the claims of the ’556 Patent. For the reasons I address below, the
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`teachings of Kupferschmidt and Tuan, along with combinations based on these
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`references and Brent and Sandstrom-501, would have rendered obvious each of the
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`allowed claims.
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`
`1 All emphasis in this declaration is added unless noted otherwise.
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`20
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`C.
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`Interpretation of the ’556 Patent Claims at Issue
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`41. For purposes of my analysis in this IPR proceeding, I understand that
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`the terms that appear in the claims of the ’556 Patent should be interpreted according
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`to their plain and ordinary meaning. I understand that the plain and ordinary
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`meaning of a claim term reflects the ordinary meaning that the term would have had
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`to a POSITA at the time of the alleged invention in the context of the technology
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`described in the patent. I also understand that the structure of the claims, the
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`specification and file history also may be used to better construe a claim insofar as
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`the plain meaning of the claims cannot be understood. Moreover, I understand that
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`even treatises and dictionaries may be used, albeit under limited circumstances, to
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`determine the meaning attributed by a POSITA to a claim term at the time of the
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`alleged invention. Except to the extent indicated otherwise in my analysis of the
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`individual claim elements, I have applied the plain and ordinary meaning to the terms
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`of the Challenged Claims in light of the specification and file history of the ’556
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`Patent.
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`42.
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`I also understand that the words of the claims should be interpreted as
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`they would have been interpreted by a POSITA at the time of the claimed invention
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`(not today). For purposes of my analysis here, I have used August 23, 2013 (i.e., the
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`earliest effective filing date or “Critical Date” of the ’556 Patent) as the date of
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`invention. Without exception, however, my analysis of the proper meanings of the
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`terms recited in the Challenged Claims would remain substantially the same even if
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`the date of invention occurred anywhere in the early-to-mid 2010s.
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`VII. Overview of the Cited References
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`A. Kupferschmidt
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`43. Kupferschmidt generally describes
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`techniques for parallelizing
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`execution of tasks on a multi-core processing system. Figure 2, for example
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`(reproduced below), illustrates a network-on-chip (NOC) device 102 constructed
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`with an array of interconnected processing cores, referred to as “integrated
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`processor” (“IP”) blocks 104. EX1004, [0041]-[0047], FIG. 2. NOC 102
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`implements a “mesh network” of nodes comprised of IP blocks 104, network
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`interface controllers 108, routers 110, and memory communications controllers 106.
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`The mesh network enables IP blocks 104 to communicate with IP blocks 104 at other
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`nodes, and to send data produced by the task executing at one node to another node
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`for further processing. EX1004, [0044], FIG. 2; generally id., [0044]-[0052].
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`
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`EX1004, FIG. 2 (annotated).
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`44. According to Kupferschmidt, “each IP block represents a reusable unit
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`of synchronous or asynchronous logic design.” EX1004, [0045]. In some examples,
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`IP block 104 is implemented as a “generally programmable microcomputer.” Id.,
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`23
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`[0053]; see also id., FIGS. 3-4. However, IP blocks 104 are not limited to general-
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`purpose processors, and can alternativel