Trials@uspto.gov
`571-272-7822
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`XILINX, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`IPR2023-00516
`Patent 6,157,589
`____________
`
`
`
`Before JEAN R. HOMERE, BARBARA A. PARVIS, and MINN CHUNG,
`Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`
`Paper 12
`Date: September 15, 2023
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`571-272-7822
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`XILINX, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`____________
`
`IPR2023-00516
`Patent 6,157,589
`____________
`
`
`
`Before JEAN R. HOMERE, BARBARA A. PARVIS, and MINN CHUNG,
`Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`
`
`
`Paper 12
`Date: September 15, 2023
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`I. INTRODUCTION
`Xilinx, Inc. (“Petitioner”) filed a Petition (Paper 2, “Pet.”) requesting
`an inter partes review of claims 1, 2, and 8–13 (the “challenged claims”) of
`U.S. Patent No. 6,157,589 (Ex. 1001, “the ’589 patent”). Polaris
`Innovations Limited (“Patent Owner”) timely filed a Preliminary Response.
`Paper 11 (“Prelim. Resp.”).
`We have authority to determine whether to institute an inter partes
`review. See 35 U.S.C. § 314; 37 C.F.R. § 42.4(a). Under 35 U.S.C.
`§ 314(a), institution of an inter partes review is authorized when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition.” Taking into account
`the arguments and evidence presented in Patent Owner’s Preliminary
`Response, we determine that the information presented in the Petition
`establishes that there is a reasonable likelihood that Petitioner would prevail
`in showing the unpatentability of at least one challenged claim.
`Accordingly, we institute an inter partes review of all challenged claims of
`the ’589 patent, based on all grounds raised in the Petition.
`
`II. BACKGROUND
`A. Related Matters
`According to the parties, the ’589 patent is involved in the following
`proceeding: Polaris Innovations Ltd. v. Xilinx, Inc., No. 1:22-cv-00174-
`RGA (D. Del.). Pet. 1; Paper 3, 2. Patent Owner further states that the ’589
`patent is also the subject of Polaris Innovations Limited v. Broadcom, Inc.,
`No. 2:22-cv-00347 (E.D. Tex.). Paper 10, 2–3.
`
`2
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`B. Real Parties-in-Interest
`Petitioner identifies itself, Advanced Micro Devices, Inc., and ATI
`Technologies ULC as the real parties-in-interest. Pet. 1. Patent Owner
`identifies itself, Wi-LAN Inc., Owlpoint IP Opportunities JVF LP, and
`Quarterhill Inc. as the real parties-in-interest. Paper 10, 2.
`
`C. The ’589 Patent
`The ’589 patent issued December 5, 2000 from U.S. Patent
`Application No. 09/343,431, filed June 30, 1999. Ex. 1001, codes (21), (22),
`(45).
`
`The ’589 patent describes an initialization circuit for a dynamic
`semiconductor memory device (“DRAM”). Id. at 1:10–13, Abstract. As
`background, the ’589 patent describes that for proper operation of a
`semiconductor memory device,
`it is necessary to ensure during the switch-on operation
`(“POWERUP”) that the internal control circuits . . . are reliably
`held in a defined desired state, in order to prevent undesirable
`activation of output transistors that would cause, on the data
`lines, a short circuit (so-called “bus contention” or “data
`contention”) or uncontrolled activation of internal current loads.
`Id. at 1:23–30. According to the ’589 patent, “[t]he solution to the problem
`turns out to be difficult” due to “a fundamental unpredictability of the time
`characteristic of the supply voltage and of the voltage level or levels at the
`external control inputs during the switch-on operation of the semiconductor
`memory.” Id. at 1:30–35. The ’589 patent describes that, to address this
`problem, the JEDEC standard for dynamic semiconductor memories
`specified that a predetermined initialization sequence of commands—e.g., a
`sequence comprising PRECHARGE, AUTOREFRESH, and
`
`3
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`MODE-REGISTER-SET commands—must be applied in a defined
`chronological order before proper operation of the control circuits is
`allowed. Id. at 1:35–61. According to the ’589 patent, “[a]fter the
`identification of such a defined initialization sequence, the memory module
`is normally in a so-called IDLE state . . . and prepared for proper
`operation”—i.e., “all the control circuits of the component have been
`unlatched.” Id. at 1:62–67.
`Against this backdrop, the ’589 patent describes embodiments of a
`DRAM initialization circuit that contains a control circuit for controlling
`operations and an enable circuit that outputs an enable signal after
`identifying a predetermined proper initialization sequence of externally
`applied further command signals, the enable signal effecting an unlatching
`of the control circuit for proper operation of the semiconductor memory
`device. Id. at 2:15–37.
`Figure 1 of the ’589 patent is reproduced below.
`
`
`
`4
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`Figure 1 is a block diagram of components of the ’589 patent’s initialization
`circuit which controls a switching-on operation of a semiconductor memory
`operating according to the JEDEC standard. Id. at 3:28–31, 3:44–48.
`With reference to Figure 1, the ’589 patent describes:
`The initialization circuit has an input circuit 1, to whose input 2
`command and clock signals that are externally applied in
`reference to the semiconductor memory are provided. The
`command and clock signals are amplified and conditioned before
`being received by a command decoder 3 connected downstream
`of the input circuit 1 and at whose output 4, inter alia, the
`command signals PRE or PRECHARGE (preparation command
`for word line activation), ARF or AUTOREFRESH (refresh
`command) and MRS or MODE-REGISTER-SET (loading
`configuration register command) are output.
`Id. at 3:51–61. The initialization circuit further includes circuit 5 for internal
`voltage regulation and/or detection, which supplies an active POWERON
`signal if, after the POWERUP phase of the memory device, the internal
`supply voltages present at output 8 have reached the values necessary for
`proper operation of the component. Id. at 3:61–4:8.
`According to the ’589 patent,
`the initialization circuit furthermore has an enable circuit 9
`connected downstream of the circuits 3 and 5. The command
`signals PRE, ARF and MRS are applied to an input 10 of the
`enable circuit 9 and the POWERON signal is applied to an input
`11 of the enable circuit 9. An enable signal CHIPREADY is
`supplied at an output 12 of the enable circuit 9 after the
`identification of a predetermined proper initialization sequence
`of the command signals applied to the semiconductor memory
`device is achieved. The enable signal effects unlatching of
`control circuits 13 provided for proper operation of the
`semiconductor memory device.
`
`5
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`Id. at 4:9–20.
`Figure 2 of the ’589 patent is reproduced below.
`
`
`Figure 2 shows an exemplary enable circuit that supplies an enable signal
`(CHIPREADY). Id. at 3:32–33, 4:24–25.
`As shown in Figure 2, enable circuit 9 contains three bistable
`multivibrator stages 14, 15 and 16, each having a set input S, a reset input R,
`and also an output Q. Id. at 4:25–28. The command signals PRE, ARF,
`MRS are applied to the respective set inputs S of the bistable multivibrator
`stages 14, 15, 16, whereas the POWERON signal is applied to the reset
`inputs R. Id. at 4:36–38, 4:41–45.
`According to the ’589 patent,
`activation of the enable signal CHIPREADY at is the output 12
`to logic HIGH is generated only when a predetermined
`chronological initialization sequence of the command signals
`
`6
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`PRE, ARF and MRS and activation of the POWERON signal to
`the logic level HIGH are detected. Only then are the control
`circuits 13 unlatched on account of the activation of the enable
`signal CHIPREADY.
`Id. at 4:50–57.
`Figure 3 of the ’589 patent is reproduced below.
`
`
`
`Figure 3 is a schematic time sequence diagram illustrating exemplary
`command sequences detected by enable circuit 9 of Figure 2. Id. at 3:34–35,
`4:59–63.
`According to the ’589 patent,
`In case situation C, a correct chronological order of the
`commands
`PRECHARGE, AUTOREFRESH, MODE-
`REGISTER-SET is present conforming to the JEDEC standard,
`in a logically consistent manner, since the POWERON signal is
`also at logic HIGH, an enable signal CHIPREADY at logic
`HIGH is now supplied. Illustrated using dashed lines, another
`further conceivable initialization sequence that is allowed and
`therefore triggers an enable signal is represented by the symbol
`
`7
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`D; activation of the command MODE-REGISTER-SET to logic
`LOW is allowed at any time after the activation of the
`POWERON signal.
`Id. at 5:10–21.
`
`D. Illustrative Claim
`Of the challenged claims, claims 1 and 11 are independent. Claim 1 is
`illustrative of the challenged claims and is reproduced below with line
`breaks and indenting added to improve readability.
`1. A dynamic semiconductor memory device of a random
`access type, comprising:
`an initialization circuit controlling a switching-on operation
`and supplying a supply voltage stable signal once a supply
`voltage has been stabilized after
`the switching-on
`operation,
`said initialization circuit having a control circuit for
`controlling operations and an enable circuit receiving the
`supply voltage stable signal and externally applied further
`command signals,
`said enable circuit outputting an enable signal after a
`predetermined proper initialization sequence of the
`externally applied further command signals being
`identified and the enable signal effecting an unlatching of
`said control circuit.
`Ex. 1001, 5:31–44.
`
`E. Prior Art and Declaration Evidence
`Petitioner cites the following references in its challenge to
`patentability:
`U.S. Patent No. 5,559,753, issued Sept. 24, 1996 (Ex. 1004, “Kocis”);
`
`8
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`U.S. Patent No. 5,703,510, issued Dec. 30, 1997 (Ex. 1007,
`“Iketani”);
`U.S. Patent No. 5,774,402, issued June 30, 1998 (Ex. 1005, “Lee”);
`
`and
`
`JEDEC Standard No. 21-C, Jan. 1997 (Ex. 1006, “JESD 21-C”).
`Petitioner supports its challenge with a declaration from Stephen W.
`Melvin (Ex. 1003, “Melvin Declaration”). Patent Owner’s Preliminary
`Response does not rely on the testimony of any declarant.
`
`F. Asserted Grounds of Unpatentability
`Petitioner asserts that the challenged claims are unpatentable based on
`the following grounds (Pet. 3).
`
`Claim(s) Challenged
`1, 9, 11, 13
`2, 8, 10, 12
`1, 11
`1, 11
`1, 11
`2, 8, 10, 12
`2, 8, 10, 12
`
`35 U.S.C. §1
`102
`103
`102
`103
`103
`103
`103
`
`Reference(s)
`Kocis
`Kocis, JESD 21-C
`Lee
`Lee
`Lee, Iketani
`Lee, JESD 21-C
`Lee, Iketani, JESD 21-C
`
`
`1 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011), amended 35 U.S.C. §§ 102 and 103 effective March 16, 2013.
`Because the ’589 patent has a filing date prior to the effective date of the
`applicable AIA amendments, we refer to the pre-AIA versions of §§ 102 and
`103.
`
`9
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`Claim(s) Challenged
`9, 13
`9, 13
`
`35 U.S.C. §1
`103
`103
`
`Reference(s)
`Lee, Kocis
`Lee, Iketani, Kocis
`
`
`
`III. ANALYSIS
`A. Level of Ordinary Skill in the Art
`The level of ordinary skill in the pertinent art at the relevant time is a
`factor in how we construe patent claims. See Phillips v. AWH Corp., 415
`F.3d 1303, 1312–13 (Fed. Cir. 2005) (en banc). It is also one of the factors
`we consider when determining whether a patent claim is obvious over the
`prior art. See Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`To assess the level of ordinary skill, we construct a hypothetical
`“person of ordinary skill in the art,” from whose vantage point we assess
`obviousness and claim interpretation. See In re Rouffet, 149 F.3d 1350,
`1357 (Fed. Cir. 1998). This legal construct “presumes that all prior art
`references in the field of the invention are available to this hypothetical
`skilled artisan.” Id. (citing In re Carlson, 983 F.2d 1032, 1038 (Fed. Cir.
`1993)).
`Citing testimony from Dr. Melvin, Petitioner asserts a person of
`ordinary skill in the art (“POSITA”) at the relevant time would have had “a
`Bachelor’s degree in Electrical Engineering or Computer Science and two
`years of experience” or “equivalent education, work, or experience in this
`field.” Pet. 21 (citing Ex. 1003 ¶¶ 31–34). According to Dr. Melvin,
`“[m]ore education could substitute for experience, and vice versa.”
`Ex. 1003 ¶ 33.
`
`10
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`Patent Owner states that “[f]or the limited purpose of this Preliminary
`Response, Patent Owner does not contest Petitioner’s definition of a person
`of ordinary skill in the art, but it reserves the right to do so in the event that
`trial is instituted.” Prelim. Resp. 11.
`For purposes of this Decision, based on our review of the ’589 patent,
`the types of problems and solutions described in the ’589 patent, and cited
`prior art, we adopt and apply Petitioner’s unopposed definition of a person
`of ordinary skill in the art.
`
`B. Claim Construction
`In an inter partes review, we construe a patent claim “using the same
`claim construction standard that would be used to construe the claim in a
`civil action under 35 U.S.C. 282(b).” 37 C.F.R. § 42.100(b) (2022). In
`applying such standard, claim terms are generally given their ordinary and
`customary meaning, as would be understood by a person of ordinary skill in
`the art, at the time of the effective filing date of the patent application and in
`the context of the entire patent disclosure. Phillips, 415 F.3d at 1312–13.
`“In determining the meaning of the disputed claim limitation, we look
`principally to the intrinsic evidence of record, examining the claim language
`itself, the written description, and the prosecution history, if in evidence.”
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17).
`Petitioner asserts that “construction of terms is unnecessary because it
`is not dispositive to this case—the art teaches the limitations under any
`construction under the Phillips standard.” Pet. 21. Patent Owner states that
`
`11
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`we need not construe any claim term for purposes of this Decision. See
`Prelim. Resp. 11.
`Based on the record presented, we need not construe any claim term
`for purposes of this Decision. See Realtime Data, LLC v. Iancu, 912 F.3d
`1368, 1375 (Fed. Cir. 2019) (“The Board is required to construe ‘only those
`terms . . . that are in controversy, and only to the extent necessary to resolve
`the controversy.’” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999))).
`
`C. Asserted Grounds of Unpatentability Based on Lee or the Combination of
`Lee and Iketani
`Petitioner contends that independent claims 1 and 11 are unpatentable
`under 35 U.S.C. § 103(a) over Lee. Pet. 46–58. In addition, Petitioner
`asserts that the subject matter of claims 1 and 11 would have been obvious
`over the combination of Lee and Iketani. Id. at 59–63. Petitioner also
`contends that claims 1 and 11 are unpatentable as anticipated by Lee. Id. at
`46–58. Patent Owner disputes Petitioner’s contentions. Prelim. Resp. 32–
`37.
`
`1. Relevant Principles of Law
`A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
`art reference expressly or inherently describes each and every limitation set
`forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
`1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
`631 (Fed. Cir. 1987). Further, a reference cannot anticipate “unless [it]
`discloses within the four corners of the document not only all of the
`limitations claimed[,] but also all of the limitations arranged or combined in
`
`12
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`the same way as recited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
`545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
`arranged in the same way as in the claim, “the reference need not satisfy an
`ipsissimis verbis test,” i.e., identity of terminology is not required. In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832 (Fed. Cir. 1990).
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which the subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations, including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations. Graham, 383 U.S. at 17–18.
`Additionally, the obviousness inquiry typically requires an analysis of
`“whether there was an apparent reason to combine the known elements in
`the fashion claimed by the patent at issue.” KSR, 550 U.S. at 418 (citing
`In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (requiring “articulated
`reasoning with some rational underpinning to support the legal conclusion of
`obviousness”)); accord Kinetic Concepts, Inc. v. Smith & Nephew, Inc., 688
`F.3d 1342, 1366–67 (Fed. Cir. 2012) (holding that “some kind of motivation
`must be shown from some source, so that the [trier of fact] can understand
`why a person of ordinary skill would have thought of either combining two
`
`13
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`or more references or modifying one to achieve the patented [invention]”)).
`Petitioner cannot satisfy its burden of proving obviousness by employing
`“mere conclusory statements.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d
`1364, 1380 (Fed. Cir. 2016).
`We analyze the asserted grounds of unpatentability with the principles
`identified above in mind.
`
`2. Overview of Lee (Ex. 1005)
`Lee describes an initialization circuit for a semiconductor memory
`device, which includes an initialization signal generator that generates an
`initialization signal in response to a specific sequence of reset control
`signals. Ex. 1005, Abstract.
`As background, Lee describes that semiconductor memory devices
`require initialization circuits for resetting the various functional circuits
`within the chip. Id. at 1:18–21. According to Lee, conventional
`initialization circuits, called “power on reset circuits,” generate a reset signal
`in response to a power supply voltage being applied to the chip. Id. at 1:22–
`24. Figure 1 of Lee (not reproduced herein) describes one such conventional
`initialization circuit. Id. at 1:30–45, Fig. 1. Lee describes that conventional
`power on reset circuits may malfunction and fail to initialize the circuits
`within the chip if input power supply voltage is unstable. Id. at 2:4–14.
`Against this backdrop, Lee purports to disclose improved initialization
`circuits that reliably initialize a semiconductor memory device in response to
`external logic signals. Id. at 2:18–23.
`
`14
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`Figure 3 of Lee is reproduced below.
`
`
`
`Figure 3 is a schematic diagram of an embodiment of Lee’s initialization
`circuit. Id. at 3:1–3.
`As shown in Figure 3, Lee’s exemplary initialization circuit comprises
`first initialization signal generator 46, second initialization signal
`generator 16, and transfer unit 56. Id. at 3:10–14. According to Lee, second
`initialization signal generator 16, which is “essentially the same” as the
`conventional power on reset circuit of Figure 1, generates a second
`initialization signal ϕINIT in response to the power up of a power supply
`VCC. Id. at 3:17–20. First initialization signal generator 46 generates a first
`initialization signal ϕSET in response to a sequence of reset control signals
`DSF, RASB, and CASB. Id. at 3:14–16. Transfer unit 56 combines the first
`initialization signal ϕSET and the second initialization signal ϕINIT to
`
`15
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`generate a reset Signal ϕRST for resetting the circuits within the memory
`device. Id. at 3:20–23, 4:59–62.
`
`3. Overview of Iketani (Ex. 1007)
`Iketani describes a DRAM device with a power on reset circuit that
`initializes the internal circuitry of the DRAM when the power is turned on.
`Ex. 1007, 1:7–12.
`Figure 6 of Iketani is reproduced below.
`
`Figure 6 is a block diagram showing an example of Iketani’s DRAM for
`which a power on reset circuit is used. Id. at 2:40–41.
`Iketani describes that the DRAM shown in Figure 6 includes memory
`cell array 51, control circuit 62 for controlling internal circuitry, and power
`on reset circuit 20. Id. at 5:4–20. Iketani further describes that power on
`
`
`
`16
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`reset circuit 20 generates a power on reset signal that initializes the DRAM
`circuits, including control circuit 62. Id. at 5:20–26.
`
`4. Independent Claims 1 and 11
`Petitioner presents essentially the same analysis regarding
`independent claims 1 and 11, asserting that the independent claims recite
`similar limitations. See Pet. 58, 61–63. Patent Owner contests Petitioner’s
`showing, addressing claims 1 and 11 together. Prelim. Resp. 32–37. At this
`stage of the proceeding, Patent Owner’s dispute mostly focuses on the
`limitation “the enable signal effecting an unlatching of said control circuit”
`recited in claim 1. See id.
`Because the parties do not dispute, and we agree, that claims 1 and 11
`recite substantially similar limitations, our discussion below focuses on
`claim 1. Unless otherwise noted, our analysis below applies equally to both
`independent claims 1 and 11.
`Figure 3 of Lee as annotated by Petitioner is reproduced below.
`
`17
`
`
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`Pet. 48. Annotated Figure 3 of Lee reproduced above illustrates Petitioner’s
`alleged identification in Lee of certain elements of claim 1. Id. at 48–50.
`Referencing annotated Figure 3 of Lee reproduced above, Petitioner
`asserts that Lee discloses the recited “initialization circuit” (Lee’s circuit
`components 12, 14, 16, 46, and 56, annotated in yellow) for “controlling a
`switching-on operation and supplying a supply voltage stable signal.”
`Pet. 48 (citing Ex. 1003 ¶ 120). Petitioner contends that Lee’s initialization
`circuit controls a switching-on operation (i.e., the process for powering on
`the memory chip) because
`Lee explains that these types of “initialization circuits are
`typically referred to as power on reset circuits and generate a
`reset signal in response to a power supply voltage VCC being
`applied to the [DRAM] chip. The typical power on reset circuit
`operates by sensing the level of the power supply voltage VCC
`and generating an initialization signal for a predetermined length
`of time when the power supply voltage reaches a predetermined
`level.”
`Id. at 48–49 (quoting Ex. 1005, 1:18–29). Petitioner further asserts that the
`ϕINIT signal in Figure 3 of Lee (annotated in green in annotated Figure 3 of
`Lee reproduced above) teaches the recited “supply voltage stable signal”
`because Lee’s ϕINIT signal is generated in response to the power-up of a
`power supply VCC. Id. at 49–50 (citing Ex. 1005, 1:31–34, 1:47–54, 3:9–
`23; Ex. 1003 ¶ 123).
`
`18
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`
`Figure 3 of Lee as annotated and modified by Petitioner is reproduced
`below.
`
`
`
`Pet. 51 (citing Ex. 1003 ¶ 125). Petitioner-modified Figure 3 of Lee
`reproduced above illustrates Petitioner’s contentions regarding Lee’s alleged
`teachings of certain elements of claim 1, including the recited “enable
`circuit,” “enable signal,” and “control circuit.” Id. at 48–58.
`Referencing modified Figure 3 of Lee reproduced above, Petitioner
`asserts that Lee’s first initialization signal generator 46 and transfer unit 56
`(annotated in blue above) disclose “an enable circuit receiving the supply
`voltage stable signal and externally applied further command signals,” as
`recited in claim 1, because Lee’s enable circuit “receives both the supply
`voltage stable signal (shown in green above) and externally applied further
`command signals (shown in brown above).” Pet. 51. Petitioner explains
`that, as shown in Figure 3 of Lee, transfer unit 56 of Lee’s enable circuit
`
`19
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`receives the ϕINIT signal (the claimed “supply voltage stable signal”). Id.
`(citing Ex. 1005, 4:33–35, 4:59–62, Fig. 3).
`Petitioner further contends that the CASB, RASB, and DSF signals
`(annotated in brown in modified Figure 3 of Lee reproduced above), which
`are received by first initialization signal generator 46 of Lee’s enable circuit,
`teach the recited “externally applied further command signals” because a
`person of ordinary skill in the art would have understood that Lee’s CASB,
`RASB, and DSF signals are similar to and related to the PRECHARGE,
`AUTOREFRESH, and MODE-REGISTER-SET commands described in the
`’589 patent as examples of the claimed “externally applied further command
`signals.” Pet. 52–53 (citing Ex. 1001, 2:50–54; Ex. 1005, 3:14–16, 3:37–49;
`Ex. 1003 ¶¶ 127, 128; Ex. 1019, 10). In particular, Petitioner relies on the
`testimony of Dr. Melvin that “the CASB and RASB signals are further
`command signals because a POSITA would have understood that they can
`be used to generate the PRECHARGE, AUTOREFRESH, and MODE-
`REGISTER-SET commands disclosed in the ’589 Patent.” Ex. 1003 ¶ 128.
`In support of his testimony, Dr. Melvin cites to a “TRUTH TABLE” in a
`DRAM specification that describes how the Precharge, Auto Refresh, and
`Mode Register Set commands are related to the CAS and RAS signals. Id.
`(citing Ex. 1019, 10).
`Further, Petitioner asserts that Lee’s reset signal ϕRST (annotated in
`purple above in modified Figure 3 of Lee reproduced above, the claimed
`“enable signal”) output by Lee’s enable circuit teaches “said enable circuit
`outputting an enable signal after a predetermined proper initialization
`sequence of the externally applied further command signals being
`
`20
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`identified,” as recited in claim 1, because Lee describes that the reset signal
`ϕRST is activated only after the CASB, RASB, and DSF signals produce “a
`predetermined bit pattern in the proper sequence.” Pet. 55–56 (citing
`Ex. 1005, 4:38–61).
`Next, Petitioner asserts that a person of ordinary skill in the art would
`have understood that Lee teaches or renders obvious “a control circuit for
`controlling operations” recited in claim 1 because a person of ordinary skill
`in the art would have understood that Lee includes “a control circuit that
`receives external commands and controls the internal operation of the
`memory device so as to properly respond to the commands.” Pet. 54 (citing
`Ex. 1003 ¶ 130). As discussed above, Petitioner contends that Lee’s
`external commands include the CASB and RASB commands, which are
`described in Lee as a “first control signal” and a “second control signal”
`used to control the read operation of the memory device. Id. at 52 (citing
`Ex. 1005, 3:37–49; Ex. 1003 ¶ 127). In the cited paragraph of his
`Declaration, Dr. Melvin states that “CASB is a column address strobe signal
`and RASB is a row address strobe signal,” which are “primarily used to
`instruct the memory chip to activate or open a row and then to read a column
`within the activated row.” Ex. 1003 ¶ 127. Dr. Melvin provides a similar
`explanation in the “Technology Background” section of his Declaration,
`citing a DRAM specification as support. Id. ¶ 53 (citing Exs. 1017, 1018).
`Petitioner further contends that a person of ordinary skill in the art
`would have understood that Lee’s reset signal ϕRST initializes the control
`circuit because Lee discloses that the reset signal initializes “circuit[s] within
`the memory device” or “circuit[s] within the chip.” Pet. 53–55 (citing
`
`21
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`Ex. 1005, 1:20–21 (“[Semiconductor memory] devices require initialization
`circuits for resetting the various functional circuits within the chip.”), 3:19–
`22 (“The transfer unit 56 generates a reset signal ϕRST for resetting a circuit
`within the memory device responsive to the first and second initialization
`signals.”), 4:20–24 (“transfer unit 56 for sending the reset signal ϕRST to a
`circuit to be initialized within the chip”), 4:35–37 (“all circuits within the
`chip which are connected to the output terminal of transfer unit 56 [are] held
`in the initialized state”), 4:59–62 (“The transfer unit 56 . . . activates the
`reset signal ϕRST . . . thereby initializing the circuits within the chip.”),
`5:11–13). Petitioner’s contention is illustrated by Petitioner’s modification
`of Figure 3 of Lee (reproduced above) to add a Control Circuit (in red color)
`that receives the reset signal ϕRST. Id. at 51, 53.
`In the alternative, Petitioner asserts that the combination of Lee and
`Iketani teaches the recited “control circuit.” Pet. 59–63.
`Annotated and modified Figure 6 of Iketani illustrating Petitioner’s
`proposed combination of Lee and Iketani is reproduced below.
`
`22
`
`
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`Pet. 60. The figure reproduced above shows Petitioner’s illustration of the
`proposed combination of Lee and Iketani. Id. at 59–61.
`As illustrated in the Petitioner-modified Figure 6 of Iketani
`reproduced above, in the proposed combination of Lee and Iketani, Lee’s
`initialization circuit replaces Iketani’s power on reset circuit 20, with Lee’s
`reset signal ϕRST providing the initialization signal for Iketani’s control
`circuit. Pet. 59–60. Petitioner contends that a person of ordinary skill in the
`art would have recognized that the initialization circuit of Lee is compatible
`with the controller of Iketani because “[b]oth the power on reset circuit of
`Iketani and the initialization circuit of Lee perform similar functions and are
`used for the same purpose.” Id. (citing Ex. 1005, 2:4–6, 2:18–20; Ex. 1007,
`2:1–4; Ex. 1003 ¶ 140). Citing Iketani’s disclosure that the power on reset
`signal generated by Iketani’s power on reset circuit 20 is supplied to control
`circuit 62 of Iketani, Petitioner asserts that “a POSITA would have
`understood that Lee’s initialization circuit is . . . compatible with Iketani’s
`control circuit.” Id. at 61 (citing Ex. 1007, 5:20–26; Ex. 1003 ¶ 142).
`Petitioner argues that Lee and Iketani expressly provide the
`motivation to combine the references because “[w]hile Lee does expressly
`illustrate the ‘circuitry’ that is initialized by the reset signal ϕRST output
`from its initialization circuit, Iketani illustrates and describes in detail the
`various circuits, including the control circuit, that receive and are initialized
`by such an initialization signal.” Pet. 59 (emphasis added) (citing Ex. 1003
`¶ 140). Petitioner further asserts that the proposed combination “amounts to
`a simple substitution of one component (i.e., Lee’s initialization circuit) for
`another (i.e., Iketani’s power on reset circuit), and a POSITA would have
`
`23
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`
`understood that this substitution would yield predicable results.” Id. at 61
`(citing Ex. 1003 ¶ 143).
`Lastly, Petitioner contends that Lee’s reset signal ϕRST (the claimed
`“enable signal”) teaches “the enable signal effecting an unlatching of said
`control circuit,” as recited in claim 1, because a person of ordinary skill in
`the art would have understood that initialization of the control circuit
`“causes the start of normal operation” of the control circuit. Pet. 57 (citing
`Ex. 1005, 4:13–24, 4:59–5:4; Ex. 1003 ¶ 133). In the combination of Lee
`and Iketani, Petitioner further argues that “the control circuit is unlatched by
`an enable signal through Iketani’s disclosure that the control circuit is
`initialized by the reset signal.” Id. at 63 (citing Ex. 1007, 5:12–26; Ex. 1003
`¶¶ 148, 151).
`In the Preliminary Response, Patent Owner asserts that Lee “contains
`no disclosure that this [reset signal ϕRST] . . . unlatches any control circuit
`for normal operation.” Prelim. Resp. 33. Similarly, Patent Owner argues
`that “[l]ike Lee, the initialization o
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
