`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`SONY GROUP CORPORATION
`
`Petitioner
`
`v.
`
`GREENTHREAD, LLC
`
`(record) Patent Owner
`
` IPR2023-00324
`Patent No. 11,121,222
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.200 ET. SEQ
`
`
`
`
`
`
`
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`TABLE OF CONTENTS
`TABLE OF EXHIBITS ............................................................................................. 4
`NOTICE OF LEAD AND BACKUP COUNSEL ..................................................... 7
`NOTICE OF RELATED MATTERS ........................................................................ 7
`NOTICE OF THE REAL-PARTIES-IN-INTEREST ............................................... 7
`NOTICE OF SERVICE INFORMATION ................................................................ 7
`GROUNDS FOR STANDING .................................................................................. 8
`STATEMENT OF PRECISE RELIEF REQUESTED .............................................. 8
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW ......................... 8
`I.
`INTRODUCTION ........................................................................................... 8
`A.
`Technical Background ........................................................................... 8
`CLAIM CONSTRUCTION ............................................................................ 9
`A.
`Claims 1-38 — “VLSI” ......................................................................... 9
`III. DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY .......................................................................... 9
`Ground 1. Claims 1-38 were obvious over Silverbrook in view of Yamashita ..... 9
`A.
`Effective Prior Art Date of Silverbrook and Yamashita ..................... 10
`B.
`Overview of the Combination ............................................................. 10
`C.
`Rationale (Motivation) Supporting Obviousness ................................ 12
`D. Graham Factors ................................................................................... 15
`E.
`Reasonable Expectation of Success .................................................... 16
`F.
`Analogous Art ..................................................................................... 16
`G.
`Claim Mapping .................................................................................... 17
`
`II.
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`Ground 2. Claims 39-43 were obvious over Yamashita. ..................................... 60
`A.
`Claim Mapping .................................................................................... 60
`Ground 3. Claims 1-43 were obvious over Silverbrook, Yamashita, and Nishi .. 64
`A.
`Effective Prior Art Dates ..................................................................... 64
`B.
`Overview of the Ground ...................................................................... 64
`A.
`Rationale (Motivation) Supporting Obviousness ................................ 67
`B.
`Graham Factors ................................................................................... 71
`C.
`Reasonable Expectation of Success .................................................... 71
`D. Analogous Art ..................................................................................... 72
`E.
`Claim Mapping .................................................................................... 72
`Ground 4. Claim 44 was obvious over Kenney .................................................... 73
`A. Overview and Rationale Supporting Obviousness. ............................. 73
`B.
`Reasonable Expectation of Success .................................................... 73
`C.
`Analogous Art ..................................................................................... 73
`D.
`Claim Mapping. ................................................................................... 74
`IV. DISCRETIONARY INSTITUTION ............................................................. 85
`A.
`The Board should not deny the petition under 35 U.S.C. §325(d) ..... 85
`B.
`The Board should not deny the petition under 35 U.S.C. §314(a) ...... 86
`CONCLUSION .............................................................................................. 89
`V.
`CERTIFICATE OF SERVICE ................................................................................ 90
`CERTIFICATE OF WORD COUNT ...................................................................... 91
`
`
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`Exhibit No.
`1001
`1002
`1003
`1004
`1005
`1006
`
`1007
`
`1008
`1009
`
`1010
`1011
`1012
`
`1013
`
`1014
`
`TABLE OF EXHIBITS
`
`
`Description
`U.S. Patent No. 11,121,222 (“the ’222 patent”).
`Declaration of R. Michael Guidash.
`C.V. of R. Michael Guidash.
`U.S. Pat. No. 6,614,560 (“Silverbrook”).
`U.S. Pat. No. 6,420,763 (“Yamashita”).
`File History of U.S. App. Ser. No. 11/622,496 (issued as U.S. Pat.
`No. 8,421,195).
`File History of U.S. App. Ser. No. 16/947,294 (issued as the
`’222 patent).
`U.S. Pat. No. 4,481,522 (“Jastrzebski”).
`Redline comparisons of claim 1 and claims 21, 39, 41, 42, and
`43 with other independent claims.
`U.S. Pat. Pub. 2004/0063288 A1 (“Kenney”).
`U.S. Pat. Pub. 2001/0032983 A1 (“Miyagawa”).
`Excerpt from Nishi, et al. (eds.) Handbook of Semiconductor
`Manufacturing, Marcel Dekker, Inc., New York (2000)
`(“Nishi”).
`Defendants’ Opening Claim Construction Brief in Greenthread,
`LLC v. Intel Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex.
`Oct. 10, 2022).
`Plaintiffs’ Claim Construction Brief in Greenthread, LLC v. Intel
`Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex. Oct. 31,
`2022).
`
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`1015
`
`1016
`
`1017
`
`1018
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`1025
`1026
`1027
`1028
`
`Complaint in Greenthread, LLC v. Intel Corp., et al., Case No.
`6:22-cv-105-ADA (W.D. Tex. January 27, 2022).
`Amended Complaint in Greenthread, LLC v. Intel Corp., et al.,
`Case No. 6:22-cv-105-ADA (W.D. Tex. April 29, 2022).
`Exhibit 12 from Amended Complaint in Greenthread, LLC v.
`Intel Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex. April
`29, 2022).
`U.S. Pat. App. Pub. 2003/0136982A1 (“Rhodes”).
`Scheduling Order in Greenthread, LLC v. Intel Corp., et al., Case
`No. 6:22-cv-105-ADA (W.D. Tex. May 23, 2022).
`United States District Courts — National Judicial Caseload
`Profile,
`March
`31,
`2022,
`available
`at
`https://www.uscourts.gov/statistics/table/na/federal-court-
`management-statistics/2022/03/31-1
`Scheduling Order in Topia Tech., Inc. v. Box, Inc., et al., Case
`No. 6:21-cv-01372-ADA (W.D. Tex. May 20, 2022).
`Scheduling Order in Parus Holdings, Inc., v. Apple Inc., et al.,
`Case No. 6:21-cv-00968-ADA (W.D. Tex. August 22, 2022).
`Scheduling Order in Lone Star SCM Systems, Ltd. V. Zebra Tech.
`Corp., Case No. 6:21-cv-00842-ADA (W.D. Tex. August 3,
`2022).
`U.S. Pat. No. 6,483,176 (“Noguchi”).
`U.S. Pat. App. Pub. 2003/0063272A1 (“Zaidi”).
`U.S. Pat. App. Pub. 2003/0081463A1 (“Bocian”).
`U.S. Pat. App. Pub. 2003/0098419A1 (“Ji”).
`Screen capture of https://www.bestbuy.com/site/sony-alpha-a7-
`iii-mirrorless-4k-video-camera-body-only-
`black/6213101.p?skuId=6213101
`
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`1029
`
`1030
`
`1031
`
`1032
`
`Excerpt from Pierret, Semiconductor Fundamentals, Vol. I,
`Addison-Wesley Publishing Company, Reading, MA, 1983.
`Excerpt from Grove, Physics and Technology of Semiconductor
`Devices, John Wiley & Sons, 1967.
`Excerpt from Sze, VLSI Technology, McGraw-Hill Book
`Company, 1983.
`Excerpt from Wolf and Tauber, Silicon Processing for the VLSI
`ERA, Lattice Press, Sunset Beach, CA, (2000).
`
`
`
`
`
`
`
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`Petitioner respectfully requests inter partes review under 35 U.S.C. §311 of
`
`claims 1-44 of U.S. Pat. No. 11,121,222 (“the ’222 patent”).
`
`NOTICE OF LEAD AND BACKUP COUNSEL
`Lead Counsel
`Backup Counsel
`Matthew A. Smith
`Andrew S. Baluch
`Reg. No. 49,003
`Reg. No. 57,503
`SMITH BALUCH LLP
`SMITH BALUCH LLP
`700 Pennsylvania Ave. SE, Ste 2060
`700 Pennsylvania Ave. SE, Ste 2060
`Washington, DC 20003
`Washington, DC 20003
`(202) 669-6207
`(202) 880-2397
`smith@smithbaluch.com
`baluch@smithbaluch.com
`
`
`
`
`NOTICE OF RELATED MATTERS
`The ’222 patent has been asserted in Greenthread, LLC v. Intel Corporation
`
`et al, Case No. 6-22-cv-00105 (W.D. Tex.), filed January 27, 2022.
`
`NOTICE OF THE REAL-PARTIES-IN-INTEREST
`The real-parties-in-interest (“RPIs”) are Sony Group Corporation, Sony
`
`Corporation, Sony Semiconductor Solutions Corporation, Sony Semiconductor
`
`Manufacturing Corporation, Sony Taiwan Ltd., Sony Corporation of America, Sony
`
`Electronics Inc., Dell Inc., and Dell Technologies Inc.
`
`NOTICE OF SERVICE INFORMATION
`Please address all correspondence to the lead counsel at the addresses shown
`
`above.
`
`Petitioner
`
`consents
`
`to
`
`electronic
`
`service
`
`by
`
`email
`
`at:
`
`smith@smithbaluch.com, baluch@smithbaluch.com.
`
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`GROUNDS FOR STANDING
`Petitioner hereby certifies that the patent for which review is sought is
`
`available for inter partes review, and that the Petitioner is not barred or estopped
`
`from requesting a inter partes review on the grounds identified in the petition.
`
`STATEMENT OF PRECISE RELIEF REQUESTED
`Petitioner respectfully requests that claims 1-44 of the ’222 patent be canceled
`
`based on the following grounds:
`
`Ground 1: Claims 1-38 were obvious over Silverbrook in view of Yamashita.
`
`Ground 2: Claims 39-43 were obvious over Yamashita.
`
`Ground 3: Claims 1-43 were obvious over Silverbrook, Yamashita, and
`
`Nishi.
`
`Ground 4: Claim 44 was obvious over Kenney.
`
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW
`As shown in the Grounds set forth below, the information presented in the
`
`instant petition, if unrebutted, demonstrates that “it is more likely than not that at
`
`least 1 of the claims challenged in the petition is unpatentable.” 35 U.S.C. § 314(a).
`
`I.
`
`INTRODUCTION
`A. Technical Background
`The ’222 patent relates to semiconductor devices having graded dopant
`
`concentrations. Petitioner’s expert, Mr. Guidash, provides an introduction to the
`
`technology concepts relevant to the ’222 patent. (Ex. 1002, ¶¶24-68).
`
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`II. CLAIM CONSTRUCTION
`“In an inter partes review proceeding, a claim of a patent…shall be construed
`
`using the same claim construction standard that would be used to construe the claim
`
`in a civil action under 35 U.S.C. 282(b), including construing the claim in
`
`accordance with the ordinary and customary meaning of such claim as understood
`
`by one of ordinary skill in the art and the prosecution history pertaining to the
`
`patent.” 37 C.F.R. §42.100(b).
`
`Greenthread LLC and defendants related to Dell and Intel have taken claim
`
`construction positions in the co-pending litigation, as reflected in Exhibits 1013 and
`
`1014.
`
`A. Claims 1-38 — “VLSI”
`The preambles of claims 1-38 use the term “VLSI”. As Mr. Guidash explains,
`
`VLSI stands for “Very Large Scale Integration”, and was typically understood to
`
`describe an integrated circuit with one million active elements, such as transistors.
`
`(Ex. 1002, ¶¶71-72). Greenthread’s prosecution statements in a related application
`
`support this definition. (Ex. 1006, p. 291).
`
`III. DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY
`
`Ground 1. Claims 1-38 were obvious over Silverbrook in view of Yamashita
`
`Claims 1-38 were obvious under 35 U.S.C. §103(a) over U.S. Pat. No.
`
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`6,614,560 (“Silverbrook”)(Ex. 1004) in view of U.S. Pat. No. 6,420,763
`
`(“Yamashita”)(Ex. 1005).
`
`Neither reference was of record during prosecution of the application leading
`
`to the ’222 patent.
`
`A. Effective Prior Art Date of Silverbrook and Yamashita
`Silverbrook is a U.S. patent that issued on September 2, 2003, from an
`
`application filed July 10, 1998, and is thus prior art under pre-AIA 35 U.S.C.
`
`§§102(a) and (e).
`
`Yamashita is a U.S. patent that issued on July 16, 2002, and is thus prior art
`
`under pre-AIA 35 U.S.C. §102(b).
`
`B. Overview of the Combination
`Yamashita teaches semiconductor devices for, e.g., DRAM in integrated
`
`circuits. (Ex. 1005, 1:7-15). Yamashita alone teaches almost all claim elements.
`
`(Ex. 1002, ¶74). This ground is nonetheless presented as one of obviousness for
`
`several reasons. First, Yamashita does not specifically state that its semiconductor
`
`devices are part of VLSI devices (as recited by the preambles of independent claims
`
`1 and 21), nor that its semiconductor devices are used in certain applications—such
`
`as “central processing units”—specified in dependent claims. (Ex. 1002, ¶74).
`
`Silverbrook teaches a VLSI integrated circuit (called an “Image Capture and
`
`Processing Chip” or “ICP”) having DRAM, a CPU, and an image sensor, in which
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`it is appropriate to use Yamashita’s devices. (Ex. 1004, 6:42-55, Fig. 15)(Ex. 1002,
`
`¶74). This Ground posits that it would have been obvious to use Yamashita in a
`
`VLSI DRAM chip for two reasons: (1) it would have been obvious from Yamashita
`
`alone to use Yamashita’s techniques specifically in a VLSI chip and (2) it would
`
`have been obvious to use Yamashita’s techniques in Silverbrook’s ICP.
`
`Second, Yamashita describes retrograde n-wells and retrograde p-wells.
`
`“Retrograde” wells are wells that have a dopant level peak below the surface. (Ex.
`
`1005, Fig. 55, 21:35-41)(Ex. 1002, ¶74). While Yamashita expressly shows a dopant
`
`profile concentration having a graded dopant profile in a retrograde p-well, it does
`
`not illustrate the corresponding graded dopant concentration profile in a retrograde
`
`n-well, which would have been obvious.
`
`Third, Yamashita teaches that graded dopant profiles create potential
`
`gradients that aid carrier movement, and the ability to aid carrier movement in the
`
`specific Eighth Embodiment, on which the Ground relies, would have been obvious.
`
`(Ex. 1002, ¶74).
`
`Finally, this Ground also posits obviousness for certain dependent claims, as
`
`explained in detail in the claim mapping section where appropriate. The Rationale
`
`underpinning other obviousness grounds will be presented in the Claim Mapping
`
`section, under each claim element as appropriate.
`
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`C. Rationale (Motivation) Supporting Obviousness
`It would have been obvious to use Yamashita’s devices in a VLSI integrated
`
`DRAM circuit and in a VLSI circuit like Silverbrook’s ICP. (Ex. 1002, ¶75).
`
`Yamashita teaches semiconductor structures useful for memory (and in
`
`particular, DRAM) having both a logic circuit region and a memory cell region, as
`
`shown with respect to the Eighth Embodiment in Fig. 53, reproduced here:
`
`(Ex. 1005, Fig. 53, 6:1-2, 21:19-34)(Ex. 1002, ¶76). Yamashita states:
`
`“The semiconductor device is divided roughly into an element region
`(a memory cell region) for storing information of large-capacity
`mainly and an element region (a logic circuit region) for executing
`
`
`
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`logical calculations while exchanging information of large-capacity
`with the memory cell region.”
`
`(Ex. 1005, 21:27-33)(Ex. 1002, ¶76).
`
`It would have been obvious from Yamashita alone that it was intended to be
`
`used in a VLSI integrated circuit, because in the relevant timeframe, memory chips
`
`with built-in logic typically had millions of transistors and memory cells, to process
`
`and store large amounts of information. (Ex. 1005, 2:62-67, 21:27-33, 31:27-
`
`32)(Ex. 1002, ¶77).
`
`As an example of this, Silverbrook teaches an Image Capture and Processing
`
`Chip (ICP) that employs DRAM and logic circuitry. (Ex. 1004, 6:42-10:23)(Ex.
`
`1002, ¶78). The layout of the ICP is shown in Silverbrook’s Fig. 15, reproduced
`
`here:
`
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`(Ex. 1004, Fig. 15, 6:42-10:23)(Ex. 1002, ¶78). As seen at the bottom of Fig. 15,
`
`the ICP has DRAM and a logic circuit region for executing logical calculations (e.g.,
`
`the 16 bit ALU 219, the Color ALU 213, and the Convolver 215). (Ex. 1004, 6:46-
`
`48, 7:1-27, 10:9-50)(Ex. 1002, ¶78).
`
`Silverbrook does not teach the low-level semiconductor structure of devices
`
`that form the DRAM and logic devices, but does state that they “can be vendor-
`
`supplied cores” (Ex. 1004, 7:28-30) (Ex. 1002, ¶79). A POSITA would have
`
`understood Silverbrook to be teaching that the exact semiconductor techniques used
`
`for the DRAM and logic circuit can be obtained from other prior art. (Ex. 1002,
`
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`¶79).
`
`A POSITA further would have found it obvious to use the techniques of
`
`Yamashita in Silverbrook. (Ex. 1002, ¶80). Yamashita teaches that its techniques
`
`can be used to achieve the advantages of:
`
`“provid[ing] a semiconductor device having a substrate impurity
`structure that has both soft error resistance and latch up resistance
`and that prevents faulty circuit operation when the semiconductor
`device is formed with a fine structure.”
`
`(Ex. 1005, 3:15-18; see also 23:17-25)(Ex. 1002, ¶80). A POSITA thus would have
`
`found the combination obvious based on the advantages of Yamashita.
`
`A POSITA further would have found the combination obvious because
`
`Silverbrook represents a known type of integrated circuit that required circuitry for
`
`DRAM and logic circuits, and would have been ready for improvement using the
`
`known techniques in a predictable manner. (Ex. 1002, ¶81). See KSR Int’l Co. v.
`
`Teleflex, Inc., 550 U.S. 398, 416-21 (2007).
`
`Other aspects of the Rationale supporting obviousness will be explained
`
`below in the Claim Mapping section, under the claim limitation to which the
`
`obviousness argument pertains.
`
`D. Graham Factors
`The level of ordinary skill encompassed a person having a Bachelor’s Degree
`
`in electrical engineering, microelectronics engineering or a related field and three
`
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`years of experience relating to semiconductor device manufacturing, where a higher
`
`level of education may substitute for experience and vice versa. (Ex. 1002, ¶83).
`
`The scope and content of the prior art are discussed throughout the Ground.
`
`The differences between the prior art and the claims are discussed in the
`
`section entitled “Rationale (Motivation) Supporting Obviousness”, above, and in the
`
`claim mapping, below.
`
`Petitioner is not aware of any secondary considerations that would make an
`
`inference of non-obviousness more likely.
`
`E. Reasonable Expectation of Success
`A person of ordinary skill in the art (“POSITA”) in the relevant timeframe
`
`would have had a reasonable expectation of success in using the prior art in the
`
`manner discussed in this petition. (Ex. 1002, ¶87). As Mr. Guidash explains, the art
`
`was relatively predictable in the relevant timeframe (September 2004). (Ex. 1002,
`
`¶87). A POSITA would have been able to make any necessary modifications to
`
`implement the Ground, and in particular would have been able to use Yamashita’s
`
`techniques in a VLSI device and in Silverbrook, and to adjust doping gradients,
`
`electric fields created by dopant gradients and carrier movement to effect the
`
`purposes of Yamashita. (Ex. 1002, ¶87).
`
`F. Analogous Art
`Silverbrook and Yamashita are analogous art because they are directed to the
`
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`same field as the ’222 patent (semiconductor devices). (Ex. 1001, Title, Abstract,
`
`1:23-30)(Ex. 1004, Title, 1:9-11, 2:10-16)(Ex. 1005, Title, Abstract). Furthermore,
`
`the teachings of Silverbrook and Yamashita would have been reasonably pertinent
`
`to the problems facing the named inventors, including the production of integrated
`
`circuits including CMOS image sensors and memory. (Ex. 1001, 3:36-55)(Ex. 1004,
`
`Title, Fig. 15, 6:41-8:17, 11:14-30)(Ex. 1005, 1:12-3:22)(Ex. 1002, ¶88). See Wyers
`
`v. Master Lock Co., 616 F.3d 1231, 1238 (Fed. Cir. 2010)(“The Supreme Court’s
`
`decision in KSR [cite omitted], directs us to construe the scope of analogous art
`
`broadly….”).
`
`G. Claim Mapping
`This section maps the challenged claims to the relevant disclosures of
`
`Silverbrook and Yamashita, where the claim text appears in bold-italics, and the
`
`relevant mapping follows the claim text. The Petitioner has added numbering and
`
`lettering in brackets (e.g., 1[a], [1b]) to certain claim elements, to facilitate the
`
`discussion.
`
`CLAIM 1
`
`“1[a]. A VLSI semiconductor device, comprising:”
`
`Yamashita alone and the combination with Silverbrook renders obvious a
`
`VLSI semiconductor device. Silverbrook teaches an Image Capture and
`
`Processing Chip or “ICP”. (Ex. 1004, 6:41-60)(Ex. 1002, ¶90). Silverbrook states
`
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`that the ICP is
`
`“a highly integrated system. It combines CMOS image sensing,
`analog to digital conversion, digital image processing, DRAM
`storage, ROM, and miscellaneous control functions in a single chip.”
`
`(Ex. 1004, 6:46-49)(Ex. 1002, ¶90).
`
`The ICP is a VLSI semiconductor device because it is a semiconductor chip
`
`that incorporates millions of transistors. (Ex. 1002, ¶91). For example, the ICP
`
`includes an “imaging array [that] is a CMOS 4 transistor active pixel design with a
`
`resolution of 1,500 x 1,000.” (Ex. 1004, 7:35-37)(Ex. 1002, ¶91). As Mr. Guidash
`
`explains, this means that the ICP has six million transistors in its CMOS image
`
`sensor array alone. (Ex. 1002, ¶91). Furthermore, the ICP includes 12 megabits of
`
`DRAM, which would include one transistor per bit, or approximately 12.5 million
`
`transistors. (Ex. 1004, 7:12, 8:63-67)(Ex. 1002, ¶91).
`
`Furthermore, it would have been obvious to a POSITA in the relevant
`
`timeframe that Yamashita was intended to be used with VLSI DRAM memory
`
`devices, which typically had millions of elements, together with logic circuits
`
`capable of “high-capacity” information exchange with the DRAM. (Ex. 1005,
`
`21:27-32)(Ex. 1002, ¶92).
`
`“[1b] a substrate of a first doping type at a first doping level having
`a surface;”
`
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`Yamashita teaches, and the combination renders obvious, a substrate of a
`
`first doping type at a first doping level having a surface. (Ex. 1002, ¶93).
`
`Yamashita teaches a semiconductor device having a substrate 1, as shown
`
`below in the reproduction of Fig. 53 of Yamashita, with an added, red-dashed box
`
`to show the reference numeral 1 of the substrate:
`
`
`
`(Ex. 1005, Fig. 53, 6:1-2, 21:20-24, 22:19-24, 7:19-21)(Ex. 1002, ¶94).
`
`The substrate 1 is “p type semiconductor substrate 1 containing boron of a
`
`concentration on the order of l x l016 / cm3”. (Ex. 1005, 6:1-2, 21:20-24, 22:19-24,
`
`7:19-21)(Ex. 1002, ¶95). Thus, the substrate is of a first doping type (p-type) at a
`
`first doping level (l x l016 / cm3). (Ex. 1005, 8;13-14)(Ex. 1002, ¶95). The substrate
`
`has a top surface (the top surface of the device shown in Fig. 53), as indicated in the
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`figure. (Ex. 1002, ¶95).
`
`“[1c] a first active region disposed adjacent the surface with a
`second doping type opposite in conductivity to the first doping type
`and within which transistors can be formed;”
`
`Yamashita teaches a first active region disposed adjacent the surface with
`
`a second doping type opposite in conductivity to the first doping type within
`
`which transistors can be formed. First, Yamashita teaches a series of active
`
`regions separated by separation regions:
`
`“As shown in FIG. 57, the field oxide film 24 is formed on the
`separation region on the main surface of the p type semiconductor
`substrate 1 containing boron of concentration on the order of l x l016
`/ cm3, and the oxide film 29 for the gate oxide film 26 is formed
`on the active region.”
`
`(Ex. 1005, 22:33-37)(Emphasis added)(Ex. 1002, ¶96). Figure 57 of Yamashita
`
`(referenced in the quote above) is reproduced below, with the location of the
`
`eventual active regions indicated with added red arrows:
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`(Ex. 1005, 6:9-10, 22:29-39)(Ex. 1002, ¶96). The active regions at this stage in
`
`manufacturing are covered by a thin gate oxide, and separated by thick portions of
`
`field oxide 24. (Ex. 1005, 22:33-37)(Ex. 1002, ¶96). The field oxide has the
`
`function of isolating active regions from one another. (Ex. 1005, 22:33-37)(Ex.
`
`1002, ¶96). The “gate oxide”, after later steps, will become the oxide that separates
`
`gate electrodes from transistor channels in MOSFET transistors. (Ex. 1002, ¶96).
`
`The active regions are disposed adjacent to the top surface of the substrate
`
`1. (Ex. 1005, Fig. 57, 22:33-37)(Ex. 1002, ¶97).
`
`Yamashita teaches that certain active regions will have n-type doping, which
`
`is a second doping type opposite in conductivity to the first doping type (which
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`is p-type, as discussed above under claim limitation [1b]). (Ex. 1005, 23:4-16,
`
`21:55-58, 21:66-22:1, 21:20-24, 22:7-9)(Ex. 1002, ¶98). The first active region
`
`with an n-type doping is indicated by the added red arrow in the reproduction of Fig.
`
`53, reproduced below:
`
`
`
`(Ex. 1005, 21:20-24)(Ex. 1002, ¶98).
`
`The first active region is formed by ion implantation of phosphorous,
`
`producing a “retrograde n well 4” extending from the surface of the semiconductor
`
`to some depth. Yamashita explains:
`
`“As shown in FIG. 63, a resist 43 is formed. The resist 43 has an
`opening portion on a formation region for the PMOSFET in the logic
`circuit region. Phosphorus, which is a source of n type impurity
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`ions, is implanted through the opening portion in the formation
`region by conditions of 300 keV - 2.5 MeV, l x 1012 – l x l014 / cm2,
`and the retrograde n wells 4, 9 are formed.”
`
`(Ex. 1005, 23:4-10)(Emphasis added)(Ex. 1002, ¶99). Figure 63, discussed in the
`
`quote above, is reproduced here:
`
`
`(Ex. 1005, Fig. 63)(Ex. 1002, ¶99). Petitioner notes that in the semiconductor arts,
`
`a substrate typically contains active regions, which can in turn contain or be
`
`contained in wells. (Ex. 1002, ¶99).
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`The first active region is a region within which transistors can be formed.
`
`Fig. 53, reproduced below with added labels and arrows, depicts the source, drain
`
`and channel of a transistor, which meets the claim language under the Patent
`
`Owner’s interpretation (Ex. 1014, p. 33):
`
`
`(Ex. 1005, Fig. 53, 6:1-2, 21:55-58)(Ex. 1002, ¶100). Furthermore, Yamashita
`
`teaches that additional transistors can be formed in this same region:
`
`“A plurality of transistors or a single transistor is formed on the
`retrograde p well 8, the retrograde n well 4 and the retrograde n
`well 9 (not shown), and a CMOS is formed on the logic circuit
`region.”
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`(Ex. 1005, 21:55-58)(Emphasis added)(Ex. 1002, ¶100).
`
`“[1d] a second active region separate from the first active region
`disposed adjacent to the first active region and within which
`transistors can be formed;”
`
`Yamashita teaches a second active region separate from the first active
`
`region disposed adjacent to the first active region within which transistors can be
`
`formed. (Ex. 1002, ¶101). The second active region is shown in Fig. 53, reproduced
`
`below, with an added red arrow showing the second active region:
`
`
`(Ex. 1005, Fig. 53)(Ex. 1002, ¶101). The second active region has a retrograde p
`
`well 8. (Ex. 1005, 21:20-23, 21:55-58, 22:64-23:3, 23:13-14)(Ex. 1002, ¶101).
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`Petitioners note that in the semiconductor arts, a substrate typically contains active
`
`regions, which can in turn contain or be contained in wells. (Ex. 1002, ¶99).
`
`The second active region is separate[d] from the first active region by a
`
`“separation region”, which is comprised of an isolating field oxide layer 24, as
`
`explained above under element [1c]. (Ex. 1005, 22:33-37)(Ex. 1002, ¶102).
`
`Petitioner notes that the ’222 patent also separates active regions by isolation
`
`regions. (e.g., Ex. 1001, claim 6)(Ex. 1002, ¶102).
`
`The second active region is also adjacent to the first active region, as shown
`
`in Fig. 53, above. (Ex. 1002, ¶103). This adjacent nature of the active regions was
`
`also obvious from the disclosure of CMOS logic, as Mr. Guidash explains. (Ex.
`
`1002, ¶103).
`
`Finally, Fig. 53 depicts a transistor formed in the second active region, and
`
`Yamashita teaches that additional transistors can be formed in the second active
`
`region:
`
`“A plurality of transistors or a single transistor is formed on the
`retrograde p well 8, the retrograde n well 4 and the retrograde n
`well 9 (not shown), and a CMOS is formed on the logic circuit
`region.”
`
`(Ex. 1005, 21:55-58)(Emphasis added)(Ex. 1002, ¶104).
`
`“[1e] transistors formed in at least one of the first active region or
`second active region;”
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`As explained above under elements [1c] and [1d], Yamashita teaches that
`
`transistors are formed in both the first and second active regions. (Ex. 1005, Fig. 53,
`
`21:55-58)(Ex. 1002, ¶105).
`
`“[1f] at least a portion of at least one of the first and second active
`regions having at least one graded dopant concentration to aid
`carrier movement from the first and second active regions towards
`an area of the substrate where there are no active regions; and”
`
`Yamashita teaches that both the first and second active regions each have
`
`at least one graded dopant concentration to aid carrier movement from the first
`
`and second active regions towards an area of the substrate where there are no
`
`active regions. Specifically, the first active region contains a retrograde n well 4,
`
`and the second active region contains a retrograde p well 8. (Ex. 1005, 21:19-25,
`
`22:7-9)(Ex. 1002, ¶106). As Mr. Guidash explains, a “retrograde well” is an area of
`
`a semiconductor device that has a dopant concentration peak below the surface of
`
`the device, and thus a graded dopant profile that creates the claimed carrier
`
`movement. (Ex. 1002, ¶106)(Ex. 1018, ¶0045). The ’222 patent admits that:
`
`“As desired, the n-well and p-wells can also be graded or retrograded
`in dopants to sweep those carriers away from the surface as well.”
`
`(Ex. 1001, 3:62-64).
`
`With respect to the second active region (which has a retrograde p well 8),
`
`Yamashita discloses a cross-section in Fig. 54. The cross-section in Fig. 54 is
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`reproduced here:
`
`
`(Ex. 1005, Fig. 54, 6:3-4, 21:19-26)(Ex. 1002, ¶107). In Fig. 54, Yamashita shows,
`
`running through the second active region, a vertical axis C-C’ toward the left-hand
`
`side. Along that axis, there is the dopant (“impurity”) concentration profile shown
`
`in Fig. 55, reproduced here:
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`(Ex. 1005, Fig. 55, 21:35-36, 6:5-6)(Ex. 1002, ¶107). The horizontal axis of Fig. 55
`
`represents the depth from the top