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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_________________________
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`CIRRUS LOGIC, INC. and
`OMNIVISION TECHNOLOGIES, INC.
`Petitioners,
`
`v.
`
`GREENTHREAD, LLC,
`Patent Owner.
`_________________________
`
`Case IPR2024-00018
`U.S. Patent 9,190,502
`_________________________
`
`DECLARATION OF ALEXANDER D. GLEW
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`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`BACKGROUND AND QUALIFICATIONS ................................................. 3
`SCOPE OF ASSIGNMENT AND MATERIALS
`CONSIDERED ................................................................................................ 6
`LEVEL OF ORDINARY SKILL IN THE ART ............................................. 8
`RELEVANT LEGAL PRINCIPLES .............................................................. 9
`A.
`Claim Construction ............................................................................... 9
`B.
`Anticipation ......................................................................................... 11
`C.
`Obviousness ......................................................................................... 11
`THE CHALLENGED PATENT ................................................................... 13
`A.
`Background Technology Regarding Dopants ..................................... 13
`B.
`Overview of Challenged Patent ........................................................... 13
`OVERVIEW OF ALLEGED PRIOR ART .................................................. 18
`A.
`Payne (Ex. 1005) ................................................................................. 18
`B.
`Onoda (Ex. 1042) ................................................................................ 21
`CLAIM CONSTRUCTION .......................................................................... 25
`THE CITED REFERENCES DO NOT DISCLOSE OR
`SUGGEST ALL THE FEATURES OF THE
`CHALLENGED CLAIMS ............................................................................ 26
`Dr. Banerjee’s Payne-based analysis is incorrect
`A.
`regarding the “aid the movement of minority
`carriers” limitations (Elements [7.5]/[7.6]). ........................................ 26
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`B.
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`Dr. Banerjee’s Onoda-based analysis is incorrect
`regarding the “aid the movement of minority
`carriers” limitations (Elements [7.5]/[7.6]). ........................................ 30
`CONCLUSION .............................................................................................. 32
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`I, Alexander D. Glew, declare as follows:
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`
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`INTRODUCTION
` My name is Alexander D. Glew. I have been retained on behalf of
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`Greenthread, LLC (“Greenthread”), and its counsel, McKool Smith, P.C., as an
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`expert with regard to this matter. I understand Cirrus Logic, Inc. (“Cirrus”),
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`OmniVision Technologies, Inc. (“OmniVision”), and ams Sensors USA, Inc.
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`(“ams”) (collectively, “Petitioner”) filed a Petition (Paper No. 1) for inter partes
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`review (IPR) of U.S. Patent No. 9,190,502 (“the ’502 patent” or “the Challenged
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`Patent”) (Ex. 1001).
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`
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`I have been asked to consider, and provide my independent analysis and
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`opinions regarding, whether the alleged prior art references cited in this proceeding
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`disclose or suggest the features recited in claims 7-12 (“the Challenged Claims”) of
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`the Challenged Patent, which I understand Petitioner has challenged in this IPR. In
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`my view, the alleged prior art references do neither. My opinions and conclusions
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`are fully discussed in later sections of this declaration. This declaration is based on
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`the information currently available to me.
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`I am an independent consultant, and I am not, and have never been, an
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`employee of Greenthread or Petitioner. I am being compensated at my consulting
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`rate of $700 per hour for my work related to this matter. I received no compensation
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`for this declaration beyond my normal hourly compensation based on my time
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`actually spent analyzing the Challenged Patent, the prosecution history of the
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`Challenged Patent and related applications, the alleged prior art publications relied
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`upon by Petitioner, the declaration of Petitioner’s expert Dr. Sanjay Banerjee, and
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`other related materials (discussed below in Section III). My compensation is not
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`dependent on the outcome of this IPR or the testimony or opinions that I give.
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`I understand a copy of my curriculum vitae is submitted as Ex. 2061,
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`and it sets forth my educational experience, employment history, and publications.
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` BACKGROUND AND QUALIFICATIONS
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`I earned a B.S. degree in Mechanical Engineering in 1985 and a M.S.
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`degree in Mechanical Engineering in 1987 from the University of California,
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`Berkeley.
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`
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`I earned a M.S. degree in Materials Science and Engineering in 1995
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`and a Ph.D. in Materials Science and Engineering in 2003 from Stanford University.
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`
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`I am the Founder and President of Glew Engineering Consulting, Inc.,
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`based in Mountain View, California. I have been President of Glew Engineering
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`Consulting, Inc. since I started the company in 1997. In my role as President, I have
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`provided consulting services to clients in the field of semiconductor manufacturing
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`and materials, as well as to clients in other fields. I have reviewed and analyzed
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`semiconductor technologies and products. My consulting work has involved
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`semiconductor process equipment, thin film deposition and characterization, process
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`development, project turnaround/rescue, gas flow and vacuum metrology, design of
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`experiments, corrosive gas applications, finite element analysis, and related market
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`analysis.
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`I have over 30 years of experience in semiconductor manufacturing and
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`materials, including in semiconductor equipment and processing. I have
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`implemented numerous manufacturing processes
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`for
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`the
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`formation of
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`semiconductors, including chemical vapor deposition (“CVD”), plasma enhanced
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`chemical vapor deposition (“PECVD”), high density plasma chemical vapor
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`deposition (“HDPCVD”), etch processing (including dry plasma and wet
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`processing), reactive-ion etching (“RIE”), chemical-mechanical planarization
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`(“CMP”), spin-on dielectrics (“SOD”), epitaxy (“EPI”), molecular beam epitaxy
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`(“MBE”), rapid thermal processing (“RTP”), and others.
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`In 1987, before receiving my Ph.D., I worked at Applied Materials, Inc.
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`in Santa Clara, California. At Applied Materials, Inc., I served in a number of roles,
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`including Engineering Manager, Core-Technologist Project Manager, CVD Supplier
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`Quality Engineering Manager, Core Technologist, CVD Engineering Manager, and
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`Systems Engineer. In these roles, I provided engineering services and supervised
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`other employees on projects related to technologies used to manufacture
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`semiconductors, including CVD, epitaxy, physical vapor deposition (“PVD”), rapid
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`thermal processing (“RTP”), etch, and thermal. I oversaw gas, vacuum, and
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`chemical component evaluation, testing, and supplier quality management. I
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`successfully proposed and executed a project to develop industry methods to
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`determine the effects of trace chemicals on semiconductor processing and equipment
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`reliability. I worked on the development and release of the Precision 5000 CVD
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`product, the first cluster tool for semiconductor manufacturing.
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`
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`I have used alpha particles to perform hydrogen forward scattering
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`(HFS) and Rutherford Back Scattering (RBS) in materials analysis of thin films on
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`silicon wafers. I am generally familiar with the effects of alpha particles fired at
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`silicon wafers.
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`I am a licensed professional mechanical engineer in the state of
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`California.
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`I have published articles and presented on topics related to
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`semiconductor manufacturing. My curriculum vitae includes a list of selected
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`publications.
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`I am a co-inventor of five U.S. patents: (a) U.S. Patent No. 6,204,174,
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`directed to a method and apparatus to control the deposition rate of material in a
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`semiconductor fabrication process; (b) U.S. Patent No. 9,224,626 and 10,395,593,
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`directed to a method of forming a heater assembly for use in semiconductor
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`processing; and (c) U.S. Patent Nos. 6,679,476 and 7,118,090, both directed to
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`control valves for use in ultra pure applications such as semiconductor processing.
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`I have another patent application pending.
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`I am a member of the American Society of Mechanical Engineers
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`(“ASME”), International Microelectronics and Packaging Society (“IMAPS”),
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`Materials Research Society (“MRS”), Institute of Electrical and Electronics
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`Engineers (“IEEE”), and Semiconductor Equipment and Materials International
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`(“SEMI”).
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`I am qualified to render an opinion regarding the design and
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`development of semiconductor manufacturing devices and semiconductor materials
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`based on my experience. Based on my expertise and qualifications, I am qualified to
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`provide an opinion as to what a person of ordinary skill in the art would have
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`understood, known, or concluded as of 2004.
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` SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED
` The opinions contained in this declaration are based on the documents
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`that I reviewed, my professional judgment, as well as my education, experience, and
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`knowledge regarding technologies related to the Challenged Patent. In preparing this
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`Declaration, I am relying on my own knowledge and expertise as well as the
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`following documents:
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` The Challenged Patent (Ex. 1001);
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` Other patents that I understand are in the same family as the Challenged
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`Patent, including:
`o U.S. Patent No. 8,421,195 to Dr. G.R. Mohan Rao (“the ’195
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`patent) (Ex. 2062);
`o U.S. Patent No. 10,510,842 to Dr. G.R. Mohan Rao (“the ’842
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`patent”) (Ex. 2063);
`o U.S. Patent No. 11,121,222 to Dr. G.R. Mohan Rao (“the ’222
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`patent”) (Ex. 2064);
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`o U.S. Patent No. 10,734,481 to Dr. G.R. Mohan Rao (“the ’481
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`patent”) (Ex. 2065);
`o U.S. Patent No. 11,316,014 to Dr. G.R. Mohan Rao (“the ’014
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`patent”) (Ex. 2066);
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` Prosecution histories for the Challenged Patent and the other patents in
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`the same family (listed above), which I understand constitute the
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`exchange of correspondence between the Patent Office and the
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`applicant (Ex. 1002; Exs. 2067-2071);
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` Petitioner’s IPR petitions in Nos. IPR2024-00001 (regarding the ’481
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`patent), IPR2024-00016 (regarding the ’842 patent), IPR2024-00017
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`(regarding the ’195 patent), IPR2024-00018 (regarding the ’502
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`patent), IPR2024-00019 (regarding the ’014 patent), and IPR2024-
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`00020 and -00021 (regarding the ’222 patent);
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` Declaration of Dr. Sanjay Banerjee (Ex. 1003), who I understand is
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`Petitioner’s expert in this IPR and the other IPR proceedings listed
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`above (his declaration is Ex. 1003 in each of those IPR proceedings);
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` Petitioner’s exhibits 1001-1018, 1020-1023, 1025-1028, 1030, 1032-
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`1033, 1036-1040, 1042-1043, and 1046-1054 in this IPR; and
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` Any other references/documents cited within this Declaration.
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` LEVEL OF ORDINARY SKILL IN THE ART
` Based on my review of the Challenged Patent, the types of problems
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`encountered in the art at and prior to the time of the alleged invention, prior solutions
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`to those problems, the pace with which innovations were made during the relevant
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`time period, the sophistication of the technology, and the educational level of active
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`professionals in the field, I believe that a person of ordinary skill in the art (POSITA),
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`at the time of the alleged invention, would have had at least a Bachelor’s of Science
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`degree in electrical or computer engineering, materials science, chemical
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`engineering, applied physics, or a related field, with emphasis on semiconductor
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`manufacturing, or an equivalent degree, and at least four years of experience in
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`semiconductor design and manufacturing. Additional education in a relevant field or
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`industry experience may compensate for a deficit in one of the other aspects of the
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`requirements stated above.
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` All of my opinions in this declaration are from the perspective of a
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`POSITA, as I have defined it above and during the relevant time frame (e.g., late
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`2004, including the period up to September 3, 2004, which I understand is the earliest
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`claimed priority date of the Challenged Patent). During this time frame, I possessed
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`at least the qualifications of a POSITA, as defined above.
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` RELEVANT LEGAL PRINCIPLES
` For the purposes of this Declaration, I have been informed about certain
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`aspects of the law that are relevant to my analysis and opinions. I have applied these
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`legal principles in rendering my opinions below.
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`A. Claim Construction
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`I understand that the ordinary and customary meaning of a claim term
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`is the meaning that the term would have to a POSITA at the time of the effective
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`filing date of the patent application that matured into the patent-at-issue. For the
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`Challenged Patent, this is September 3, 2004. In the absence of an express intent on
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`the part of the inventor to give a special meaning to the claim terms, the words are
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`presumed to take on the ordinary and customary meanings attributed to them by a
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`POSITA.
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`I understand that it is the use of the words in the context of the written
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`description, and as customarily used by those skilled in the relevant art, that
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`accurately reflects both the ordinary and the customary meaning of the terms in the
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`claims.
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`I understand that the basis for a term’s ordinary and customary meaning
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`may be derived from a variety of sources, including the words of the claims
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`themselves, the remainder of the specification, the prosecution history, and extrinsic
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`evidence concerning relevant scientific principles, the meaning of technical terms,
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`and the state of the art at the time of the invention.
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`I have been instructed that dictionary definitions or definitions from
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`technical references can be used to inform or confirm the ordinary and customary
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`meaning of words found in a claim, but that in construing claim terms, the general
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`meanings gleaned from reference sources, such as dictionaries, must always be
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`compared against the use of the terms in the context of the claim itself, and the
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`intrinsic record must always be consulted to identify which of the different possible
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`dictionary meanings is most consistent with the use of the words by the inventor.
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`I understand that a patent applicant is entitled to be his or her own
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`lexicographer (in other words, provide his or her own meaning to a word or phrase)
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`and may rebut the presumption that claim terms are to be given their plain and
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`ordinary meaning. To do so, the applicant must clearly set forth a definition of the
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`term that is different from its ordinary and customary meaning.
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` Where the applicant provides an explicit definition for a term, that
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`definition will control interpretation of the term as it is used in the claim in which it
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`appears. I understand that the specification can also be relied on for more than just
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`explicit lexicography to determine the meaning of a claim term. For example, I
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`understand that the meaning of a particular claim term may also be determined by
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`implication, that is, according to the usage of the term in the context of the
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`specification.
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`B. Anticipation
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`I understand that under U.S. Patent Law, 35 U.S.C. § 102, a claim is
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`invalid as anticipated if a single prior art reference discloses each and every
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`limitation of the claimed invention.
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`I am informed that a reference is anticipatory if it contains the claim
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`elements in the same order as claimed, regardless of whether the prior art and the
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`claimed invention are directed to achieving the same purpose.
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`I understand that a prior art reference may anticipate a claim without
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`expressly disclosing a feature of the claimed invention if that missing feature is
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`necessarily present, or inherent, in the single anticipating reference.
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`I am informed that inherency requires more than a probability or
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`possibility that a claimed feature is present in the prior art, but rather that the feature
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`or characteristic is a necessary part of the prior art. I also am informed that
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`recognition of the inherency by a POSITA— at the time— is not required.
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`C. Obviousness
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`I understand that under U.S. Patent Law, 35 U.S.C. § 103, a claim is
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`invalid as obvious if the differences sought to be patented and the prior art are such
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`that the subject matter as a whole would have been obvious at the time the invention
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`was made to a person having ordinary skill in the art to which said subject matter
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`pertains.
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`I am informed that an obviousness analysis requires an assessment of
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`the scope and content of the prior art, the differences between the art and the claims
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`at issue, and the level of ordinary skill in the art. I am told that it is against this
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`backdrop that obviousness is assessed.
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`I am informed that a person of ordinary skill in the art (POSITA) is a
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`hypothetical person who is presumed to be aware of all the pertinent prior art. I am
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`also informed that an obviousness analysis may take account of the inferences and
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`creative steps that a POSITA would employ.
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` THE CHALLENGED PATENT
`A. Background Technology Regarding Dopants
` Silicon is an example of a semiconductor. In its pure form, it is
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`typically an insulator, but it can become an electrical conductor when impurities
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`called “dopants” are added into the silicon crystal. These dopants are often
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`phosphorous or boron atoms that have one more or one less valence electron than a
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`silicon atom. If the dopant has one less valence electron, then it creates what is
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`called a “hole” where there was an electron, which can be thought of as a positive
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`unit of charge. The extra electrons or holes disturb the local charge equilibrium in
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`the silicon and can become mobile in response to electric fields. Thus, the electrons
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`and holes are called “charge carriers.” These dopants can also change the local net
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`electrical charge distribution in the surrounding silicon, influencing the motion of
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`other charge carriers passing by. When the dopant concentration is graded in a
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`particular direction, other charge carriers will move in the gradient direction (or
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`opposite direction) depending on the charge carrier’s polarity. This phenomenon is
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`called “carrier drift.”
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`B. Overview of Challenged Patent
` At the time of invention of the Challenged Patent, most semiconductor
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`devices relied on spatially uniform concentrations of dopants. Ex. 1001 (Challenged
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`Patent), Abstract, 1:40-55. Dr. Rao (the inventor named on the Challenged Patent)
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`recognized, however, that graded concentrations of dopants can be used to improve
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`certain aspects of the performance of transistors and other semiconductor devices.
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`Id., Abstract, 3:7-14, 3:42-44. The claimed invention is clearly disclosed in, e.g.,
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`Figs. 5B-5C of the Challenged Patent, and the corresponding parts of the
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`specification.
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` A surface-channel MOSFET is a common type of transistor capable of
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`controlling current flow at or along the surface of the semiconductor substrate. Ex.
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`2059 (Chen textbook), 27 (“carriers propagate at the semiconductor surface”).
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`Figure 5B shows an NMOS1 transistor that is formed in a p-type surface layer. The
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`transistor comprises (1) a gate; (2) a thin oxide separating the gate from the surface
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`layer; and (3) two doped regions called the source and drain (shaded red). Ex. 1001,
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`3:14-16 (“electrons can be swept from source to drain”), 3:50-52 (“accelerate
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`majority carriers towards the drain”). In Fig. 5B, which is annotated below, the N+
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`means these regions are heavily doped with an n-type dopant that creates a surplus
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`1 MOS stands for “metal oxide semiconductor.”
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`of negative carriers (i.e., electrons).2 The specification explains that the NMOS
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`transistor in Fig. 5B can be a surface-channel MOSFET.
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`
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`Id., Fig. 5B (annotated); see also id., 3:50-52. Meanwhile, the p-type silicon
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`between the source and drain (shaded blue) has an abundance of positively charged
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`holes (green circles). When the holes separate the source’s electrons from the drain’s
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`electrons, current cannot flow through the transistor, and the transistor is in an “off”
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`state.
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` When a positive voltage is applied to the gate, an electric field forms in
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`the oxide. This positive electric field repels the “positive” holes downwards, while
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`2 An “N” region or layer has more electrons, and thus a “negative charge.” A “P”
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`layer has more holes, and a “positive charge.” A “+” or “-” means heavily or lightly
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`doped.
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`the negative electrons (red circles) are attracted to move into the blue surface layer.
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`When enough electrons have accumulated in the surface layer below the oxide, they
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`form a conductive channel (as annotated in Figure 5B below) of electrons between
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`the source and the drain, and current can begin to flow through the transistor.
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`Ex. 1001, FIG. 5B (annotated). 3 In order to turn the transistor “off,” the positive
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`voltage is removed from the gate and the channel disappears as the holes return to
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`the surface layer.
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` Dr. Rao (the inventor named on the Challenged Patent) recognized that
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`by using graded concentrations of dopants in the well region and a drift layer (shaded
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`pink), it is possible to “pull” carriers from the silicon’s surface. Ex. 1001, Fig. 5B
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`3 Because the channel is formed by electrons with a negative charge, the MOSFET
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`is referred to as an n-channel MOSFET, and the “minority carriers” are holes.
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`(annotated above). In this example, pulling the holes from the surface layer when a
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`positive voltage is applied to the gate, allows the transistor to turn “on” more quickly.
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`This improves the speed and performance of the transistor. Ex. 1001, 3:12-17.
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` OVERVIEW OF ALLEGED PRIOR ART
` Dr. Banerjee’s declaration relies on the Payne (Ex. 1005) reference for
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`single-reference obviousness in Ground I, obviousness over Payne in view of
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`Parrillo (Ex. 1025) in Ground IV, obviousness over Payne in view of Wolf (Exs.
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`1008A-1008D) in Ground, V, obviousness over Payne in view of Silverbrook (Ex.
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`1047) in Ground VII, anticipation by Onoda (Ex. 1042 is an English-language
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`translation of the Japanese patent application Ex. 1043) in Ground II, obviousness
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`over Onoda in view of Wolf (Exs. 1008A-1008D) in Ground III, obviousness over
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`Onoda in view of Wolf in Ground VI, and obviousness over Onoda in view of
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`Silverbrook in Ground VIII. Ex. 1003, ¶¶32-38. Below, I provide overviews of
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`relevant portions of Payne and Onoda.
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`A.
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`Payne (Ex. 1005)
` The Petition’s first ground is single-reference obviousness over Payne
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`(Ex. 1005), and Payne is the primary reference in obviousness combinations in the
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`fifth and seventh grounds. Pet., 6. Below is an overview of pertinent portions of
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`Payne relevant to the present dispute.
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` Payne is a patent that “relates to complementary field effect transistors
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`formed by ion implantation, and in particular to a structure and method of fabrication
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`which permit high packing density.” Ex. 1005, 1:5-8. Much of the Petition’s
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`18
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`discussion focuses on Figures 10 and 11 of Payne. Payne describes a CMOS device
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`shown in Figure 10 (shown below):
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`The oxide layer can then be stripped off, for example, with a
`solution of dilute HF, and fabrication may proceed in accordance
`with standard techniques to produce the CMOS device depicted
`in FIG. 10. The p-channel device includes source and drain
`regions, 21 and 22, respectively, of P+ conductivity type formed
`with the N surface region, 18. Similarly, the n-channel device
`includes source and drain regions, 23 and 24, of N + conductivity
`type formed within the P surface region 20.
`Id., 5:18-27.
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`Id., FIG. 10. Figure 10 shows an N- tub 15 and a P- tub 17. Id., 3:35-39 (describing
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`N- tub 15), 4:12-14, 5:3-5 (describing P- tub 17). Payne discloses that after a heating
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`step, “[t]he resulting impurity profile in both tubs thereby has the general shape
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`illustrated in FIG. 11, where the abscissa is depth and the ordinate is impurity
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`concentration.” Id., 5:14-17.
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`Id., FIG. 11; see also id., 2:38-41 (“FIG. 11 is an illustration of the approximate
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`concentration of implanted impurities as a function of depth in the semiconductor
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`for a device in accordance with one embodiment of [Payne].”).
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`B. Onoda (Ex. 1042)
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` The Petition’s second ground relies on Onoda (Ex. 1042) for
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`anticipation, and the third, sixth, and eighth grounds rely on Onoda as the primary
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`reference for an obviousness combination. Pet., 6. Below is an overview of pertinent
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`portions of Onoda relevant to the present dispute.
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` Onoda discloses a nonvolatile semiconductor storage device with a
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`cross-section as shown below in Figure 2.
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`Ex. 1042, FIG. 2.
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` Onoda discloses that:
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`
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`A lightly-doped P-type epitaxial layer 102a is formed on the
`surface of a first semiconductor layer 101 that is made from a
`heavily-doped P-type silicon substrate. Boron [B] is implanted
`into the surface of this epitaxial layer 102a and a heat treatment
`is carried out to produce a lightly-doped P-type second
`semiconductor layer 102. Regions other than a desire region are
`masked, phosphorus is implanted, and a heat treatment is carried
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`out to form an N-type first well region 103. Regions other than
`the desired region are masked, boron [B] is implanted, and the
`boron implantation layer is then masked and phosphorus is
`implanted, and a heat treatment is carried out to form P-type
`second well regions 104a and 104b, P-type third well regions
`105a through 105c, and N-type fourth well regions 106a through
`106c.
`Id., Abstract.
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` Onoda discloses performing carrying out a heat treatment to thermally
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`diffuse the boron and phosphorus of the boron implantation layers 104A, 104B,
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`105A, 105B, and 105C to form, as illustrated below in FIG. 8, P-type second well
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`regions 104a and 140b and P-type third well regions 106a through 106c, and N-type
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`fourth well regions 106a through 106c, in the surface of the second semiconductor
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`layer 102. The dopant concentration due to the boron at this time is depicted by the
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`dotted line D shown in FIG. 9 (below). Id., ¶[0050].
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`Ex. 1042, FIG. 8.
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`Ex. 1042, FIG. 9.
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` Onoda discloses that the dopant profile appearing in the B-B' cross-
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`section in FIG. 8 is shown in FIG. 11 (below). Id., ¶[0052].
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`Ex. 1042, FIG. 11.
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` CLAIM CONSTRUCTION
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`I understand that claim terms are typically given their ordinary and
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`customary meaning, as would have been understood by a person of ordinary skill in
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`the art at the time of the alleged invention. In considering the meaning of the claims,
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`I also understand that one must consider the claim language, specification,
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`prosecution history, and the knowledge of a person of ordinary skill in the art at the
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`relevant time. I understand that Patent Owner is not proposing any claim terms for
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`claim construction. I agree with Patent Owner that none of the terms require
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`construction. I applied the above understanding in my analysis.
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` THE CITED REFERENCES DO NOT DISCLOSE OR SUGGEST ALL
`THE FEATURES OF THE CHALLENGED CLAIMS
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`In my opinion, the prior art references relied upon in the Petition and
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`Dr. Banerjee’s declaration (Ex. 1003) do not disclose or suggest all the features of
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`the Challenged Claims, as I explain below.
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`A. Dr. Banerjee’s Payne-based analysis is incorrect regarding the “aid
`the movement of minority carriers”
`limitations (Elements
`[7.5]/[7.6]).
` Dr. Banerjee stated in his declaration that “Payne renders claim 7
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`obvious.” Ex. 1003, ¶72. I disagree. For elements [7.5] and [7.6], Dr. Banerjee
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`stated in his declaration that “Payne discloses or, at a minimum, renders obvious this
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`element.” Ex. 1003, ¶¶89, 109. I disagree. He did not identify any portion of Payne
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`that actually discloses the “aid the movement of minority carriers…” feature of these
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`claim elements. The “aid the movement of minority carriers” feature appears in the
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`Challenged Claims as follows. Element [7.5]: “said drift layer having a graded
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`concentration of dopants generating a first static unidirectional electric drift field to
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`aid the movement of minority carriers from said surface layer to said substrate”; and
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`Element [7.6]: “at least one well regio
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