`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________________________________________
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`v.
`GREENTHREAD LLC,
`Patent Owner
`
`U.S. PATENT NO. 9,190,502
`Case IPR2024-00018
`
`DECLARATION OF DR. SANJAY BANERJEE IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 9,190,502
`
`
`1 CIRRUS EX. 1003
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`

`
`
`TABLE OF CONTENTS
`BACKGROUND AND QUALIFICATIONS ................................................ 6
`I.
`II. MATERIALS AND OTHER INFORMATION CONSIDERED .................. 9
`III. UNDERSTANDING OF PATENT LAW ................................................... 13
`A.
`Claim Construction ............................................................................ 13
`B. Anticipation and Obviousness ............................................................ 13
`C.
`Cumulativeness .................................................................................. 16
`IV. SUMMARY OF OPINIONS ........................................................................ 17
`V. OVERVIEW OF THE TECHNOLOGY ...................................................... 18
`VI. THE ’502 PATENT ...................................................................................... 21
`A.
`Claims ................................................................................................. 21
`B.
`Summary of the Specification ............................................................ 22
`C.
`Summary of the Prosecution History ................................................. 25
`VII. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 26
`VIII. CLAIM CONSTRUCTION ......................................................................... 27
`IX. OVERVIEW OF THE PRIOR ART ............................................................ 29
`A.
`Payne .................................................................................................. 29
`B. Onoda ................................................................................................. 31
`C. Wolf .................................................................................................... 35
`SPECIFIC GROUNDS FOR PETITION ..................................................... 35
`A. Ground I: ............................................................................................ 35
`1.
`Independent Claim 7 ................................................................ 35
`B. Grounds II and III ............................................................................... 64
`
`X.
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`3.
`
`2.
`
`3.
`
`1.
`2.
`
`Independent Claim 7 ................................................................ 64
`Dependent Claim 8: “The semiconductor device of claim
`7 wherein said first and second static unidirectional
`electric fields are adapted to respective grading of
`dopants to aid movements of carriers in respective active
`regions.” ................................................................................. 104
`Dependent Claim 11: “The semiconductor device of
`claim 7 wherein the semiconductor device is a flash
`memory device.” .................................................................... 107
`C. Ground IV ......................................................................................... 107
`1.
`Dependent Claim 8: “The semiconductor device of claim
`7 wherein said first and second static unidirectional
`electric fields are adapted to respective grading of
`dopants to aid movements of carriers in respective active
`regions.” ................................................................................. 107
`D. Ground V .......................................................................................... 115
`1.
`Dependent Claim 9: “The semiconductor device of claim
`7 wherein
`the semiconductor device
`is a central
`processing unit (CPU).” ......................................................... 115
`Dependent Claim 10: “The semiconductor device of
`claim 7 wherein the semiconductor device is a DRAM
`device.” .................................................................................. 117
`Dependent Claim 11: “The semiconductor device of
`claim 7 wherein the semiconductor device is a flash
`memory device.” .................................................................... 118
`Ground VI ......................................................................................... 120
`1.
`Dependent Claim 9: “The semiconductor device of claim
`7 wherein
`the semiconductor device
`is a central
`processing unit (CPU).” ......................................................... 120
`Dependent Claim 10: “The semiconductor device of
`claim 7 wherein the semiconductor device is a DRAM
`device.” .................................................................................. 123
`
`E.
`
`2.
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`
`F.
`
`3. Motivation to combine Onoda and Wolf ............................... 124
`Ground VII ....................................................................................... 126
`1.
`Dependent Claim 12: “The semiconductor device of
`claim 7 wherein the semiconductor device is an image
`sensor.” ................................................................................... 126
`G. Ground VIII ...................................................................................... 128
`1.
`Dependent Claim 12: “The semiconductor device of
`claim 7 wherein the semiconductor device is an image
`sensor.” ................................................................................... 128
`XI. CUMULATIVENESS ................................................................................ 132
`XII. CONCLUSION ........................................................................................... 135
`
`
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`
`I, Dr. Sanjay Banerjee, declare as follows:
`
`1. My name is Sanjay Banerjee.
`
`2.
`
`I have been retained as an expert witness on behalf of Cirrus Logic,
`
`Inc., OmniVision Technologies, Inc., and ams Sensors USA, Inc. (collectively,
`
`“Petitioner”) for the above-captioned Petition for Inter Partes Review (“Petition”)
`
`of U.S. Patent No. 9,190,502 (the “’502 Patent”) (Ex. 1001). I am being
`
`compensated for my time in connection with this Petition at my standard
`
`consulting rate of $675 per hour. My compensation is not affected by the outcome
`
`of, or my testimony in, this Inter Partes Review, or any litigation proceedings. I
`
`am informed that the assignee for the patent in the present proceeding is
`
`Greenthread, LLC (“Patent Owner”). I am also informed that the Petition names
`
`Cirrus Logic, OmniVision, ams Sensors USA, OSRAM GmbH, ams-OSRAM AG,
`
`and GlobalFoundries U.S., Inc. as real-parties-in-interest.
`
`3.
`
`I have been asked to provide my opinions regarding whether claims 7-
`
`12 of the ’502 Patent (the “Challenged Claims”) are invalid as anticipated, or as
`
`obvious to a person having ordinary skill in the art at the time of the alleged
`
`invention. In connection with this effort, I have reviewed a declaration provided in
`
`connection with another Inter Partes Review Petition filed against the ’502 Patent
`
`(specifically, Ex. 1003 in IPR2023-00541 filed on behalf of Petitioner Intel
`
`Corporation). After having conducted my own independent analysis on the ’502
`
`5 CIRRUS EX. 1003
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`
`
`Patent, I concur with the analysis provided in that declaration. For efficiency, I
`
`have excerpted portions of that declaration in drafting this declaration.
`
`4.
`
`The ’502 Patent issued on November 17, 2015, from Application No.
`
`14/515,584, filed on October 16, 2014. The ’502 Patent claims priority to
`
`Application No. 10/934,915, filed on September 3, 2004.
`
`5.
`
`I am not currently, and have not at any time in the past been, an
`
`employee of any Petitioner or Real-party-in-interest. Other than set out above, I
`
`have no affiliation, contractual connection, or financial connection with any
`
`Petitioner or Real-party-in-interest, or any of their respective subsidiaries or
`
`parents. I similarly have no financial interest in, or affiliation with the Patent
`
`Owner.
`
`I.
`
`BACKGROUND AND QUALIFICATIONS
`
`6.
`
`I am currently the Cockrell Family Chair Professor of Electrical and
`
`Computer Engineering at the University of Texas at Austin. At UT Austin, I am
`
`also the director of the Microelectronics Research Center. I have been a faculty
`
`member at UT Austin since 1987.
`
`7.
`
`I have also been active in industries related to the relevant field of art.
`
`As a Member of the Technical Staff, Corporate Research, Development and
`
`Engineering of Texas Instruments Incorporated from 1983–1987, I worked on
`
`polysilicon transistors and dynamic random access trench memory cells used by
`
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`Texas Instruments in the world’s first 4-Megabit DRAM, for which I was co-
`
`recipient of the Best Paper Award, IEEE International Solid State Circuits
`
`Conference, 1986.
`
`8.
`
`I received a B. Tech. degree from the Indian Institute of Technology,
`
`Kharagpur, and M.S. and Ph.D. degrees from the University of Illinois at Urbana-
`
`Champaign, all in Electrical Engineering.
`
`9.
`
`I am a leading researcher and educator in various areas of transistor
`
`device fabrication technology, including the fabrication, characterization and
`
`application of memory devices, transistors, and nanotechnology. My research has
`
`been funded by the Texas Advanced Technology Program (ATP), the Texas
`
`Higher Education Coordinating Board, the National Science Foundation, the
`
`SEMATECH (Semiconductor Manufacturing Technology) consortium, the SRC
`
`(Semiconductor Research Corporation) consortium, DARPA, and the Department
`
`of Energy, among others.
`
`10. At the University of Texas, I am the director of the Microelectronics
`
`Research Center, comprised of faculty colleagues, graduate, and undergraduate
`
`students. I also served as the director of the South West Academy of
`
`Nanoelectronics from its inception through the end (Dec. 2017), one of three
`
`centers in the United States established to develop a replacement for MOSFETs.
`
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`11.
`
`I have published over 1,200 technical articles, many related to
`
`semiconductor fabrication technology, most at highly competitive refereed
`
`conferences and rigorously reviewed journals. I have also published 8 books or
`
`chapters on transistor device physics and fabrication, and have supervised over 50
`
`Ph.D. and 60 MS students.
`
`12.
`
`I have been a member of scientific organizations and committees,
`
`including the IEEE Dan Noble Award Committee from 2010–2013, serving as
`
`Chair
`
`from 2012–2013,
`
`the
`
`International Technology Roadmap
`
`for
`
`Semiconductors, the International Conference on MEMS (Microelectromechanical
`
`Systems) and Nanotechnology,
`
`the
`
`IEEE
`
`International Conference on
`
`Communications, Computers, Devices, the International Electron Devices Meeting,
`
`the International Conference on Simulation of Semiconductor Processes and
`
`Devices, and the IEEE Symposium on VLSI (Very-Large-Scale Integration)
`
`Technology. I have served as the Session Chair for the “Device Technology”
`
`Session conducted at the IEEE International Electron Devices Meeting in 1989–
`
`1990. I have also served as the General Chairman for the IEEE University
`
`Government Industry Microelectronics Symposium in 1994–1995, and Chair of the
`
`IEEE Device Research Conference.
`
`13.
`
`I have served on the Technical Advisory Boards of AstroWatt, DSM
`
`Semiconductors, Cambrios, Nanocoolers Inc., BeSang Memories, Organic ID and
`
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`
`
`ITU Ventures; Gerson Lehmann Group, NY; Austin Community College; Asia
`
`Pacific IIT; Rochester Institute of Technology, and HSMC Foundry.
`
`14.
`
`I received the Engineering Foundation Advisory Council Halliburton
`
`Award (1991), the Texas Atomic Energy Fellowship (1990–1997), Cullen
`
`Professorship (1997–2001) and the Hocott Research Award from UT Austin
`
`(2007). I also received the IEEE Grove Award (2014), Distinguished Alumnus
`
`Award, IIT (2005), Industrial R&D 100 Award (2004), ECS Callinan Award, 2003,
`
`IEEE Millennium Medal, 2000, NSF Presidential Young Investigator Award in
`
`1988, and several SRC Inventor Recognition and Best Paper Awards. I was a
`
`Distinguished Lecturer for IEEE Electron Devices Society, and am a Fellow of the
`
`Institute of the Electrical and Electronics Engineers (IEEE), the American Physical
`
`Society (APS) and the American Association for the Advancement of Science
`
`(AAAS).
`
`15.
`
`I am the inventor or co-inventor of over 35 United States patents in
`
`various areas of transistor device fabrication technology. I was elected a Fellow of
`
`the National Academy of Inventors in 2021.
`
`16. My qualifications and publications are set forth more fully in my
`
`curriculum vitae, attached as Ex. 1004.
`
`II. MATERIALS AND OTHER INFORMATION CONSIDERED
`
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`
`
`17.
`
`In forming the opinions expressed in this Declaration, I relied upon
`
`my education and experience in the relevant field of the art and have considered
`
`the viewpoint of a person having ordinary skill in the art (POSITA) at the time of
`
`the alleged invention.
`
`18.
`
`I have considered the materials referenced herein, including the ’502
`
`Patent (Ex. 1001), the file history of the ’502 Patent (Ex. 1002), the parent and
`
`related applications, the file histories of the parent and related applications, the
`
`Petition, and other documents listed in the Exhibit List of the Petition, including:
`
`to
`
`to
`
`Description
`U.S. Patent No. 4,684,971
`Payne (“Payne”) (Ex. 1005)
`U.S. Patent No. 4,907,058
`Sakai (“Sakai”) (Ex. 1006)
`to
`U.S. Patent No. 6,043,114
`Kawagoe, et al. (“Kawagoe”) (Ex.
`1007)
`Tauber,
`and
`Wolf
`Silicon
`Processing For The VLSI Era,
`Vol 1, Lattice Press
`(2000)
`(“Wolf.1”) (Ex. 1008A)
`Wolf
`and
`Tauber,
`Silicon
`Processing For The VLSI Era,
`Vol. 2, Lattice Press
`(2000)
`(“Wolf.2”) (Ex. 1008B)
`Wolf and
` Tauber, Silicon
`Processing For The VLSI Era,
`Vol. 3, Lattice Press
`(2000)
`(“Wolf.3”) (Ex. 1008C)
`
`Date of Public Availability
`Filed March 13, 1981 and issued
`August 4, 1987.
`Filed July 1, 1988 (with priority to
`July 3, 1987) and issued on March
`6, 1990.
`Filed on September 22, 1997 (with
`priority to July 28, 1995) and
`issued on March 28, 2000.
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
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`

`
`
`Published and publicly available no
`later than 2002.
`
`Filed November 25, 1977 and
`issued July 10, 1979.
`
`Filed March 24, 1982 and issued
`on November 6, 1984.
`Filed on August 30, 2001.
`
`Filed on October 24, 2001 (with
`priority to October 26, 2000).
`
`Published and publicly available
`in 2008.
`
`Published and publicly available
`in 2004.
`
`Published and publicly available
`in 1988.
`
`Filed on June 29, 1983 (with
`priority to December 7, 1981) and
`issued on March 13, 1984.
`Published and publicly available
`in 1980.
`
`Filed on August 31, 2005.
`
` Tauber, Silicon
`Wolf and
`Processing For The VLSI Era,
`Vol. 4, Lattice Press
`(2000)
`(“Wolf.4”) (Ex. 1008D)
`to
`U.S. Patent No. 4,160,985
`Kamins et al. (“Kamins”) (Ex.
`1009)
`U.S. Patent No. 4,014,522
`(“Jastrzebski”) (Ex. 1010)
`U.S.
`Patent
`Application
`Publication No. 2003/0042511
`(“Rhodes”) (Ex. 1011)
`U.S.
`Patent
`Application
`Publication No. 2002/0102783
`(“Fujimoto”) (Ex.
`1012)
`Wang and Agrawal, Single Event
`Upset: An Embedded Tutorial,
`21st Intl Conf on VLSI Design,
`IEEE 2008 (“Wang”) (Ex. 1013)
`U.S.
`Patent
`Application
`Publication No. 2004/0063288
`(“Kenney”) (Ex. 1022)
`Jaeger,
`to
`Introduction
`Microelectronic Fabrication, Vol.
`V, Addison-Wesley Modular
`Series on Solid State Devices
`(1988) (“Jaeger”) (Ex. 1023)
`U.S.
`Patent No.
`4,435,896
`(“Parrillo”) (Ex. 1025)
`L.C. Parrillo, R.S. Payne et al.,
`Twin-Tub CMOS - A Technology
`for VLSI Circuits, IEEE 1980
`(“Parrillo2”) (Ex. 1026)
`U.S.
`Patent
`Application
`Publication No. 2007/0045682 to
`Hong et al. (“Hong”) (Ex. 1027)
`
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`
`Published and publicly available
`in 1996.
`
`Filed on October 29, 2002 (with
`priority to March 28, 2002).
`
`Published and publicly available
`in 2003.
`
`Date of application April 7, 1995
`and publication date October 22,
`1996.
`
`Filed July 10, 1998 and issued
`September 2, 2003.
`
`Filed June 24, 1998 (with priority
`to June 25, 1997) and issued
`November 16, 1999.
`Published and publicly available
`in 2003.
`
`Published and publicly available
`in 2002.
`
`Published and publicly available
`in 1992.
`
`The Oxford American Dictionary
`and Language Guide, Oxford
`University Press
`(1996)
`(Ex.
`1028)
`Application
`Patent
`U.S.
`Publication No. 2003/0183856 to
`Wieczorek
`(“Wieczorek”)
`(Ex.
`1038)
`and
`Dictionary of Scientific
`Technical Terms, McGraw Hill
`(2003) (Ex. 1040)
`Patent
`Japanese Unexamined
`Application Publication No. H8-
`279598 (“Onoda”) (Ex. 1043,
`certified translation Ex. 1042)
`to
`U.S. Patent No. 6,614,560
`Silverbrook (“Silverbrook”) (Ex.
`1047)
`
`Patent No.
`U.S.
`(“Yamada”) (Ex. 1049)
`
`5,986,924
`
`Rabaey et al., Digital Integrated
`Circuits, A Design Perspective,
`Prentice Hall Electronics and
`VLSI Series (2003) (“Rabaey”)
`(Ex. 1050)
`Sze,
`Semiconductor Devices
`Physics and Technology, 2d Ed.,
`John Wiley & Sons (2002) (Ex.
`1051)
`and Hayes, Layout
`Maziasz
`Minimization of CMOS Cells,
`Kluwer Academic Publishers
`(1992) (“Maziasz”) (Ex. 1054)
`
`
`
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`
`
`19. The references listed above include prior art to the ’502 Patent which
`
`is entitled to a priority date not earlier than September 3, 2004. I am also relying
`
`on the declaration of Dr. Sylvia Hall-Ellis who opined that the Wolf reference was
`
`publicly available before September 3, 2004. Payne, Onoda and Wolf.1-4 (Exs.
`
`1008A-D) were not cited during the prosecution of the ’502 Patent.
`
`III. UNDERSTANDING OF PATENT LAW
`
`20.
`
`I am not an attorney. For purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as listed below.
`
`A. Claim Construction
`I understand that in an IPR petition filed after November 13, 2018, a
`21.
`
`claim must be construed under the Phillips standard. Under that standard, words of
`
`a claim are given their plain and ordinary meaning as understood by a POSITA at
`
`the time of invention, in light of the specification and prosecution history, unless
`
`those sources show an intent to depart from such meaning, as well as pertinent
`
`evidence extrinsic to the patent.
`
`B. Anticipation and Obviousness
`I have been informed that a patent claim is anticipated if a single prior
`22.
`
`art reference, such as a patent or a publication, discloses all the elements of the
`
`claimed invention.
`
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`
`23.
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a POSITA at the time the application was filed.
`
`This means that, even if all of the requirements of a claim are not found in a single
`
`prior art reference, the claim is not patentable if the differences between the subject
`
`matter in the prior art and the subject matter in the claim would have been obvious
`
`to a POSITA at the time the application was filed. I have been informed and
`
`understand that a determination of whether a claim would have been obvious
`
`should be based upon several factors, including, among others:
`
`• the level of ordinary skill in the art at the time the application was filed;
`
`• the scope and content of the prior art; and
`
`• what differences, if any, existed between the claimed invention and the
`prior art.
`I have been informed and understand that the teachings of two or
`24.
`
`more references may be combined in the same way as disclosed in the claims, if
`
`such a combination would have been obvious to a POSITA. In determining
`
`whether a combination based on either a single reference or multiple references
`
`would have been obvious, it is appropriate to consider at least the following
`
`factors:
`
`• whether the teachings of the prior art references disclose known concepts
`combined in familiar ways, which, when combined, would yield
`predictable results;
`
`14 CIRRUS EX. 1003
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`

`
`
`• whether a POSITA could implement a predictable variation, and would
`see the benefit of doing so;
`
`• whether the claimed elements represent one of a limited number of
`known design choices, and would have a reasonable expectation of
`success by a POSITA;
`
`• whether a POSITA would have recognized a reason to combine known
`elements in the manner described in the claim;
`
`• whether there is some teaching or suggestion in the prior art to make the
`modification or combination of elements claimed in the patent; and
`
`• whether the innovation applies a known technique that had been used to
`improve a similar device or method in a similar way.
`I understand that a POSITA has ordinary creativity, and is not an
`25.
`
`automaton.
`
`26.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`27.
`
`I understand that prior art to the ’502 Patent includes patents and
`
`printed publications in the relevant art that predate the Priority Date of the ’502
`
`Patent.
`
`28.
`
`I understand
`
`that certain
`
`factors—often called “secondary
`
`considerations”—may support or rebut an assertion of obviousness of a claim. I
`
`understand that such secondary considerations include, among other things,
`
`commercial success of the alleged invention, skepticism of those having ordinary
`
`skill in the art at the time of the alleged invention, unexpected results of the alleged
`
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`

`

`
`
`invention, any long-felt but unsolved need in the art that was satisfied by the
`
`alleged invention, the failure of others to make the alleged invention, praise of the
`
`alleged invention by those having ordinary skill in the art, and copying of the
`
`alleged invention by others in the field.
`
`29.
`
`I further understand that there must be a nexus—a connection—
`
`between any such secondary considerations and the alleged invention. I also
`
`understand that contemporaneous and independent invention by others is a
`
`secondary consideration tending to show obviousness.
`
`C. Cumulativeness
`I understand that, under 35 U.S.C. § 325(d), the Board may exercise
`30.
`
`its discretion to deny institution of inter partes review if the IPR petition presents
`
`the same or substantially the same prior art or arguments that were previously
`
`presented to the Patent Office.
`
`31. When deciding whether to exercise its discretion to deny institution
`
`under 35 U.S.C. § 325(d), I understand the Board weighs several non-exclusive
`
`factors, including:
`
`(a)
`
`the similarities and material differences between the asserted art
`
`and the prior art involved during examination;
`
`(b)
`
`the cumulative nature of the asserted art and the prior art
`
`evaluated during examination;
`
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`
`
`(c)
`
`the extent to which the asserted art was evaluated during
`
`examination, including whether the prior art was the basis for
`
`rejection;
`
`(d)
`
`the extent of the overlap between the arguments made during
`
`examination and the manner in which Petitioner relies on the
`
`prior art or Patent Owner distinguishes the prior art;
`
`(e) whether Petitioner has pointed out sufficiently how the
`
`Examiner erred in its evaluation of the asserted prior art; and
`
`(f)
`
`the extent to which additional evidence and facts presented in
`
`the Petition warrant reconsideration of the prior art or
`
`arguments.
`
`IV. SUMMARY OF OPINIONS
`
`32.
`
`It is my opinion that claim 7 is disclosed or, at a minimum, rendered
`
`obvious by Payne (Ground I).
`
`33.
`
`It is my opinion that claims 7, 8, and 11 are anticipated by Onoda
`
`(Ground II) or rendered obvious by Onoda (Ground III).
`
`34.
`
`It is my opinion that claim 8 is rendered obvious by Payne in
`
`combination with Parrillo (Ground IV).
`
`35.
`
`It is my opinion that claims 9-11 are rendered obvious by Payne in
`
`view of Wolf (Ground V).
`
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`

`
`
`36.
`
`It is my opinion that claims 9 and 10 are rendered obvious by Onoda
`
`in view of Wolf (Ground VI).
`
`37.
`
`It is my opinion that claim 12 is rendered obvious by Payne in
`
`combination with Silverbrook (Ground VII).
`
`38.
`
`It is my opinion that claim 12 is rendered obvious by Onoda in
`
`combination with Silverbrook (Ground VIII).
`
`39.
`
`It is my opinion that none of the prior art references relied on in this
`
`petition are cumulative with prior art considered by the Examiner during
`
`prosecution of the ’502 Patent.
`
`40.
`
`It is my opinion that for purposes of this proceeding, the claim terms
`
`need not be construed to resolve the prior art issues presented in this Petition.
`
`V. OVERVIEW OF THE TECHNOLOGY
`
`41. A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is
`
`a transistor that switches from an OFF state to an ON state when a voltage is
`
`applied to a gate terminal. Ex. 1008B, 402. In the ON, or active state, current
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`flows from a source to a drain through a channel region (the length of such channel
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`region is labelled “L” below). The channel region is under the gate and gate oxide,
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`and between the source and drain.
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`Ex. 1008B, FIG. 5-1 (annotations in red); 1 id., 298-301, FIGS. 5-2, 6-4. The
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`combination of the source, drain, and channel regions of a transistor may be an
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`example of an active region, as Wolf teaches. Ex. 1008B, 299-300 (“The top
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`surface of the [substrate] body consists of active or transistor regions as well as
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`passive or (field) regions. The active regions are those in which transistor action
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`occurs; i.e., the channel and the heavily doped source and drain regions.”), FIG. 5-
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`2, 382, FIG. 6-8(c), 387, FIG. 6-10; Ex. 1008C, 525, FIG. 8-1(e).
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`42. MOSFETs are characterized by the material used in the source and
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`drain. A MOSFET with source/drain regions made from “p-type” material in such
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`areas (as shown in the figure above, labelled “p+”) is known as a PMOS or p-FET,
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`while a MOSFET with source/drain regions made from “n-type” material (“n+”) in
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`1 All emphases and annotations added unless otherwise noted.
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`such areas is known as a NMOS or n-FET. In the mid-1980s, Complementary
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`MOS (CMOS) devices became popular, which have both PMOS (p-FET) and
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`NMOS (n-FET) transistors on the same substrate or integrated circuits (ICs). In
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`such devices, the active areas (and associated transistors) are generally formed in
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`regions called “wells.” Impurities known as “dopants” are added to the active areas
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`and wells to add charge carriers and tailor the electrical properties of these regions
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`such as their conductivity. The wells have opposite dopant type to the dopants of
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`the source/drain. As illustrated below, an n-FET is formed in a p-well, and a p-FET
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`is formed in an n-well.
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`
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`Ex. 1008A, FIG. 16-28 (annotations in red).
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`43. With respect to dopants, charge carriers can be electrons (which are
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`negatively charged) or holes (which are positively charged). Ex. 1008C, 86.
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`When a region is doped with p-type dopants, the holes are majority carriers and the
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`electrons are minority carriers. Ex. 1008C, 86. When a region is doped with n-
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`type dopants, the electrons are majority carriers and the holes are minority carriers.
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`Ex. 1008C, 86.
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`44. A “dopant profile” refers to the “map” of concentration of dopants
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`over a doped region and, in certain simplified scenarios, can be expressed as a
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`function of depth. For example, a dopant concentration that does not change with
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`depth is a uniform concentration. A non-uniform dopant concentration that varies
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`for example with depth, e.g., increases or decreases with depth, is a non-uniform
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`dopant concentration called “graded.” A graded dopant concentration that peaks at
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`some depth of the doped region(s) instead of at the top or bottom of the doped
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`region(s) is called “retrograde.” In my opinion, all such doping profiles were
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`known in the art.
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`VI. THE ’502 PATENT
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`45. The ’502 Patent issued on November 17, 2015, from Application No.
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`14/515,584, filed on October 16, 2014. The ’502 Patent claims priority to
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`Application No. 10/934,915, filed on September 3, 2004. Ex. 1001, cover.
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`A. Claims
`46. The ’502 Patent has 12 claims, including two independent claims
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`numbered 1 and 7. Ex. 1001, 4:23-5:12. Claims 7-12 are the Challenged Claims.
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`47. Exemplary Claim 7 is reproduced below:
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`7. A semiconductor device comprising:
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`a surface layer;
`a substrate;
`an active region including a source and a drain, disposed on one
`surface of said surface layer;
`a single drift layer disposed between the other surface of said surface
`layer and said substrate, said drift layer having a graded concentration
`of dopants generating a first static unidirectional electric drift field to
`aid the movement of minority carriers from said surface layer to said
`substrate; and
`at least one well region disposed in said single drift layer, said well
`region having a graded concentration of dopants generating a second
`static unidirectional electric drift field to aid the movement of
`minority carriers from said surface layer to said substrate.
`Ex. 1001, 4:24-39.
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`Summary of the Specification
`B.
`48. The ’502 Patent is directed to “grading the dopant concentration” in
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`certain regions of a semiconductor device. Ex. 1001, Title, Abstract. The
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`Challenged Claims claim that a single drift layer and a well region of a
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`semiconductor device have graded dopant concentrations to aid movement of
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`minority carriers from the surface layer to the substrate. Id., Cl. 7. I understand
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`that those claims are asserted against CMOS products in Greenthread, LLC v.
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`Cirrus Logic, Inc., 1:23-cv-00369 (W.D. Tex., filed March 31, 2023), Greenthread,
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`LLC v. OSRAM GmbH, 2:23-cv-00179 (E.D. Tex., filed Apr. 19, 2023), and
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`Greenthread, LLC v. OmniVision Technologies, Inc., 2:23-cv-00212 (E.D. Tex.,
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`filed May 10, 2023) (collectively, “District Court Cases”). In my opinion, a
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`majority of the references relied on in the Petition (i.e., Payne, Onoda and Wolf)
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`are also directed to CMOS devices and technology.
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`49. A bipolar junction transistor (BJT) is a type of transistor that, unlike a
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`FET, uses both electrons and holes as charge carriers. See, e.g., Ex. 1001, 1:27-50.
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`The ’502 Patent admits that graded dopant concentrations were known. For
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`example, the graded dopant concentration “B” (green) in Figure 1 below is
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`described as one of “the two most popular” doping profiles used in prior art bipolar
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`transistors, in contrast to the uniform doping profile “A” (red). Ex. 1001, 2:17-19.
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`Id., FIG. 1 (“Prior Art”).2 The ’502 Patent further admits that it was known to
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`grade the dopant concentration in well regions of CMOS devices to affect the
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`movement of carriers, but alleges, without support, that prior attempts were met
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`with “little success.” Id., 1:38-2:9.
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`50. The ’502 Patent explains that “[r]etrograde wells have been attempted,
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`with little success, to help improve soft error immunity in SRAMs and visual
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`quality in imaging circuits.” Ex. 1001, 1:63-65. The ’502 Patent further states that
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`“[r]etrograde and halo wells have also been attempted to im