(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2003/0097503A1
`Huckins
`(43) Pub. Date:
`May 22, 2003
`
`US 20030097503A1
`
`(54) PCI COMPATIBLE BUS MODEL FOR
`NON-PC COMPATIBLE BUS
`ARCHITECTURES
`(76) Inventor: Jeffrey L. Huckins, Chandler, AZ (US)
`Correspondence Address:
`BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
`LLP
`Seventh Floor
`12400 Wilshire Boulevard
`Los Angeles, CA 90025-1026 (US)
`(21) Appl. No.:
`09/989,475
`(22) Filed:
`Nov. 19, 2001
`Publication Classification
`
`(51) Int. Cl." ..................................................... G06F 13/00
`
`(52) U.S. Cl. .............................................................. 710/104
`
`(57)
`
`ABSTRACT
`
`A method for a Peripheral Component Interconnect (PCI)
`compatible bus model for non-PCI compatible bus architec
`tures. The method of one embodiment comprises identifying
`a hardware controller coupled to a PCI compatible bus, the
`hardware controller compatible to a PCI bus protocol and to
`a non-PCI bus protocol. The hardware controller is initial
`ized. A non-PCI compatible bus coupled to the hardware
`controller is searched for a non-PCI compatible device, the
`non-PCI compatible device compatible to the non-PCI bus
`protocol. The non-PCI compatible device is configured. The
`non-PCI compatible device is recognized as a PCI compat
`ible device coupled to said PCI compatible bus.
`
`PROCESSOR
`102
`
`CACHE
`104.
`
`
`
`PROCESSOR BUS
`
`110
`
`
`
`GRAPHCS,
`WDEO
`CARD
`
`112
`
`MEMORY
`CONTROLLER
`UE
`
`MEMORY
`INSTRUCTION
`
`DATA
`
`120
`
`DATA
`stóAGE KF)
`124
`
`USER
`NPUT
`
`KEYBOARD :
`: INTERFACE :
`
`FLASH BIOS KEX
`128
`
`FO
`CONTROLLER
`HUB
`
`SERAL EXPANSION
`PORT
`
`AUDIO
`coACLER KR)
`
`
`
`
`
`1OO
`
`NETWORK
`CONTROLLER
`134
`
`NON-PCBUS
`CONTROLLER
`126
`
`132
`
`NON-PCI DEVICE
`33
`
`Lenovo
`Ex. 1007 - Page 1
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`

`

`Patent Application Publication May 22, 2003 Sheet 1 of 7
`
`US 2003/0097503 A1
`
`PROCESSOR
`
`102
`
`CACHE
`
`FIG. 1
`
`
`
`
`
`
`
`
`
`PROCESSOR BUS
`
`110
`
`GRAPHICS/
`VIDEO
`CARD
`
`112
`
`MEMORY
`CONTROLLER
`HUB
`
`MEMORY
`NSTRUCTION
`
`DATA
`
`
`
`DATA
`STORAGE
`124
`
`; : KEYBOARD :
`; : INTERFACE :
`
`fO
`C
`FLASH BIOS KH) ONE LER
`128
`
`
`
`KRX
`
`SERIAL EXPANSION
`PORT
`
`AUDIO
`CONTROLLER
`
`
`
`
`
`
`
`
`
`NON-PCBUS
`CONTROLLER
`126
`
`1OO
`
`NETWORK
`CONTROLLER
`134
`
`NON-PCI DEVICE
`133
`
`Lenovo
`Ex. 1007 - Page 2
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`

`

`Patent Application Publication May 22, 2003 Sheet 2 of 7
`
`US 2003/0097503 A1
`
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`Lenovo
`Ex. 1007 - Page 3
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`

`

`Patent Application Publication
`
`US 2003/0097503 A1
`
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`Lenovo
`Ex. 1007 - Page 4
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`

`

`Patent Application Publication May 22, 2003 Sheet 4 of 7
`
`US 2003/0097503 A1
`
`
`
`SOFTWARE APPLICATION
`401
`
`OPERATING SYSTEM
`402
`
`DEVICE DRIVERS
`404
`
`PC INTERFACE LAYER
`4O6
`
`NON-PC BUS COMMUNICATION
`LAYER
`4.08
`
`FIG. 4
`
`Lenovo
`Ex. 1007 - Page 5
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`

`

`Patent Application Publication May 22, 2003. Sheet 5 of 7
`
`US 2003/0097503 A1
`
`COMPUTER SARUP/RESE
`5O2
`
`PERFORM HARDWARE CHECKS
`504
`
`FIG. 5
`
`ANY
`PC DEVICES
`FOUND?
`516
`
`FRECOGNIZEDEVICE DAND VENDOR
`D FOREACH DEVICE FOUND
`518
`
`LOAD OPERATING SYSTEM
`506
`
`OAO DEWCEDRIVERS FOR DEVICES
`FOUND
`
`NTAZE HARDWARE DEVICES
`508
`
`INALEZE AND CONFIGURE DEVICES
`522
`
`PERFORM SEARCH FOR
`CONNECTIONS ONPCBUS
`51O.
`
`
`
`MAP INTERRUPSOEVICES
`524
`
`
`
`ANY
`BRGES
`FOUND?
`52
`
`NTAZE AND CONFIGURE BROGES
`54
`
`ASSUMES NORMAL OFPERATION
`526
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Lenovo
`Ex. 1007 - Page 6
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`

`

`Patent Application Publication May 22, 2003 Sheet 6 of 7
`
`US 2003/0097503 A1
`
`START
`
`
`
`RECEIVE INTERRUPT OR MEMORY
`ACCESS FROM SYSTEM
`602
`
`DETERMINE WHICH / O DEVICE IS
`BEING REQUESTED
`604
`
`MAP PCI DEVICE ID TO
`NON-PC BUS DEVICE D
`606
`
`READ FROM PC MEMORY SPACE FOR
`REQUESTED I/O DEVICE
`608
`
`PACKAGE DATA FROM SYSTEM INTO
`NON-PC BUS PROTOCOL
`610
`
`SEND PACKAGED DATA TO /O DEVICE
`ON NON-PC BUS
`612
`
`FIG 6A
`
`Lenovo
`Ex. 1007 - Page 7
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`

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`Patent Application Publication May 22, 2003 Sheet 7 of 7
`
`US 2003/0097503 A1
`
`START
`
`
`
`RECEIVE NOT FICATION OF READ
`REQUEST FROM I/O DEVICE
`650
`
`DETERMINE WHICH I/O DEVICE SENT
`REO UEST
`652
`
`TRANSLATE NON-PC DATA MESSAGE
`TO PC FORMAT
`654
`
`MAP NON-PC DEVICE D
`TO PCI DEVICE D
`656
`
`ISSUE INTERRUPT TO SYSTEM
`658
`
`SYSTEM SERVICES REQUEST AND
`READS DEVICE MEMORY SPACE
`660
`
`FIG. 6B
`
`Lenovo
`Ex. 1007 - Page 8
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`US 2003/0097503 A1
`
`May 22, 2003
`
`PC COMPATIBLE BUS MODEL FOR NON-PC
`COMPATIBLE BUS ARCHITECTURES
`FIELD OF THE INVENTION
`0001. The present invention relates generally to the field
`of microprocessors and computer Systems. More particu
`larly, the present invention relates to a method and apparatus
`for peripheral component interface (PCI) compatible bus
`model for non-PCI compatible bus architectures.
`BACKGROUND OF THE INVENTION
`0002 Computer systems have become increasingly per
`vasive in our Society. In recent years, the price of personal
`computers (PCs) have rapidly declined. As a result, more
`and more consumerS have been able to take advantage of
`newer and faster machines. AS the Speed of the new pro
`cessors increases, new input/output (I/O) devices are also
`developed to make use of the greater processing power. An
`enormous array of peripheral devices are available for every
`kind of computer in the marketplace. These and other I/O
`devices are typically connected to a computer System
`through some type of bus. Whenever a user obtains a new
`I/O device, the user Simply plugs the device into the com
`puter and loads the appropriate device driver to configure the
`System.
`0.003 Computer motherboards are generally designed
`with one or more types of expansion buses having a number
`physical slots or ports to which a user can connect an I/O
`device. Examples of the different types of expansion buses
`fall under different protocols including Industry Standard
`Architecture (ISA), Peripheral Component Interconnect
`(PCI) local bus, and Accelerated Graphics Port (AGP).
`However, each bus protocol come with a unique expansion
`Slot and pin configuration. Different bus types are generally
`not compatible with each other. Furthermore, a specific
`hardware controller is needed on the motherboard to handle
`each type of bus. Thus, even though a large number of
`peripheral I/O devices exist, a user can only use the ones
`compatible with whichever bus protocols exist in the com
`puter at issue.
`0004. The bus limitations of computer systems also
`impact the manufacturers of Systems and I/O devices.
`Equipping a computer with the capability to handle each bus
`protocol is expensive in terms of time and money. Similarly,
`the marketing and development of peripheral devices
`wherein each bus type is a line item can Severely impact
`product direction. Thus, computer manufacturers often limit
`the Systems produced to having one or two widely popular
`types of buses. As a result, device manufacturers respond in
`kind by designing peripherals mainly for a few specific types
`of bus protocols. Similarly, the introduction of a new bus
`type is difficult as the computer System designers do not
`want to include an unknown bus protocol, device vendors do
`not want to make products for an unknown bus type, and
`consumers do not wish to buy items for a bus that may not
`be widely used. It is simply not cost effective for the
`manufacturers to attempt to meet the needs of every con
`Sumer out there with a unique and incompatible buS proto
`col.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0005 The present invention is illustrated by way of
`example and not limitations in the figures of the accompa
`nying drawings, in which like references indicate Similar
`elements, and in which:
`
`0006 FIG. 1 is a block diagram of a computer system
`having a capability to communicate with a non-PCI bus
`architecture via a PCI compatible bus in accordance with the
`present invention;
`0007 FIG. 2 is a block diagram of one embodiment of a
`non-PCI compatible bus architecture joined with a PCI
`compatible bus architecture;
`0008 FIG. 3 is a block diagram of another embodiment
`of a non-PCI compatible bus architecture joined with a PCI
`compatible bus architecture;
`0009 FIG. 4 is a block diagram of the software stack
`residing in a computer of one embodiment;
`0010 FIG. 5 is a flow chart showing one embodiment of
`a method to initialize a computer to access a non-PCI
`compatible bus architecture;
`0011 FIG. 6A is a flow chart showing one embodiment
`of a method in accordance with the present invention to
`communicate with a non-PCI compatible device acroSS a
`PCI bus; and
`0012 FIG. 6B is a flow chart showing one embodiment
`of a method in accordance with the present invention to
`receive communications from a non-PCI compatible device
`across a PCI bus.
`
`DETAILED DESCRIPTION
`0013 A method and apparatus for a PCI compatible bus
`model for non-PCI compatible bus architectures is dis
`closed. The embodiments described herein are described in
`the context of a microprocessor, but are not So limited.
`Although the following embodiments are described with
`reference to a computer System and the PCI bus protocol,
`other embodiments are applicable to other computing
`devices and other types of bus protocols. The same tech
`niques and teachings of the present invention can easily be
`applied to other types of machines or Systems that can
`benefit from connecting together incompatible bus architec
`tureS.
`In the following description, for purposes of expla
`0014.
`nation, numerous specific details are set forth in order to
`provide a thorough understanding of the present invention.
`One of ordinary skill in the art, however, will appreciate that
`these Specific details are not necessary in order to practice
`the present invention. In other instances, well known elec
`trical Structures and circuits have not been Set forth in
`particular detail in order to not necessarily obscure the
`present invention.
`0015 AS technology advances and new products emerge
`in the marketplace, many users have a desire to upgrade their
`existing computers and associated hardware. Most of these
`upgrades or replacements are associated with peripheral I/O
`hardware devices Such as Video cards, Sound cards, network
`controllers, game controllers, disk drives, etc. One popular
`bus protocol found in many computer systems is the PCI bus
`protocol. System manufacturers generally include a couple
`of PCI expansion slots on the motherboard of every com
`puter. As a result, peripheral device vendors design a large
`number of PCI compatible type of I/O devices to capitalize
`on the readily available market. However, improvements in
`buS technology are not as easily taken advantaged of. In
`order to incorporated a new buS protocol into a computer
`
`Lenovo
`Ex. 1007 - Page 9
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`US 2003/0097503 A1
`
`May 22, 2003
`
`System, a System manufacturer has to spend enormous
`amounts of time and money to design the new protocol and
`its necessary components into the board. Because bus pro
`tocols are usually not compatible and have different con
`nectors, a peripheral device adhering to a first protocol is not
`easily interchangeable and cannot be used with a Second
`protocol.
`0016 New bus architectures are continually being devel
`oped in order to improve the performance and utility of
`computer platforms. However, it is often necessary to first
`integrate these new buses into the present platform via
`existing or legacy bus interfaces until native Support can be
`provided for the operating Systems that run on the platform.
`Thus a System designer may wish to piggyback off an
`existing buS in the computer System in order to introduce a
`new bus protocol. Furthermore, a designer can easily incor
`porate a proprietary bus into a System with an embodiment
`of the present invention as long as end is PCI compatible.
`Embodiments of the present invention allow for the inte
`gration of a non-PCI compatible bus architecture into a
`system through a PCI compatible bus. Currently, the PCI bus
`is the predominant I/O bus having the most advanced
`plug-and-play (PnP) and power management capabilities. In
`order to integrate a new buS interface or interconnect bus
`into the PC platform in accordance with the present inven
`tion, a designer can use a System PCI bus to connect non-PCI
`compatible types of I/O devices to the computer. Because
`the PCI and non-PCI protocols are incompatible, the incom
`patible characteristics of the new bus have to be hidden from
`the system in order to masquerade the non-PCI bus and its
`new peripherals as a PCI bus and PCI type of devices.
`0017 Presently, Support for the integration or intercon
`nection of non-PCI buses and devices does not exist. Fur
`thermore, no standard bus integration model offers PCI
`compatibility. By using embodiments of the present inven
`tion, manufacturers can significantly reduce the time to
`market for new types of buses and I/O devices. Enhanced
`buses and related architectures can be introduced and deliv
`ered to the marketplace Sooner than if a Vendor needed to
`design the new bus into systems. The bus model of embodi
`ments of the present invention allow companies to easily
`provide the functionality of different types of presently
`unsupported new buses to Support mobile communications,
`advance multimedia functionalities, and other value enhanc
`ing features.
`0.018 Embodiments in accordance of the present inven
`tion as described below include a hardware controller or bus
`bridge to perform PCI to non-PCI and non-PCI to PCI
`translations for the PCI I/O commands/data to and from the
`host computer. The hardware controller masks the non-PCI
`bus architecture and topology from the host computer SyS
`tem in order to leverage the native initialization and con
`figuration Support that already exists for an industry Standard
`bus and interface like PCI. To accomplish this, the hardware
`controllers will expose themselves to the system as a PCI
`to-PCI (P2P) bridge on which PCI compatible devices are
`connected. By masquerading as a P2P bridge, the hardware
`controller is offered the opportunity to function as a proxy to
`its downstream non-PCI compatible devices. The I/O
`devices (communication front end devices or CFE) can be
`integrated into the system by the hardware controller as PCI
`compatible devices.
`
`0019. In one embodiment of the bus model, a hardware
`controller is a “traffic director' for downstream bus control
`ler devices and non-PCI CFE devices. As the traffic director,
`the hardware controller acts as the target of upstream bus
`transactions from an I/O device to the host and as the
`initiator of new non-PCI compatible bus transactions from
`the host. PCI commands and messages from the host have to
`be translated by a hardware controller into non-PCI com
`mands and messages before being delivered downstream to
`a non-PCI device. Similarly, a hardware controller has to
`translate the upstream non-PCI commands into PCI com
`mands to the host. As a result, embodiments of the present
`invention also manage a mapping between the PCI device
`identification (ID) and the non-PCI device ID in order to
`properly route communication traffic to and from the PCI
`bus.
`0020 Referring now to FIG. 1, an exemplary computer
`system 100 is shown. System 100 is representative of
`processing systems based on the PENTIUM(R) III, PEN
`TIUM(R) 4, and/or Itanium TM microprocessors available
`from Intel Corporation of Santa Clara, Calif., although other
`Systems (including PCs having other microprocessors, engi
`neering workstations, set-top boxes and the like) may also be
`used. In one embodiment, Sample System 100 may execute
`a version of the WINDOWSTM operating system available
`from Microsoft Corporation of Redmond, Wash., although
`other operating Systems and graphical user interfaces, UNIX
`and Linux for example, may also be used. Thus, the present
`invention is not limited to any Specific combination of
`hardware circuitry and Software.
`0021. The present enhancement is not limited to com
`puter Systems. Alternative embodiments of the present
`invention can be used in other devices Such as embedded
`applications. Embedded Systems can include a microcon
`troller, a digital signal processor (DSP), System on a chip,
`network computers (NetPC), set-top boxes, network hubs,
`wide area network (WAN) switches, or any other system
`which uses a PCI bus protocol and can connect to devices
`via a PCI bus.
`0022 FIG. 1 is a block diagram of a computer system
`100 having the capability to communicate with a non-PCI
`bus architecture via a PCI compatible bus in accordance
`with the present invention. The present embodiment is
`described in the context of a Single processor desktop or
`Server System, but alternative embodiments can be included
`in a multiprocessor system. System 100 is an example of a
`hub architecture. The computer system 100 includes a
`processor 102 to process data Signals. The processor 102 can
`be a complex instruction Set computer (CISC) microproces
`Sor, a reduced instruction set computing (RISC) micropro
`cessor, a very long instruction word (VLIW) microproces
`Sor, a processor implementing a combination of instruction
`Sets, or any other processor device, Such as a digital Signal
`processor, for example. The processor 102 is coupled to a
`processor bus 110 that transmits data signals between the
`processor 102 and other components in the system 100. The
`elements of system 100 perform their conventional functions
`well known in the art.
`0023 System 100 includes a memory 120. Memory 120
`can be a dynamic random access memory (DRAM) device,
`a static random access memory (SRAM) device, flash
`memory device, or other memory device. Memory 120 can
`
`Lenovo
`Ex. 1007 - Page 10
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`US 2003/0097503 A1
`
`May 22, 2003
`
`Store instructions and/or data represented by data Signals that
`can be executed by the processors 102. An internal cache
`memory 104 can reside inside the processor 102 to store
`recently used data Signals from memory 120. Alternatively,
`in another embodiment, the cache memory can reside exter
`nal to the processor 102.
`0024. A system logic chip 116 is coupled to the processor
`bus 110 and memory 120. The system logic chip 116 in the
`illustrated embodiment is a memory controller hub (MCH).
`The processor 102 communicates to the MCH 116 via a
`processor bus 110. The MCH 116 provides a high bandwidth
`memory path 118 to memory 120 for instruction and data
`Storage and for Storage of graphics commands, data and
`textures. The MCH 116 is to direct data signals between the
`processor 102, memory 120, and other components in the
`system 100 and to bridge the data signals between processor
`bus 110, memory 120, and system I/O 122. In some embodi
`ments, the System logic chip 116 can provide a graphics port
`for coupling to a graphics controller 112. The MCH 116 is
`coupled to memory 120 through a memory interface 118.
`The graphics card 112 is coupled to the MCH 116 through
`an Accelerated Graphics Port (AGP) interconnect 114.
`0.025 System 100 uses a proprietary hub interface bus
`122 to couple the MCH 116 to the I/O controller hub (ICH)
`130. The ICH 130 provides direct connections to some I/O
`devices via a local I/O bus. The local I/O bus is a high-speed
`I/O bus for connecting peripherals to the memory 120,
`chipset, and processor 102. The PCI protocol is commonly
`asSociated with a type of the local I/O bus. Some examples
`are the audio controller, firmware hub (flash BIOS) 128, data
`Storage 124, legacy I/O controller containing user input and
`keyboard interfaces, a Serial expansion port Such as Univer
`sal Serial Bus (USB), wireless transceivers, and a network
`controller 134. The data Storage device 124 can comprise a
`hard disk drive, a floppy disk drive, a CD-ROM device, a
`flash memory device, or other mass Storage device.
`0026. For the embodiment of a computing system in
`FIG. 1, a non-PCI bus controller 126 is also coupled on a
`PCI buS 131 to the ICH 130. The non-PCI bus controller 126
`is capable of receiving and transmitting Signals to and from
`the system 100 on the PCI bus 131. The non-PCI bus
`controller 126 is also physically and electrically compatible
`to the PCI bus protocol in order to connect to the PCI bus
`131. This non-PCI bus controller 126 can also be referred to
`as a bus bridge. Control of this non-PCI bus controller 126
`resides with Software located in the controller logic and
`memory 120. Also coupled to the non-PCI bus controller
`126 is a non-PCI device 133. This non-PCI device 133 is
`coupled on a bus 132 having a protocol different than the
`PCI protocol. Thus the non-PCI device 133 can indirectly
`interact with the rest of the system 100 through the PCI bus
`131, even though the non-PCI device is not designed to
`operate with the PCI protocol. Processor 102 can execute
`instructions from memory 120 that cause the processor 102
`to send data to and request from the non-PCI device 133.
`Furthermore, the non-PCI device 133 may be able to interact
`with other System components including the audio control
`ler, network controller 134, and I/O controller as needed.
`The operating System and device driver Software can also
`interface with the non-PCI bus controller 126 and a non-PCI
`device 133. The bus bridge 126 enables the computer system
`100 to communicate with a non-PCI device 133 through a
`PCI bus 131. Although the example of FIG. 1 shows the
`
`presence of one non-PCI device 126, a multiple of non-PCI
`devices can be coupled to the non-PCI bus bridge 126
`depending on the particular implementation. Furthermore in
`Some embodiments, the non-PCI devices may all be directly
`attached to the non-PCI bus controller 126 itself or the
`non-PCI devices may be connected together in a daisy chain.
`0027 FIG. 2 is a block diagram of one embodiment of a
`non-PCI compatible bus architecture joined with a PCI
`compatible bus architecture. For this embodiment, the hard
`ware controller 201 physically resides on the system moth
`erboard. In an alternative embodiment, the hardware con
`troller may be part of a plug-in board or expansion card that
`slides into a PCI expansion slot on the motherboard. The
`hardware controller 201 may also be referred to as a bus
`bridge as the hardware controller 201 functions as a bridge
`to communications between a first bus 212 compatible with
`the PCI protocol and a second bus 213 having a non-PCI
`compatible protocol. Presently, Support for the integration or
`interconnection of can also be referred to a “PCI to non-PCI
`bus bridge'. But the system itself may view the hardware
`controller 201 as a P2P bridge. A PCI to non-PCI translator
`202 is included in the hardware controller 201. This trans
`lator 202 operates to translate data, commands, interrupts,
`and other information between the PCI and non-PCI bus
`protocols. For this embodiment, the translator 202 is imple
`mented in logic circuits within the hardware controller 201.
`The translator 201 of alternative embodiments may also be
`implemented in Software or code residing and executing in
`the hardware controller 201 or a processor. Two non-PCI bus
`peripheral I/O devices, Device 0210 and Device 1220, are
`shown in this example, although the hardware controller 201
`of this embodiment is capable of Supporting three individual
`non-PCI devices. The non-PCI bus devices 210, 220, are
`coupled to the hardware controller 201 on a non-PCI com
`patible bus 212. The systems of other embodiments can be
`designed to handle a different number of non-PCI devices.
`In this embodiment, the non-PCI bus 212 is configured to be
`shared with multiple devices as a flatbus hierarchy and more
`than one non-PCI device can be physically connected to the
`buS 212.
`0028. A system interrupt controller 230 is coupled to the
`hardware controller 201. Three separate interrupt request
`(IRO) lines 234, 236,238, one for each of the supported I/O
`devices, extend between the interrupt controller 230 and the
`hardware controller 201. For this embodiment, the interrupt
`lines are handled by the hardware controller 201 and do not
`physically connect to the non-PCI devices. However, the
`interrupt lines of other embodiments may be coupled to the
`non-PCI devices. The hardware controller 201 includes
`interrupt resources to handle the PCI Interrupt Pin and
`Interrupt Line registers for each non-PCI I/O device. In this
`embodiment, bits in a read-only PCI Interrupt Pin register is
`set for each device that uses interrupts. During the I/O
`device discovery and configuration process, the configura
`tion algorithm for each device writes the interrupt routing
`information to PCI Interrupt Line register for each device.
`The system interfaces the hardware controller 201 and the
`attached non-PCI devices 210, 220, through an I/O device
`driver 240. The I/O device driver 240 may comprise of one
`or more Software components that may or may not be part
`of the operating system. For this embodiment, the I/O bus
`driver 240 is the PCI.SYS driver found in Microsoft Win
`dows. Specific software device drivers 244, 246, 248, for
`each of the non-PCI bus devices that are installed interface
`
`Lenovo
`Ex. 1007 - Page 11
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`US 2003/0097503 A1
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`May 22, 2003
`
`to the I/O bus driver Software 240 for enumeration and
`configuration for each of the non-PCI devices.
`0029. The system also provides memory resources as a
`memory mapped region in the System memory for each of
`the I/O devices coupled to the hardware controller 201. The
`PCI memory base address register for each non-PCI device
`is implemented in this embodiment of the hardware con
`troller 201 to cause the configuration Software to allocate a
`4 kilobyte (KB) memory mapped I/O region for each of the
`non-PCI devices. These memory regions 224, 226, 228, are
`to Support the device control and data pipes. During the
`discovery and configuration process, the configuration Soft
`ware for each I/O device allocates the 4KB memory mapped
`region and writes the memory start address to the PCI
`memory base address register for that device. The memory
`mapped regions 224, 226, 228, also interface with the I/O
`device driver 244, 246, 248, for the respective non-PCI I/O
`device. The hardware controller 201 of this embodiment also
`includes a direct memory access (DMA) controller for each
`I/O device to handle the accesses to the associated memory
`Space. Both the System and a non-PCI peripheral device can
`read and write to the memory mapped space for that par
`ticular I/O device. During normal operations, data can be
`communicated back and forth between the processor and a
`non-PCI device as each uses the assigned memory Space as
`a storage buffer and transfer mechanism.
`0.030. Also coupled to the hardware controller 201 are
`registers or memory Spaces for the configuration of each of
`the non-PCI devices that can be attached to the non-PCI bus
`212 and also for the hardware controller 201 itself. These
`configuration (config) spaces 211, 214, 216, 218, are used
`with the PCI buS 213 and the PCI device driver to ensure
`proper device recognition and operation. The hardware
`controller 201 of this embodiment is responsible for map
`ping the configuration information for downstream non-PCI
`devices appropriately into the PCI configuration Space asso
`ciated with each non-PCI device. The PCI configuration
`spaces 214, 216, 218, can store the PCI related configuration
`information for each of the associated I/O devices. For
`instance, the Device 0 PCI configuration space 214 can store
`the vendor ID (VID), device ID (DID), memory mapped
`addresses, interrupts, etc. for Device 0210. Similarly, the
`bridge PCI configuration Space 211 is used to configure the
`hardware controller (bus bridge) 201 for use on the PCI bus
`213. The bridge PCI configuration space 211 is to store the
`vendor ID (VID), device ID (DID), memory mapped
`addresses, interrupts, etc. for bus bridge 201. The hardware
`controller 201 needs the bridge PCI configuration space 211
`because the PCI system views the hardware controller 201
`as a P2Pbridge on the PCI bus 212. The hardware controller
`201 manages a PCI configuration Header Type 1 as required
`for P2P bridges under the PCI bus protocol. A PCI configu
`ration Header Type 0 is also managed by the hardware
`controller 201 for each of the possible three downstream
`non-PCI CFE devices of this embodiment. Each PCI con
`figuration Header Type 0 in this embodiment implements a
`16-bit status word to facilitate error recovery by the device
`driver. The hardware controller 201 of this embodiment can
`support the standard PCI configuration fields needed for
`proper operation and PCI functionality. The PCI configura
`tion spaces 211, 214, 216, 218, also interface with the I/O
`bus driver 240.
`
`0031) The hardware controller 201 allows the non-PCI
`I/O devices to be treated as normal PCI devices from the
`viewpoint of the system. The non-PCI bus architecture and
`its related devices, are transparent to the System. Embodi
`ments in accordance with the present invention allow for
`new buses and buses with a non-PCI topology to be back
`wards compatible with legacy Systems that cannot be
`upgraded. Similarly the PCI drivers are not aware of non
`PCI devices being coupled to the PCI bus. The non-PCI
`architecture can thus make use of the available built-in
`Support in the operating System for the PCI architecture.
`Althought the hardware controller (bus bridge) 201
`described in these examples are separate components, the
`functionality of the hardware controller may be incorporated
`into the chipset of alternative embodiments.
`0032 FIG. 3 is a block diagram of another embodiment
`of a non-PCI compatible bus architecture joined with a PCI
`compatible bus architecture. The hardware controller (PCI
`to non-PCI bus bridge) 301 of this embodiment physically
`resides on the System motherboard, but may also be mounted
`on a plug-in board or expansion card that slides into a PCI
`slot on the motherboard. A PCI to non-PCI translator 302 is
`included in the hardware controller 301. This translator 302
`is to translate data, commands, interrupts, and other infor
`mation between the PCI and non-PCI bus protocols. The
`present embodiment is configured to operate with a daisy
`chain of non-PCI bus devices connected to one another in
`series. Two non-PCI bus peripheral I/O devices, Device
`0310 and Device 1320, are shown coupled together in a
`daisy-chain pattern in this example. Depending on the
`particular implementation, the System and hardware control
`ler 301 may be capable of Supporting one or more individual
`non-PCI devices. A first non-PCI bus device, Device 0310,
`is coupled to the hardware controller 301 on a non-PCI
`compatible bus 312. A second non-PCI bus device, Device
`1320, is coupled to Device 0310 on a non-PCI compatible
`bus 313. The non-PCI buses 312, 313, are of the same
`non-PCI bus protocol type. If there are no I/O devices
`connected to the hardware controller 301, the bus bridge 301
`simply appears as another device on the PCI bus 315 from
`the Viewpoint of the operating System.
`0033) A system interrupt controller 330 is coupled to the
`hardware controller 301. Two separate interrupt request
`(IRO) lines, Device 0 IRQ 334 and Device 1 IRQ 336, one
`for each of the supported I/O devices shown in FIG. 3,
`extend between the interrupt controller 330 and the hard
`ware controller 301. Additional IRQ lines may be added as
`needed if additional I/O devices are coupled to the hardware
`controller 301. The system interfaces the hardware control
`ler 301 and the attached non-PCI devices 310,320, through
`an I/O device driver 340. Within the I/O device driver
`Software 340 can be the specific software device drivers for
`each of the non-PCI bus devices 310,320, that are installed.
`The System provides a memory mapped region 324, 326, in
`the system memory for each of the I/O devices 310, 320,
`coupled to the hardware controller 301. The hardware con
`troller 301 of this embodiment also includes a DMA con
`troller for each I/O device to handle the accesses to the
`asSociated memory Space. Both the System and a non-PCI
`peripheral device can read and write to the memory mapped
`Space for that particular I/O device.
`0034. Also coupled to the hardware controller 301 are
`registers or memory SpaceS for the configuration of each of
`
`Lenovo
`Ex. 1007 - Page 12
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`US 2003/0097503 A1
`
`May 22, 2003
`
`the non-PCI devices that can be attached via a non-PCI bus