PCF8584
`I2C-bus controller
`
`Product specification
`Supersedes data of 1997 Mar 19
`File under Integrated Circuits, IC12
`
`1997 Oct 21
`
`Lenovo
`Ex. 1009 - Page 1
`
`

`

`Product specification
`
`PCF8584
`
`SOFTWARE FLOWCHART EXAMPLES
`7
`Initialization
`7.1
`Implementation
`7.2
`I2C-BUS TIMING DIAGRAMS
`8
`LIMITING VALUES
`9
`HANDLING
`10
`DC CHARACTERISTICS
`11
`I2C-BUS TIMING SPECIFICATIONS
`12
`PARALLEL INTERFACE TIMING
`13
`APPLICATION INFORMATION
`14
`Application Notes
`14.1
`PACKAGE OUTLINES
`15
`SOLDERING
`16
`Introduction
`16.1
`DIP
`16.2
`Soldering by dipping or by wave
`16.2.1
`Repairing soldered joints
`16.2.2
`SO
`16.3
`Reflow soldering
`16.3.1
`Wave soldering
`16.3.2
`Repairing soldered joints
`16.3.3
`DEFINITIONS
`17
`LIFE SUPPORT APPLICATIONS
`18
`19 PURCHASE OF PHILIPS I2C COMPONENTS
`
`Philips Semiconductors
`
`I2C-bus controller
`
`CONTENTS
`
`1
`2
`3
`4
`5
`6
`6.1
`6.2
`6.3
`6.4
`6.5
`6.6
`6.7
`6.8
`6.8.1
`6.8.1.1
`6.8.1.2
`6.8.1.3
`6.8.1.4
`6.8.1.5
`6.8.1.6
`6.8.2
`6.8.2.1
`6.8.2.2
`6.8.2.3
`6.8.2.4
`6.8.2.5
`6.8.2.6
`6.8.2.7
`6.9
`6.10
`6.11
`6.11.1
`6.11.2
`6.12
`6.12.1
`6.12.2
`6.12.3
`
`FEATURES
`GENERAL DESCRIPTION
`ORDERING INFORMATION
`BLOCK DIAGRAM
`PINNING
`FUNCTIONAL DESCRIPTION
`General
`Interface Mode Control (IMC)
`Set-up registers S0', S2 and S3
`Own address register S0'
`Clock register S2
`Interrupt vector S3
`Data shift register/read buffer S0
`Control/status register S1
`Register S1 control section
`PIN (Pending Interrupt Not)
`ESO (Enable Serial Output)
`ES1 and ES2
`ENI
`STA and STO
`ACK
`Register S1 status section
`PIN bit
`STS
`BER
`LRB/AD0
`AAS
`LAB
`BB
`Multi-master operation
`Reset
`Comparison to the MAB8400 I2C-bus interface
`Deleted functions
`added functions
`Special function modes
`Strobe
`Long-distance mode
`Monitor mode
`
`1997 Oct 21
`
`2
`
`Lenovo
`Ex. 1009 - Page 2
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`FEATURES
`1
`— Parallel-bus to I2C-bus protocol converter and interface
`— Compatible with most parallel-bus
`microcontrollers/microprocessors including 8049, 8051,
`6800, 68000 and Z80
`— Both master and slave functions
`— Automatic detection and adaption to bus interface type
`— Programmable interrupt vector
`— Multi-master capability
`— I2C-bus monitor mode
`— Long-distance mode (4-wire)
`— Operating supply voltage 4.5 to 5.5 V
`— Operating temperature range: -40 to +85 (cid:144)C.
`
`3 ORDERING INFORMATION
`
`Product specification
`
`PCF8584
`
`2 GENERAL DESCRIPTION
`The PCF8584 is an integrated circuit designed in CMOS
`technology which serves as an interface between most
`standard parallel-bus microcontrollers/microprocessors
`and the serial I2C-bus. The PCF8584 provides both master
`and slave functions.
`Communication with the I2C-bus is carried out on a
`byte-wise basis using interrupt or polled handshake.
`It controls all the I2C-bus specific sequences, protocol,
`arbitration and timing. The PCF8584 allows parallel-bus
`systems to communicate bidirectionally with the I2C-bus.
`
`TYPE
`NUMBER
`PCF8584P
`PCF8584T
`
`PACKAGE
`DESCRIPTION
`plastic dual in-line package; 20 leads (300 mil)
`plastic small outline package; 20 leads; body width 7.5 mm
`
`NAME
`DIP20
`SO20
`
`VERSION
`SOT146-1
`SOT163-1
`
`1997 Oct 21
`
`3
`
`Lenovo
`Ex. 1009 - Page 3
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`4 BLOCK DIAGRAM
`
`Product specification
`
`PCF8584
`
`PARALLEL BUS
`
`DB7
`
`DB6
`
`DB5
`
`DB4
`
`DB3
`
`DB2
`
`DB1
`
`DB0
`
`15
`
`14
`
`13
`
`12
`
`11
`
`9
`
`8
`
`7
`
`V
`
`DD
`20
`
`V
`
`SS
`10
`
`read
`only
`
`write
`only
`
`SDA/
`SDA OUT
`
`(3)
`
`2
`
`DIGITAL
`FILTER
`
`MSB
`
`READ BUFFER
`
`DATA SHIFT REGISTER S0 AND READ BUFFER
`
`SHIFT REGISTER
`
`8
`
`COMPARATOR S0, S0'
`
`8
`
`OWN ADDRESS S0'
`
`8
`
`INTERRUPT VECTOR S3
`
`MSB
`
`(1)
`
`X
`
`(1)
`
`X
`
`LSB
`
`DATA CONTROL
`
`PCF8584
`
`3
`
`SCL/
`SCL IN
`
`(3)
`
`DIGITAL
`FILTER
`
`CLOCK REGISTER S2
`S24
`0
`0
`
`0
`
`SCL CONTROL
`
`CONTROL STATUS
`ES2
`ES1
`ES0
`
`PIN
`
`8
`
`default: 00H 80XX
` 0FH 68XXX
`
`S23
`S22
`S21
`CLOCK REGISTER S2
`8
`REGISTER S1
`STA
`ENI
`
`STO
`
`AAS
`
`LAB
`
`S20
`
`ACK
`
`BB
`
`write only
`
`read only
`
`CONTROL STATUS REGISTER S1
`AD0/
`LRB
`
`STS
`
`BER
`
`PIN
`
`0
`
`CLOCK PRESCALER
`SCL MULTIPLEXER
`BUS BUSY LOGIC
`ARBITRATION LOGIC
`
`17
`
`CS
`
`6
`
`A0
`
`19
`
`RESET/
`STROBE
`(O.C.)
`
`PARALLEL BUS CONTROL
`
`REGISTER ACCESS CONTROL
`BUS BUFFER CONTROL
`INTERRUPT CONTROL
`RESET/STROBE CONTROL
`
`18
`
`16
`
`5
`
`4
`
`WR (R/W)
`
`(2)
`
`RD (DTACK)
`
`(2)
`
`INT
`SCL OUT
`
`(3)
`
`IACK
`SDA IN
`
`(3)
`
`1
`
`CLK
`
`(1) X = don’t care.
`(2) Pin mnemonics between parenthesis indicate the 68000 mode pin designations.
`(3) These pin mnemonics represent the long-distance mode pin designations.
`
`Fig.1 Block diagram.
`
`1997 Oct 21
`
`4
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`Lenovo
`Ex. 1009 - Page 4
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`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`5 PINNING
`SYMBOL
`CLK
`SDA or
`SDA OUT
`SCL or SCL IN
`IACK or
`SDA IN
`
`INT or
`SCL OUT
`
`A0
`
`DB0
`DB1
`DB2
`VSS
`DB3
`DB4
`DB5
`DB6
`DB7
`RD (DTACK)
`
`CS
`WR (R/W)
`
`RESET/
`STROBE
`VDD
`
`PIN
`1
`2
`
`3
`4
`
`5
`
`6
`
`7
`8
`9
`10
`11
`12
`13
`14
`15
`16
`
`17
`18
`
`19
`
`20
`
`I/O
`I
`I/O
`
`I/O
`I
`
`O
`
`I
`
`DESCRIPTION
`clock input from microcontroller clock generator (internal pull-up)
`I2C-bus serial data input/output (open-drain). Serial data output in long-distance
`mode.
`I2C-serial clock input/output (open-drain). Serial clock input in long-distance mode.
`Interrupt acknowledge input (internal pull-up); when this signal is asserted the
`interrupt vector in register S3 will be available at the bus Port if the ENI flag is set.
`Serial data input in long-distance mode.
`Interrupt output (open-drain); this signal is enabled by the ENI flag in register S1.
`It is asserted when the PIN flag is reset. (PIN is reset after 1 byte is transmitted or
`received over the I2C-bus). Serial clock output in long-distance mode.
`Register select input (internal pull-up); this input selects between the control/status
`register and the other registers. Logic 1 selects register S1, logic 0 selects one of
`the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1.
`bidirectional 8-bit bus Port 0
`I/O
`bidirectional 8-bit bus Port 1
`I/O
`bidirectional 8-bit bus Port 2
`I/O
`ground
`-
`bidirectional 8-bit bus Port 3
`I/O
`bidirectional 8-bit bus Port 4
`I/O
`bidirectional 8-bit bus Port 5
`I/O
`bidirectional 8-bit bus Port 6
`I/O
`bidirectional 8-bit bus Port 7
`I/O
`I/(O) RD is the read control input for MAB8049, MAB8051 or Z80-types. DTACK is the
`data transfer control output for 68000-types (open-drain).
`chip select input (internal pull-up)
`WR is the write control input for MAB8048, MAB8051, or Z80-types
`(internal pull-up). R/W control input for 68000-types.
`Reset input (open-drain); this input forces the I2C-bus controller into a predefined
`state; all flags are reset, except PIN, which is set. Also functions as strobe output.
`supply voltage
`
`I
`I
`
`I/O
`
`-
`
`1997 Oct 21
`
`5
`
`Lenovo
`Ex. 1009 - Page 5
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`Table 1 Control signals utilized by the PCF8584 for
`microcontroller/microprocessor interfacing
`R/W
`WR
`R
`DTACK IACK
`no
`yes
`yes
`no
`no
`
`yes
`no
`
`no
`yes
`
`no
`yes
`
`yes
`no
`
`yes
`yes
`
`TYPE
`8048/
`8051
`68000
`Z80
`
`The structure of the PCF8584 is similar to that of the
`I2C-bus interface section of the Philips’
`MABXXXX/PCF84(C)XX-series of microcontrollers, but
`with a modified control structure. The PCF8584 has five
`internal register locations. Three of these (own address
`register S0', clock register S2 and interrupt vector S3) are
`used for initialization of the PCF8584. Normally they are
`only written once directly after resetting of the PCF8584.
`The remaining two registers function as double registers
`(data buffer/shift register S0, and control/status
`register S1) which are used during actual data
`transmission/reception. By using these double registers,
`which are separately write and read accessible, overhead
`for register access is reduced. Register S0 is a
`combination of a shift register and data buffer.
`Register S0 performs all serial-to-parallel interfacing with
`the I2C-bus.
`Register S1 contains I2C-bus status information required
`for bus access and/or monitoring.
`
`Interface Mode Control (IMC)
`6.2
`Selection of either an 80XX mode or 68000 mode
`interface is achieved by detection of the first WR-CS signal
`sequence. The concept takes advantage of the fact that
`the write control input is common for both types of
`interfaces. An 80XX-type interface is default. If a
`HIGH-to-LOW transition of WR (R/W) is detected while CS
`is HIGH, the 68000-type interface mode is selected and
`the DTACK output is enabled. Care must be taken that WR
`and CS are stable after reset.
`
`PCF8584
`
`20
`
`19
`
`18
`
`17
`
`16
`
`15
`
`14
`
`13
`
`12
`
`11
`
`VDD
`RESET / STROBE
`(1)
`
`WR (R/W)
`
`CS
`
`RD (DTACK)
`
`(1)
`
`DB7
`
`DB6
`
`DB5
`
`DB4
`
`DB3
`
`1 2 3 4 5 6 7 8 9 1
`
`0
`
`CLK
`
`SDA or SDA OUT
`
`SCL or SCL IN
`
`IACK or SDA IN
`
`INT or SCL OUT
`
`A0
`
`DB0
`
`DB1
`
`DB2
`
`VSS
`
`(1) Pin mnemonics between parenthesis indicate the 68000 mode
`pin designations.
`
`Fig.2 Pin configuration.
`
`FUNCTIONAL DESCRIPTION
`6
`General
`6.1
`The PCF8584 acts as an interface device between
`standard high-speed parallel buses and the serial I2C-bus.
`On the I2C-bus, it can act either as master or slave.
`Bidirectional data transfer between the I2C-bus and the
`parallel-bus microcontroller is carried out on a byte-wise
`basis, using either an interrupt or polled handshake.
`Interface to either 80XX-type (e.g. 8048, 8051, Z80) or
`68000-type buses is possible. Selection of bus type is
`automatically performed (see Section 6.2).
`
`1997 Oct 21
`
`6
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`Lenovo
`Ex. 1009 - Page 6
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`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`I2C-bus
`SCL
`
`(1.5 MHz)
`
`SIO DIVIDER
`(S21 and S20)
`
` DIVIDER
`(S24, S23, S22)
`/2, 3, 4, 5, 8
`
`EN
`
`D
`
`ENRD
`
`EN
`
`D
`
`FILTER
`t = 16CLK
`
`RESET
`STROBE
`
`CS
`
`A0
`
`WR/
`R/W
`
`RD/
`DTACK
`
`INT
`
`IACK
`
`CLK
`(50 : 50)
`
`mode select
`
`mode locked
`
`mode select
`
`(1)
`
`(2)
`
`R/W
`
`CS
`
`DTACK
`
`WR
`
`CS
`
`(1) Bus timing; 68000 mode write cycle.
`(2) Bus timing; 80XX mode.
`
`Fig.3 68000/80XX timing sequence utilized by the Interface Mode Control (IMC).
`
`1997 Oct 21
`
`7
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`Ex. 1009 - Page 7
`
`

`

`Product specification
`
`PCF8584
`
`Programming of S2 is accomplished via the parallel-bus
`when A0 = LOW, with the appropriate bit combinations set
`in control status register S1 (S1 is written when
`A0 = HIGH). Bit combinations for accessing all registers
`are given in Table 5.
`
`Table 3 Register S2 selection of clock frequency
`INTERNAL CLOCK FREQUENCY
`S23
`S22
`fclk (MHz)
`X(1)
`X(1)
`3
`0
`0
`4.43
`0
`1
`6
`1
`0
`8
`1
`1
`12
`
`S24
`0
`1
`1
`1
`1
`
`Note
`1. X = don’t care.
`
`Interrupt vector S3
`6.6
`The interrupt vector register provides an 8-bit
`user-programmable vector for vectored-interrupt
`microcontrollers. The vector is sent to the bus port
`(DB7 to DB0) when an interrupt acknowledge signal is
`asserted and the ENI (enable interrupt) flag is set. Default
`vector values are:
`— Vector is ‘00H’ in 80XX mode
`— Vector is ‘0FH’ in 68000 mode.
`On reset the PCF8584 is in the 80XX mode, thus the
`default interrupt vector is ‘00H’.
`
`Data shift register/read buffer S0
`6.7
`Register S0 acts as serial shift register and read buffer
`interfacing to the I2C-bus. All read and write operations
`to/from the I2C-bus are done via this register. S0 is a
`combination of a shift register and a data buffer; parallel
`data is always written to the shift register, and read from
`the data buffer. I2C-bus data is always shifted in or out of
`shift register S0.
`
`Philips Semiconductors
`
`I2C-bus controller
`
`Set-up registers S0', S2 and S3
`6.3
`Registers S0', S2 and S3 are used for initialization of the
`PCF8584 (see Fig.5 ‘Initialization sequence’ flowchart).
`
`Own address register S0'
`6.4
`When the PCF8584 is addressed as slave, this register
`must be loaded with the 7-bit I2C-bus address to which the
`PCF8584 is to respond. During initialization, the own
`address register S0' must be written to, regardless
`whether it is later used. The Addressed As Slave (AAS) bit
`in status register S1 is set when this address is received
`(the value in S0 is compared with the value in S0'). Note
`that the S0 and S0' registers are offset by one bit; hence,
`programming the own address register S0' with a value of
`55H will result in the value AAH being recognized as the
`PCF8584’s slave address (see Fig.1).
`Programming of S0' is accomplished via the parallel-bus
`when A0 is LOW, with the appropriate bit combinations set
`in control status register S1 (S1 is written when
`pin A0 = HIGH). Bit combinations for accessing all
`registers are given in Table 5. After reset, S0' has default
`address 00H (PCF8584 is thus initially in monitor mode,
`see Section 6.12.3).
`
`Clock register S2
`6.5
`Register S2 provides control over chip clock frequency
`and SCL clock frequency. S20 and S21 provide a selection
`of 4 different I2C-bus SCL frequencies which are shown in
`Table 2. Note that these SCL frequencies are only
`obtained when bits S24, S23 and S22 are programmed to
`the correct input clock frequency (fclk).
`
`Table 2 Register S2 selection of SCL frequency
`BIT
`
`S21
`0
`0
`1
`1
`
`S20
`0
`1
`0
`1
`
`APPROXIMATE SCL
`FREQUENCY fSCL (kHz)
`90
`45
`11
`1.5
`
`S22, S23 and S24 are used for control of the internal clock
`prescaler. Due to the possibility of varying microcontroller
`clock signals, the prescaler can be programmed to adapt
`to 5 different clock rates, thus providing a constant internal
`clock. This is required to provide a stable time base for the
`SCL generator and the digital filters associated with the
`I2C-bus signals SCL and SDA. Selection for adaption to
`external clock rates is shown in Table 3.
`
`1997 Oct 21
`
`8
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`Ex. 1009 - Page 8
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`DB7
`
`DB6
`
`to/from microcontroller parallel bus
`DB5
`DB4
`DB3
`DB2
`DB1
`
`DB0
`
`Read Buffer
`Data Shift Register S0 and Read Buffer
`Shift register
`
`Read
`only
`
`Write
`only
`
`to/from
`I2C-Bus SDA line
`
`Fig.4 Data shift register/bus buffer S0.
`
`In receiver mode the data from the shift register is copied to the read buffer during the acknowledge phase. Further
`reception of data is inhibited (SCL held LOW) until the S0 read buffer is read (see Section 6.8.1.1).
`In the transmitter mode data is transmitted to the I2C-bus as soon as it is written to the S0 shift register if the serial I/O is
`enabled (ESO = 1).
`Remarks:
`1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the
`I2C-bus controller operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies.
`2. To start a read operation immediately after a write, it is necessary to read the S0 read buffer in order to invoke
`reception of the first byte (‘dummy read’ of the address). Immediately after the acknowledgement, this first byte will
`be transferred from the shift register to the read buffer. The next read will then transfer the correct value of the first
`byte to the microcontroller bus (see Fig.7).
`
`Control/status register S1
`6.8
`Register S1 controls I2C-bus operation and provides I2C-bus status information. Register S1 is accessed by a HIGH
`signal on register select input A0. For more efficient communication between microcontroller/processor and the I2C-bus,
`register S1 has separate read and write functions for all bit positions (see Fig.3). The write-only section provides register
`access control and control over I2C-bus signals, while the read-only section provides I2C-bus status information.
`
`Table 4 Control/status register S1
`CONTROL/STATUS
`Control(1)
`Status(2)
`
`PIN
`PIN
`
`BITS
`
`ESO
`0(3)
`
`ES1
`STS
`
`ES2
`BER
`
`ENI
`AD0/LRB
`
`STA
`AAS
`
`STO
`LAB
`
`ACK
`BB
`
`MODE
`write only
`read only
`
`Notes
`1. For further information see Section 6.8.1.
`2. For further information see Section 6.8.2.
`3. Logic 1 if not-initialized.
`
`1997 Oct 21
`
`9
`
`Lenovo
`Ex. 1009 - Page 9
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`REGISTER S1 CONTROL SECTION
`6.8.1
`The write-only section of S1 enables access to registers S0, S0', S1, S2 and S3, and controls I2C-bus operation; see
`Table 4.
`
`When the PIN bit is written with a logic 1, all status bits are reset to logic 0. This may serve as a software reset function
`(see Figs 5 to 9). PIN is the only bit in S1 which may be both read and written to. PIN is mostly used as a status bit for
`synchronizing serial communication, see Section 6.8.2.
`
`ESO enables or disables the serial I2C-bus I/O. When ESO is LOW, register access for initialization is possible. When
`ESO is HIGH, I2C-bus communication is enabled; communication with serial shift register S0 is enabled and the S1 bus
`status bits are made available for reading.
`
`Table 5 Register access control; ESO = 0 (serial interface off) and ESO = 1 (serial interface on)
`INTERNAL REGISTER ADDRESSING 2-WIRE MODE
`ES2
`IACK
`
`FUNCTION
`
`ES1
`A0
`ESO = 0; serial interface off (see note 1)
`1
`0
`0
`0
`0
`0
`0
`1
`ESO = 1; serial interface on
`1
`0
`1
`0
`0
`0
`0
`0
`X
`0
`
`X
`0
`1
`0
`
`X
`X
`0
`1
`X
`
`1(2)
`1(2)
`1(2)
`1(2)
`
`1
`1
`1
`1
`0
`
`R/W S1: control
`R/W S0': (own address)
`R/W S3: (interrupt vector)
`R/W S2: (clock register)
`
`W S1: control
`R S1; status
`R/W S0: (data)
`R/W S3: (interrupt vector)
`R S3: (interrupt vector ACK cycle))
`
`Notes
`1. With ESO = 0, bits ENI, STA, STO and ACK of S1 can be read for test purposes.
`2.
`‘X’ if ENI = 0.
`
`ES1 and ES2 control selection of other registers for initialization and control of normal operation. After these bits are
`programmed for access to the desired register (shown in Table 5), the register is selected by a logic LOW level on
`register select pin A0.
`
`This bit enables the external interrupt output INT, which is generated when the PIN bit is active (logic 0).
`This bit must be set to logic 0 before entering the long-distance mode, and remain at logic 0 during operation in
`long-distance mode.
`
`1997 Oct 21
`
`10
`
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`Ex. 1009 - Page 10
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`These bits control the generation of the I2C-bus START condition and transmission of slave address and R/W bit,
`generation of repeated START condition, and generation of the STOP condition (see Table 7).
`
`Table 6 Register access control; ESO = 1 (serial interface on) and ES1 = 1; long-distance (4-wire) mode; note 1
`INTERNAL REGISTER ADDRESSING: LONG-DISTANCE (4-WIRE) MODE
`ES1
`ES2
`IACK
`FUNCTION
`1
`X
`1
`1
`X
`X
`1
`X
`X
`
`W S1: control
`R S1; status
`R/W S0; (data)
`
`A0
`1
`1
`0
`
`Note
`1. Trying to read from or write to registers other than S0 and S1 (setting ESO = 0) brings the PCF8584 out of the
`long-distance mode.
`
`Table 7 Instruction table for serial bus control
`PRESENT
`MODE
`SLV/REC
`
`STO
`
`0
`
`STA
`
`1
`
`FUNCTION
`
`START
`
`REPEAT
`START
`STOP READ;
`STOP WRITE
`DATA
`CHAINING
`NOP
`
`OPERATION
`
`transmit START + address, remain
`MST/TRM if R/W = 0;
`go to MST/REC if R/W = 1
`same as for SLV/REC
`
`transmit STOP go to SLV/REC mode; note 1
`
`send STOP, START and address after last
`master frame without STOP sent; note 2
`no operation; note 3
`
`1
`
`0
`
`1
`
`0
`
`0
`
`1
`
`1
`
`0
`
`MST/TRM
`
`MST/REC;
`MST/TRM
`MST
`
`ANY
`
`Notes
`1.
`In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’).
`2.
`If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
`condition + address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control.
`3. All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
`
`This bit must be set normally to a logic 1. This causes the I2C-bus controller to send an acknowledge automatically after
`each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I2C-bus controller is
`operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
`negative acknowledge on the I2C-bus, which halts further transmission from the slave device.
`
`REGISTER S1 STATUS SECTION
`6.8.2
`The read-only section of S1 enables access to I2C-bus status information; see Table 4.
`
`1997 Oct 21
`
`11
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`Ex. 1009 - Page 11
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`‘Pending Interrupt Not’ (MSB of register S1) is a status flag
`which is used to synchronize serial communication and is
`set to logic 0 whenever the PCF8584 requires servicing.
`The PIN bit is normally read in polled applications to
`determine when an I2C-bus byte transmission/reception is
`completed. The PIN bit may also be written, see
`Section 6.8.1.
`Each time a serial data transmission is initiated (by setting
`the STA bit in the same register), the PIN bit will be set to
`logic 1 automatically (inactive). When acting as
`transmitter, PIN is also set to logic 1 (inactive) each time
`S0 is written. In receiver mode, the PIN bit is automatically
`set to logic 1 (inactive) each time the data register S0 is
`read.
`After transmission or reception of one byte on the I2C-bus
`(9 clock pulses, including acknowledge), the PIN bit will be
`automatically reset to logic 0 (active) indicating a complete
`byte transmission/reception. When the PIN bit is
`subsequently set to logic 1 (inactive), all status bits will be
`reset to logic 0. PIN is also set to zero on a BER (bus error)
`condition.
`In polled applications, the PIN bit is tested to determine
`when a serial transmission/reception has been completed.
`When the ENI bit (bit 4 of write-only section of register S1)
`is also set to logic 1 the hardware interrupt is enabled.
`In this case, the PIN flag also triggers an external interrupt
`(active LOW) via the INT output each time PIN is reset to
`logic 0 (active).
`When acting as slave transmitter or slave receiver, while
`PIN = 0, the PCF8584 will suspend I2C-bus transmission
`by holding the SCL line LOW until the PIN bit is set to
`logic 1 (inactive). This prevents further data from being
`transmitted or received until the current data byte in S0 has
`been read (when acting as slave receiver) or the next data
`byte is written to S0 (when acting as slave transmitter).
`PIN bit summary:
`— The PIN bit can be used in polled applications to test
`when a serial transmission has been completed. When
`the ENI bit is also set, the PIN flag sets the external
`interrupt via the INT output.
`— Setting the STA bit (start bit) will set PIN = 1 (inactive).
`— In transmitter mode, after successful transmission of
`one byte on the I2C-bus the PIN bit will be automatically
`reset to logic 0 (active) indicating a complete byte
`transmission.
`— In transmitter mode, PIN is set to logic 1 (inactive) each
`time register S0 is written.
`
`1997 Oct 21
`
`12
`
`— In receiver mode, PIN is set to logic 0 (active) on
`completion of each received byte. Subsequently, the
`SCL line will be held LOW until PIN is set to logic 1.
`— In receiver mode, when register S0 is read, PIN is set to
`logic 1 (inactive).
`— In slave receiver mode, an I2C-bus STOP condition will
`set PIN = 0 (active).
`— PIN = 0 if a bus error (BER) occurs.
`
`When in slave receiver mode, this flag is asserted when an
`externally generated STOP condition is detected (used
`only in slave receiver mode).
`
`Bus error; a misplaced START or STOP condition has
`been detected. Resets BB (to logic 1; inactive), sets
`PIN = 0 (active).
`
`‘Last Received Bit’ or ‘Address 0 (General Call) bit’. This
`status bit serves a dual function, and is valid only while
`PIN = 0:
`1. LRB holds the value of the last received bit over the
`I2C-bus while AAS = 0 (not addressed as slave).
`Normally this will be the value of the slave
`acknowledgement; thus checking for slave
`acknowledgement is done via testing of the LRB.
`2. AD0; when AAS = 1 (‘Addressed As Slave’ condition),
`the I2C-bus controller has been addressed as a slave.
`Under this condition, this bit becomes the ‘AD0’ bit and
`will be set to logic 1 if the slave address received was
`the ‘general call’ (00H) address, or logic 0 if it was the
`I2C-bus controller’s own slave address.
`
`‘Addressed As Slave’ bit. Valid only when PIN = 0. When
`acting as slave receiver, this flag is set when an incoming
`address over the I2C-bus matches the value in own
`address register S0' (shifted by one bit, see Section 6.4),
`or if the I2C-bus ‘General Call’ address (00H) has been
`received (‘General Call’ is indicated when AD0 status bit is
`also set to logic 1, see Section 6.8.2.4).
`
`‘Lost Arbitration’ Bit. This bit is set when, in multi-master
`operation, arbitration is lost to another master on the
`I2C-bus.
`
`Lenovo
`Ex. 1009 - Page 12
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`‘Bus Busy’ bit. This is a read-only flag indicating when the
`I2C-bus is in use. A zero indicates that the bus is busy, and
`access is not possible. This bit is set/reset (logic 1/logic 0)
`by STOP/START conditions.
`
`Multi-master operation
`6.9
`To avoid conflict between data and repeated START and
`STOP operations, multi-master systems have some
`limitations:
`— When powering up multiple PCF8584s in multi-master
`systems, the possibility exists that one node may power
`up slightly after another node has already begun an
`I2C-bus transmission; the Bus Busy condition will thus
`not have been detected. To avoid this condition, a delay
`should be introduced in the initialization sequence of
`each PCF8584 equal to the longest I2C-bus
`transmission, see flowchart ‘PCF8584 initialization’
`(Fig.5).
`
`6.10 Reset
`A LOW level pulse on the RESET (CLK must run) input
`forces the I2C-bus controller into a well-defined state.
`All flags in S1 are reset to logic 0, except the PIN flag and
`the BB flag, which are set to logic 1. S0' and S3 are set
`to 00H.
`The RESET pin is also used for the STROBE output
`signal. Both functions are separated on-chip by a digital
`filter. The reset input signal has to be sufficiently long
`(minimum 30 clock cycles) to pass through the filter.
`The STROBE output signal is sufficiently short (8 clock
`cycles) to be blocked by the filter. For more detailed
`information on the strobe function see Section 6.12.
`
`6.11 Comparison to the MAB8400 I2C-bus interface
`The structure of the PCF8584 is similar to that of the
`MAB8400 series of microcontrollers, but with a modified
`control structure. Access to all I2C-bus control and status
`registers is done via the parallel-bus port in conjunction
`with register select input A0, and control bits ESO, ES1
`and ES2.
`
`6.11.1 DELETED FUNCTIONS
`The following functions are not available in the PCF8584:
`— Always selected (ALS flag)
`— Access to the bit counter (BC0 to BC2)
`— Full SCL frequency selection (2 bits instead of 5 bits)
`— The non-acknowledge mode (ACK flag)
`— Asymmetrical clock (ASC flag).
`
`6.11.2
`ADDED FUNCTIONS
`The following functions either replace the deleted
`functions or are completely new:
`— Chip clock prescaler
`— Assert acknowledge bit (ACK flag)
`— Register selection bits (ES1 and ES2 flags)
`— Additional status flags (BER, ‘bus error’)
`— Automatic interface control between 80XX and
`68000-type microcontrollers
`— Programmable interrupt vector
`— Strobe generator
`— Bus monitor function
`— Long-distance mode [non-I2C-bus mode (4-wire); only
`for communication between parallel-bus processors
`using the PCF8584 at each interface point].
`
`6.12 Special function modes
`6.12.1 STROBE
`When the I2C-bus controller receives its own address (or
`the ‘00H’ general call address) followed immediately by a
`STOP condition (i.e. no further data transmitted after the
`address), a strobe output signal is generated at the
`RESET/STROBE pin (pin 19). The STROBE signal
`consists of a monostable output pulse (active LOW),
`8 clock cycles long (see Fig.9). It is generated after the
`STOP condition is received, preceded by the correct slave
`address. This output can be used as a bus access
`controller for multi-master parallel-bus systems.
`
`1997 Oct 21
`
`13
`
`Lenovo
`Ex. 1009 - Page 13
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`LONG-DISTANCE MODE
`6.12.2
`The long-distance mode provides the possibility of
`longer-distance serial communication between parallel
`processors via two I2C-bus controllers. This mode is
`selected by setting ES1 to logic 1 while the serial interface
`is enabled (ESO = 1).
`In this mode the I2C-bus protocol is transmitted over
`4 unidirectional lines, SDA OUT, SCL IN, SDA IN and
`SCL IN (pins 2, 3, 4 and 5). These communication lines
`should be connected to line drivers/receivers
`(example: RS422) for long-distance applications.
`Hardware characteristics for long-distance transmission
`are then given by the chosen standard. Control of data
`transmission is the same as in normal I2C-bus mode. After
`reading or writing data to shift register S0, long-distance
`mode must be initialized by setting ESO and ES1 to
`logic 1. Because the interrupt output INT is not available in
`this operating mode, synchronization of data
`transmission/reception must be polled via the PIN bit.
`Remarks:
`Before entering the long-distance mode, ENI must be
`set to logic 0.
`When powering up an PCF8584-node in long-distance
`mode, the PCF8584 must be isolated from the 4-wire
`bus via 3-state line drivers/receivers until the PCF8584
`is properly initialized for long-distance mode. Failure to
`implement this precaution will result in system
`malfunction.
`
`6.12.3 MONITOR MODE
`When the 7-bit own address register S0' is loaded with all
`zeros, the I2C-bus controller acts as a passive I2C monitor.
`The main features of the monitor mode are:
`
`Product specification
`
`PCF8584
`
`— The controller is always selected.
`— The controller is always in the slave receiver mode.
`— The controller never generates an acknowledge.
`— The controller never generates an interrupt request.
`— A pending interrupt condition does not force SCL LOW.
`— BB is set to logic 0 after detection of a START condition,
`and reset to logic 1 after a STOP condition.
`— Received data is automatically transferred to the read
`buffer.
`— Bus traffic is monitored by the PIN bit, which is reset to
`logic 0 after the acknowledge bit of an incoming byte has
`been received, and is set to logic 1 as soon as the first
`bit of the next incoming byte is detected. Reading the
`data buffer S0 sets the PIN bit to logic 1. Data in the read
`buffer is valid from PIN = 0 and during the next 8 clock
`pulses (until next acknowledge).
`— AAS is set to logic 1 at every START condition, and
`reset at every 9th clock pulse.
`
`7 SOFTWARE FLOWCHART EXAMPLES
`7.1
`Initialization
`The flowchart of Fig.5 gives an example of a proper
`initialization sequence of the PCF8584.
`
`Implementation
`7.2
`The flowcharts (Figs 6 to 9) illustrate proper programming
`sequences for implementing master transmitter, master
`receive, and master transmitter, repeated start and master
`receiver modes in polled applications.
`
`1997 Oct 21
`
`14
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`Lenovo
`Ex. 1009 - Page 14
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`PCF8584 resets to
`slave receiver mode
`
`parallel bus interface
`determined by
`PCF8584 (80XX/68XXX)
`
`START
`
`reset minimum
`30 clock cycles
`
`send byte 80H
`
`send byte 55H
`
`send byte A0H
`
`send byte 1CH
`
`send byte C1H
`
`initialization of
`PCF8584 completed
`
`delay: wait a time
`equal to the longest I2C
`message to synchronize
`BB-bit. (multimaster
`systems only
`
`END
`
`A0 = HIGH enables data transfer to/from
`register S1
`
`power-on
`address line A0
`
`A0 = LOW Access to all other registers
`defined by the bit pattern in
`register S1
`
`A0 = HIGH
`
`A0 = LOW
`
`A0 = HIGH
`
`A0 = LOW
`
`A0 = HIGH
`
`Loads byte 80H into register S1'
`i.e. next byte will be loaded into register S0'
`(own address register); serial interface off.
`
`Loads byte 55H into register S0';
`effective own address becomes AAH.
`
`Loads byte A0H into register S1, i.e. next byte
`will be loaded into the clock control register S2.
`
`Loads byte 1CH into register S2;
`system clock is 12 MHz; SCL = 90 kHz.
`
`Loads byte C1H into register S1; register enable
`serial interface, set I2C-bus into idle mode;
`SDA and SCL are HIGH. The next write or read
`operation will be to/from data transfer register
`S0 if A0 = LOW.
`
`On power-on, if an PCF8584 node is powered-up
`slightly after another node has already begun an
`I2C-bus transmission, the bus busy condition will
`not have been detected. Thus, introducing this
`delay will insure that this condition will not occur.
`
`Fig.5 PCF8584 initialization sequence.
`
`1997 Oct 21
`
`15
`
`Lenovo
`Ex. 1009 - Page 15
`
`

`

`Philips Semiconductors
`
`I2C-bus controller
`
`Product specification
`
`PCF8584
`
`START
`
`read byte from S1 register
`
`A0 = HIGH
`
`yes
`
`is bus busy?
`(BB = 0?)
`
`PCF8584 remains in
`master transmitter
`mode if R/W bit of
`'slave address' = 0
`
`no
`send byte 'slave address'
`
`A0 = LOW
`
`Load 'slave address' into S0 register:
`'slave address' = value of slave address
`(7-bits + R/W = 0). After reset, default = '0'
`
`send C5H to control
`register S1
`
`A0 = HIGH
`
`Load C5H into S1. 'C5H' = PCF8584 generates
`the 'START' condition and clocks out the slave
`address and the clock pulse for slave acknowledgement.
`Next byte(s) sent to the S0 register will be immediately
`transferred over the I2C-bus.
`
`n = 0 (data byte counter);
`m = number of data bytes
`to be transferred
`
`read byte from S1 register
`
`Poll for transmission finished.
`
`A0 = HIGH
`
`no
`
`PIN bit = 0?
`
`yes
`slave
`acknowledged?
`(LRB = 0?)
`
`yes
`
`n = m
`
`no
`n = n + 1
`
`send byte 'data'
`
`transmission
`completed
`
`yes
`
`A0 = LOW
`
`Load 'data'
`into bus
`buffer register S0;
`data is transmitted.
`
`send byte C3H
`
`A0 = HIGH
`
`Load C3 into the