(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY(PCT)
`
`(19) World Intellectual Property
`Organization
`International Bureau
`
`
`
`
`oeLy
`SyAIPOT
`Q
`
`
`(43) International Publication Date
`19 February 2004 (19.02.2004)
`
`(10) International Publication Number
`WO 2004/015764 A2
`
`(51) International Patent Classification’:
`
`HOI1L 23/00
`
`(21) International Application Number:
`PCT/US2003/025048
`
`(22) International Filing Date:
`
`8 August 2003 (08.08.2003)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`(30) Priority Data:
`60/402,112
`
`8 August 2002 (08.08.2002)
`
`US
`
`(71) Applicant and
`[US/US]; 8010 Bethel
`(72) Inventor: LEEDY, Glenn, J.
`Church Road, Saline, MI 48176 (US).
`
`(74) Agent: MUIR, Michael, P.O. Box 2187, Cupertino, CA
`95015-2187 (US).
`
`(81) Designated States (national): AE, AG, AL, AM,AT, AU,
`AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ,
`DE, DK, DM, DZ,EE, ES, FI, GB, GD, GE, GH, GM, HR,
`HU,ID,IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR,
`LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ,
`NO, NZ, PL, PT, RO, RU, SD, SE, SG, SL, TJ, TM, TR,
`TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZM, ZW.
`
`(84) Designated States (regional): ARIPO patent (GH, GM,
`KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZM, ZW),
`Eurasian patent (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM),
`European patent (AT, BE, BG, CH, CY, CZ, DE, DK, EE,
`ES, FI, FR, GB, GR, HU,IE, IT, LU, MC, NL, PT, RO,
`SE, SI, SK, TR), OAPI patent (BF, BJ, CF, CG, CI, CM,
`GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
`
`Published:
`
`without international search report and to be republished
`upon receipt of that report
`
`bor two-letter codes and other abbreviations, refer to the "Guid-
`ance Notes on Codes and Abbreviations" appearing at the begin-
`ning of each regular issue of the PCT Gazette.
`
`(54) Title: VERTICAL SYSTEM INTEGRATION
`
`
`
`
`
`
`
`4/015764A2|IIMIMNINAMETMTATMATTAA
`
`& (57) Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and
`MEMStechnologiesinto a single integrated circuit die or component and wherein the individual device layers used in the VSI fab-
`rication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily
`limited in its use to a specific application. The VSI method of integration lowersthe cost difference between lower volume custom
`electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and
`fabrication costs.
`
`Lenovo
`
`Ex. 1045 - Page 1
`
`Lenovo
`Ex. 1045 - Page 1
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`Vertical System Integration
`
`Thediversity of circuit function and operational requirements that underlay the implementation of a broad range of
`integrated circuit applications including what is commonly referred to as a SoC [System on a Chip] demand widely
`varying semiconductor fabrication processes and/or technologies without further consideration being givento the
`integration of optical and MEMStechnologies with those semiconductor technologies. Limitations on the electronic
`industry’s capability to meet these ever greater demands has madethe implementation of numerous integrated
`circuit and SoC products impossible or beyond acceptable manufacturing costs.
`
`The Vertical System Integration (VSI) invention herein is a methodfor integration of disparate electronic, optical
`and MEMStechnologies into a single integrated circuit die or component and wherein the individual device layers
`used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple
`application use and notnecessarily limited in its use to a specific application. The VSI method ofintegration lowers
`the cost difference between lower volumecustom electronic products and high volume generic use electronic
`products by eliminating or reducing circuit design, layout, tooling and fabrication costs.
`
`The VSI invention achieves its novel methodsofintegration through high precision alignment and stacking of
`componentlayers,fine grain vertical interconnections, thin flexible circuit substrates fabricated using stress-
`controlled dielectrics and low temperature component layer bonding. The VSIintegration methods are fabrication
`methods are independent ofthe fabrication process methodsused in electronic or optical circuit fabrication or
`MEMSfabrication.
`
`The VSI invention enables the integration systems or subsystems as a single die or VSIIC_ which would otherwise
`be collections of multiple planar ICs, optical ICs, passive circuit devices and or MEMS. A VSI IC is a stack of
`closely coupled device or componentlayers the majority of which are less than 50pm thick andtypically less than
`25m thick. The VSI invention for vertical integration fabrication ofplanar electronic [passive andactive], optical
`or MEMSdevice layers enables on demandfastturn circuit fabrication through the use of an inventory ofpreviously
`fabricated generic VSI IC or device layers in combination of various proprietary IP generic device layers to achieve
`custom circuitry which, heretofore, would require at a minimum a newcircuit design, layout and masking before
`consideration ofthe planar circuit process integration incompatibility of various device elements.
`
`The VSI fabrication methods enable significant cost and power reduction and performance enhanéement through
`higher levels ofintegration with highercircuit yields than are presently possible with sftanar circuit fabrication
`processes. VSI IC device layers are interconnected by high density vertical intereénnections which are scalable so
`that they can be compatible with the on going decreases ofcircuit fabrication: geometries used in horizontal
`interconnectionsof the planar device layers. The VSI method for high density vertical interconnection is enabled
`through wafer to wafer bonding alignment methods capable ofprecisions of less than 25nm.
`
`Lenovo
`
`Ex. 1045 - Page 2
`
`Lenovo
`Ex. 1045 - Page 2
`
`

`

`WO 2004/015764
`PCT/US2003/025048
`The VSIfabrication methods enable the integration as one IC or die thatare currently system assemblies of discreet
`circuits with the benefit that performancelimiting circuit interconnect structures such as long on on-IC
`interconnections, IC carriers and sockets, PCBs and PCB edge connectors are eliminated. The VSI invention
`enablesthe reuse ofpost fabrication or inventory circuit device layers for multiple IC applications. The primary
`benefits ofthe VSI technology is a reduction in complexity ofIC manufacturing, testing, packaging and an increased
`in circuit yieldresulting in a nominal reduction in manufacturing costs ofapproximately10x and commensurate with
`an approximate nominal 5x increases in net circuit operating performance.
`
`The VSIinvention enables the implementation of SoC circuits which presently cannot be manufactured for the
`commercial or consumer markets due to technological or manufacturing costs limitations. This is before
`consideration ofthe present high costs associated with custom circuit tooling, large die size or the low production
`“quantities,
`
`BACKGROUNDofthe INVENTION
`
`1.
`Field of the Invention
`The present‘invention relates to methods for making closely coupled closely aligned stacked integrated electronic
`circuits, optical circuits and MEMS. In particular, the present inventionrelates to methods specific to fabrication
`integration, yield enhancement, performance enhancement, power dissipation reduction and cost reduction.
`2.
`State of the Art
`;
`Manufacturing Integrated Circuit [IC] methods are most notable for an exponential rate in the integration
`progression ofelectronic devices per unit area, consistently doubling approximately every 18 months over a short
`forty year history. These manufacturing methods are remarkable for their abilities ofincreasing circuit performance
`while simultaneously reducing circuit cost, power andsize, and as a result ICs have contributed in no small measure
`to today’s modern way oflife.
`
`The integration progression has repeatedly enabled the making ofICs that were notpossible or practical only a few
`years earlier. What before prevented the practical implementationofcircuits with 100,000 transistors due to
`excessivepowerdissipation or low fabrication yields, the integration progression has now enabledpractical yields of
`circuits with 100,000,000 transistors and at much lower powerdissipations despite the dramatic increase in transistor
`count. The integration progression has made possible the expectation that [Cs with more than 1 billion transistors
`will be in wide spread commonuse within the next three to four years.
`
`The ultimate and widely understood objective ofthe ICintegration progression is to reduce all electronic systems or
`subsystems composed ofmultiple ICs to one IC. This ultimate IC is often commonly referredto as a SoC [System
`on Chip]. Theresult ofthis objective isever lower cost ofmanufacturing, higherperformance, andhopefully
`therefore, a greater end userutility and socialbenefit. FIG. 1 showsincross section aconventional planar IC
`
`2
`
`Lenovo
`
`Ex. 1045 - Page 3
`
`Lenovo
`Ex. 1045 - Page 3
`
`

`

`WO 2004/015764
`PCT/US2003/025048
`composed ofnumberofIP [Intellectual Property] circuit blocks 1a which are interconnected by numerouslayers of
`horizontal metal interconnect or wiring 1b.
`
`Electronic systems and subsystems made from assemblies of separate planar ICs are performance or cost reduction
`limited foremost by the implementation meansfor off-circuit or off-chip interconnections or I/Os. The performance
`and cost reduction limitations due to IC I/O result from manufacturingrestrictions in the number ofI/Os an IC may
`have, the cost ofpackaging,the significantly lower transmission performance of off-circuit connections versus on-
`circuit connections and the higher power dissipation required for off-chip signal transmission. Further, there is not
`presently planar IC fabrication technology that will allow the integration onto one planarIC for all of the
`significantly different IC fabrication processes used to makethe electronic components ofwidely used products such
`as PCs, PDAsorcell phones. Thisis likely to remain so for the foreseeable future, because past demandfor greater
`capabilities from such electronic products has resulted in greater divergence ofthe IC fabrication processes used to
`implementthe various types of ICs from which they are made.
`
`The usefulness ofthe integration progression is now strongly challenged by the growing complexity in the design,
`and logical and physicalverification developmentandtest efforts required to bring ICs to market. The wide spread
`incorporation ofpreviously designed or off the shelf logic functionsreferred to as IP [Intellectual Property] is an
`example ofefforts being taken to address IC design and development complexity. However, the usage of ever
`greater numbersof IP placements across an IC hasresulted in greater logical, physical and manufacturing
`interconnection complexity.
`
`The integration progression rate has changed the relationship ofthe primary cost structure components for making
`ICs. The cost oftesting ICs is now approaching and in a numberof cases exceeding IC fabrication cost and the cost
`ofIC packaging ranging from 25% to several times IC fabrication cost. The cost dominanceoftest and packaging
`over IC fabrication increases with each generation of IC fabrication technology. It is becoming clear that IC
`manufacturing methods that reduce through IC integration techniques the cost of test and packaging are of most
`
`importance.
`
`The integration progression is presently challenged by the need for methods to integrate as a single die not only
`active electronics, but also passive electronic devices, optical devices and MEMS [Micro-Electro-Mechanical
`Systems]. This need is particularly evident in networking and telecommunication equipment where the switching of
`optical signals through the conversion ofoptical signals to electronic and back,to optical or electronically controlled
`MEMSofoptical mirrors are used. Butalso in consumerproducts suchas video devices that use imaging arrays
`which needhigherintegration of processing electronics and memory or wireless communication devices which need
`greater integration of analog and passivecircuitry.
`
`Theprimary drivers ofthe integration progression of planar IC manufacturing have been circuit feature size
`reduction through fabrication process methods and increased wafer or substrate diameter. Volume production
`process fabrication methods for the dominate CMOS semiconductor technology has presently reached feature sizes
`
`3
`
`Lenovo
`
`Ex. 1045 - Page 4
`
`Lenovo
`Ex. 1045 - Page 4
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`of .12um [120nm], and wafersizes of300mm [12 inches]. Methods for forming stacked ICs or stacked IC
`structures have been demonstrated and are expected to become one moreofthe primary drivers ofthe IC integration
`
`progression.
`
`IC stacking methods can be broadly classified as:
`
`1. Package driven stacked ICs.
`2. Process driven [design and fabrication] stacked closely coupled ICs.
`
`The stacking of ICs through various packaging methods or package driven stacking has a long and varied
`application history that goes back at least twenty years. A recent article published in the IEEE Spectrum entitled
`“Packages Go Vertical” by Harry Goldstein, August 2001, pages 46-51, is one representative summary ofthe more
`recent methods of 3D packagingofIntegrated Circuits. The primary benefit ofpackage driven stacking of ICs is
`reduced physical volume, implemented through the use of conventional ICs with various methodsof forming
`peripheral connections from the I/O contacts of each IC to a commonset of termination contacts the package
`envelop enclosing the ICs.
`
`The stacking ofICs through process drive methods, typically requires custom designed ICs and wafer level
`processing steps. The primary benefits ofprocess driven IC stacking are increased performance with simultaneous
`reductions of cost, size and power. Process driven stacked ICs can be generally characterized by the following
`
`processsteps:
`1. Wafer level bonding with a bonding material thickness of a few micronsorless.
`2. Thinning of wafercircuit layers to less than 50m andtypically less than 25m and less thanl5pm.
`3. Vertical through the circuit layer substrate interconnections or interconnectionsthat are internal to the
`IC stack.
`
`Process driven wafer stacking fabrication in the above mannerwill herein also bereferred to as Closely Coupled
`stacked integrated circuits. The Closely Coupled stacked integrated circuit layers ofthe invention herein are thinned
`to facilitate the fabrication offine grain vertical interconnections passing through the circuit layers and substantially
`flexible, and wherein these layers are preferably fabricated using low stress or stress controlled dielectric materials.
`The primary objective of closely coupled wafer stacking is to enhance the integration progression of IC fabrication
`beyondthat possible with existing planar wafer process fabrication methods and wafer diameter. Closely coupled
`stacked IC prior art by the inventor and referred to as 3DS [Three Dimensional Structures] are 5,915,167, 6,208,545,
`6,133,640, 6,551,857; 6,563,224, 5,985,693 and 5,654,220.
`
`Closely coupled wafer bonding requires wafer to wafer alignmentprior to bonding. Equipmentpresently available
`has the capability for +1 wm wafer to wafer alignment. By comparison horizontal interconnection minimum pitchis
`.15 wm [150nm] with current state ofthe art semiconductor processes. The horizontal routing efficiency through
`vertical interconnections is determined by wafer to wafer alignment, and is fundamentally importantto the scaling of
`fine grain vertical interconnections to maintain compatibly with reducing horizontal interconnection geometries.
`
`4
`
`Lenovo
`
`Ex. 1045 - Page 5
`
`Lenovo
`Ex. 1045 - Page 5
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`Thestate ofthe art for completed or fabricated planar ICs has and presently results in the expectation that the utility
`of a fabricated IC does notallowits reuse for subsequentIC integration in a single die or single IC. This is to say
`that subsequent integration ofpost-fabricated planar semiconductor circuitry with other fabricated ICs that would
`result in device and interconnection integration densities that are the same or similar to any ofthe planar ICs being
`integrated, and therefore, providing the well known attendant benefits of single IC integration, is no longerpossible.
`Therefore, any andall subsequentcircuit design changes or additions [placementofcircuitry or horizontal
`interconnect routing layers] to a completed planar IC requires the IC be remade, requiring at a minimum revalidation
`ofelectrical and functional operation ofthe circuit, the remaking of mask tooling, circuit fabrication and in most
`cases the obsolescence ofpreviouscircuit inventory. This is a clear and significant restriction on the control of cost
`in the development, manufacturing and inventory management ofplanar ICs. Conversely, having the ability to
`inventory fabricated or complete circuitry which can subsequently be integrated at the IC or die level presents a
`opportunity for cost savingsthat affects all aspects of IC development and manufacturing, and extends the range of
`intended end use applications beyond that presently possible.
`
`PLANARCIRCUIT INTEGRATION PROGRESSION LIMITATIONS
`
`There presently exists numerouslimitations to the integration progression ofplanar ICs, someoftheselimitations
`which are:
`
`[1] Die size in fabrication, complexity and performance.
`
`The IC Integration Progressionis limited by die size. The die size ofplanar circuits is limited by current
`semiconductor fabrication lithographic technology. Die size fabrication lithographic limitations stem from the
`maximum imaging field size ofpresent semiconductor lithographic processing equipment. The often sought end
`objective for most electronic products or applications composed ofmultiple ICsis to integrate the ICs into a single
`chip solution referred to generically as a SoC [System on Chip]. The limits ofcircuit integration manufacturing are
`feature size andlithographic stepperreticle size [maximum lithographic image size] and yield. At this point in time
`production IC feature size is approaching .12ym and stepperreticle demagnification size is approximately 25mm by
`30mm which enables presently a die size limit of approximately one square inch.
`
`Larger planar ICs, those greater than 100mm”,that are fabricated with lithographic processes less than .15pm are
`limited in performanceby the distances acrossthe surface ofa die or chip of suchsize resulting in the use of
`additional circuitry to amplify signals that must travel these greater distances. Adding further to the complexity of
`long signalline propagation is the use oflower voltage levels [such as 1.5v when using .15m fabrication
`technology] whichresult in lower signal strength, and stronger parasitic electronic effects due to the use of smaller
`lithographic geometries. And further as a result of large ICs and smaller lithographic geometries, skewed timing of
`signals which results from the varying distances of circuit sources makes an ever present demand for more precise
`
`5
`
`Lenovo
`
`Ex. 1045 - Page 6
`
`Lenovo
`Ex. 1045 - Page 6
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`circuit timing analysis and attendantcircuit design compensations necessary to reduce planarcircuit signal skew
`sufficiently to bring the circuit into acceptable operating ranges withouttoo great a reduction in net circuit
`performance.
`
`[2] Levels of interconnections and substrate leakagelimit device fabrication density and the use of
`complex IP blocks.
`
`The IC Integration Progression has now reached a minimum circuit device feature size of .15m [150nm] in volume
`production. The end ofthe IC integration progression is now anticipated to be something approaching a feature size
`of approximately 20nm. Anincreasein circuit density of approximately 36 times. However, such circuit density
`gains will be difficult to achieve or to implementtheir effective use without additional horizontal interconnect layers
`and new methods ofpowerreduction orutilization necessary to drive a greater numberoflow voltage signals long
`distances over the surface ofplanarcircuits.
`In order to implementgreater circuit densities resulting from smaller
`circuit devices, a comparable reduction in the geometries of interconnections and an increase in the number of
`interconnection levels must be achieved. Reduction in powerdissipation is necessary to prevent powerdissipation
`from becominga limitation on IC Integration Progression. Reduction in transistor subsirate leakage could reduce
`current power dissipation by approximately 50%.
`
`The IC Integration Progressionis limited by the numberofinterconnection levels that can be usedin a circuit
`design. The numberofhorizontal wiring levels of a planar IC is limited by manufacturing processes, presently nine
`[9] layers, which in turn limit the integration density of an IC design. Smaller active device circuit geometries and
`the frequent incorporation of hardwired Intellectual Property [IP] in the design of a circuit increases the wiring or
`interconnection complexity between those IP circuit elements to each other andtherest ofthe circuitry of an IC.
`The design ofmostICs and certainly most large complex ICs incorporate IP circuitry into their circuit designs in
`orderto save the time and humanresourcesthat would otherwise be required in duplicative development of such
`circuit IPs. Increased die size and greater use of IPs results most often in an increase in the planar [horizontal]
`routing interconnection complexity. This interconnect complexity results in more layers of interconnections
`necessary to complete a circuit’s local and global wiring networks. This interconnect complexity is proportional
`circuit size, resulting in higher manufacturing costs.
`
`The integration progression is physically accomplished by the making ofever smaller circuit devices and through
`the fabrication of denser and denserinterconnectionsor wiring. Design of most planar circuits posses the challenge
`ofrouting interconnections from onecircuit block or functional group oftransistors to another circuit block and then
`typically to the portion ofthe die ofthe circuit where I/O pads or contacts are formedforoff circuit or external
`connections. These horizontal interconnections take the form of successivelayersfirst interconnecting adjacent
`circuit devices, then progressing to the interconnection of ever moredistantcircuit blocks ofthe circuit. These
`interconnection layers are themselves connectedby structures called vias, or wiring connections typically of less
`than 1m in length. These horizontalcircuit interconnections have provedto be the greatest challenge in the design
`oflargecircuits resulting in a non-stop evolution ofmore sophisticated automatic interconnect routing software tools
`
`6
`
`Lenovo
`
`Ex. 1045 - Page 7
`
`Lenovo
`Ex. 1045 - Page 7
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`for completing whatis called the physical IC design, and the addition ofmore and more interconnect layers
`presently at nine [9] and anticipated to exceed twelve [12] by 2005.
`
`[4] Limits of SoCs, ASICs and FPGAs.
`
`The IC Integration Progression hasleadto efforts to incorporateall the ICs of a system onto one chip,resulting in
`the reference to such ICs as SoCs [System on Chip]. However, achieving the SoC goalis greatly restricted by the
`limited ability ofthe semiconductor industry to fabricate single ICs consisting of multiple semiconductor processes
`[such as .5ym analog and .18pm logic or DRAM processes] or multiple semiconductor technologies [such as SiGe
`and GaAs, InP, GaN,etc.].
`
`Similar problemsface the moretraditional and familiar ASIC and FPGA [Field Programmable Gate Arrays] or
`CPLD [Complex Programmable Logic Devices] products. Thelimitations of ASICs are design complexity due to
`their relentless growth in size, and a long and costly ofproduct development process. The well established benefit
`of ASICintegration has now also becomea limitation that requires re-verification and retooling ofthe entire circuit
`irregardless ofthe size of a design change and followed by prototype fabrication delays measured in months.
`
`The alternative to ASICs are FPGAsor CPLDswith the advantage of a very short product developmentprocess,but
`with the distinct disadvantages versus ASICsof higherunit circuit cost, lower performanceand lower gate density.
`The lower performance and lower gate density of FPGAs follows from the interconnect complexity required to
`support programmable function blocks and the on chip programmable routing interconnections for programming of
`the function blocks.
`
`The development of SoCs, ASICs and FPGAscircuits has becomeincreasing capital intensive in terms offacility
`support and large numbers ofhighly trained personnel. The IC integration progression can only guarantee that this
`trend will continue, making the developmentofthese circuits the exclusive domainofa few large established
`companies with the result of lessening product diversity, competition and the well established economic vitality that
`flows from the innovation of small enterprise. The result ofthe current trendsofthe IC integration process is the
`loss of greater diversity due to the growing capital barrier to market entry, this cannotbein the long term public best
`interest.
`
`All planar circuits are made from a custom maskset, where a mask set consists oftypically 16 to 32 lithography
`masks. A single changeto onecircuit device or the its wiring connectionsin a circuit design of 10s ofmillions of
`circuit devices will result in the remaking of severalor all masks for a planar IC. This in turn results in a
`requirementfor timing simulation analysis ofthe circuit to determine anew it operating characteristics and if a
`failure condition has been created by the change. The operational simulation process or IC physical validation
`process presently requires the majority ofdevelopmenteffort in the design of most ICs. This effort is growing with
`the rate of integration progression.
`
`Lenovo
`
`Ex. 1045 - Page 8
`
`Lenovo
`Ex. 1045 - Page 8
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`[5] Intellectual Property
`
`[5] IP [Intellectual Property] in the semiconductor circuit design industry typically refers to previously designed
`integrated circuit blocks that can be incorporated into a circuit design with only modestlevels of additional
`engineering design effort. IPs are often an item oftrade and are leased for incorporation into a circuit design. Some
`examples of IPs are microprocessors, DSPs, PCIbus interfaces andarithmetic functions. The valueofIP isits
`ability to reduce IC developmentcosts by its use, however, the reuse of IP only offers circuit design cost savings and
`do not extend savings to IC fabrication.
`
`[6] IC Inventory Management and Reuse
`
`Circuit design changes to an ASIC or any IC results in the need to make new masksand potentially the creation of
`devalued or obsolete [valueless] inventory ofthose circuits made from the current and now outdated mask set. A
`design change requires the remaking of one or more masks. New masks are expensive, andin large planarcircuit
`designs made with complex processes they also can result in the introduction ofnew circuit defects, or due to large
`mask size reduced IC yield. ASIC inventory is a serious problem which comesin three forms: wafers, bare die and
`packagedcircuits. Circuit inventory is most often held in wafer form for cost reasons, it represents unfinished goods
`at a lower value but can be quickly turnedinto the finished goods ofbare die or packaged die, however, circuit wafer
`inventories often take several monthsto replenish. Thisis a difficult unfinished goods management challenge.
`Oncecircuit wafers are fabricated, a change in IC demandora circuit design change can renderthese circuit wafers
`oflittle or no value. Theability to reuse such obsolete circuit wafers is often not an option even though the majority
`ofthe area of each die on the waferis often unaffected bya circuit design change; this being even more the case the
`larger the planarcircuit design. The challenge for IC integration is to reduce mask complexity forlarge circuit
`designs andto find methods for reuse of unaffected circuit area due to design changes.
`
`[7] Power Limitations Due to Substrate Leakage and I/Os
`
`Powerdissipation oflarge ICs have increasedsignificantly with the Integration Progression such that high
`performancecircuits exceeding 100 watts ofpower. Such high thermalheating of ICslimits the performance and
`useful life ofthe IC. The primary sources of IC powerdissipation for most high performance ICs is from substrate
`leakage and high I/O counts. Substrate leakageis the passage ofcurrent between source and drain while the
`transistoris in the offstate. Substrate leakageis increasing with decreasingcircuit feature size and is expected to be
`more than 30% of IC powerdissipation for fabrication processes below 130nm. The powerdissipation from I/O
`drivers are well known, butthe increase in the numberof I/Os for advancedICs is expected to exceed 1,000 by 2004
`and is a limit on the useofthe IC technology.
`
`[8] Circuit Yield Enhancement
`
`Lenovo
`
`Ex. 1045 - Page 9
`
`Lenovo
`Ex. 1045 - Page 9
`
`

`

`WO 2004/015764
`
`PCT/US2003/025048
`
`ICs of greater than 100mm‘often resort to redundantorspare circuit yield enhancement methods. Such methods
`have proven successful in only a few higher volume production circuit types such as DRAMs and PLDs. These
`
`methods have beentried with little success in planar custom logic circuits by such companies as TRWin the 1980s
`
`and Trilogy Corporation founded by Dr. Gene Amdahl in the 1970s. These attempts failed due primary to the
`
`limitation of circuit design automation software tools and available capacity ofhorizontal interconnections. The
`
`integration progression beyond .15um [150nm]circuit device feature size will reduce the size or footprint of large
`
`and complex IP circuit functions such as microprocessors, DSPs or graphics processors to enable sparing as the
`
`simple solution to planar circuit defect resolution, however, the design complexity of interconnection layout and the
`capacity of horizontal interconnectionisstill a challenge for generalized implementation methods for these types of
`circuits.
`
`The testing of IC under normal andstressed conditions is challenging problem. External testing of ICs by ATE
`
`{Automatic Test Equipment] is presently the primary meansof determiningif a circuit is defective. This testing
`
`procedure is complex and lengthy and canresult in failure to detect a defective operating condition.
`
`Further, mostcircuits under go a procedure called burn-in. Various failure conditions of an IC only occur under
`
`temperature or voltage stressing, or after some lengthy period of operation. The burn-in procedure is the means used
`
`to provide this type of testing, however, the burn-in procedurelacksthe full speed functionaltesting procedures of
`
`ATEtesting, and therefore, can result in failure to detect a defective operating condition.
`
`[9] Lithographic Limitations
`
`Production semiconductorlithographic tools use masks in the form of imagingreticles which image or print one or
`
`more die onto a wafer perlithographic exposure. Lithographic exposures are repeated until the wafer or substrate is
`
`completed. The reticle is limited in its ability to image circuitry on a wafer in one exposure to approximate area of
`
`25x30mm, and therefore, the largest planar IC that can be madeis limited to the maximum imaging area ofthe
`
`reticle of the lithographic system. The production tooling for making an IC consists of a set of masks. The number
`
`of masks per mask set is dependent on the complexity of the process being use and nominally vary from 16 to 32
`
`masks. Any design changeto a circuit results in the remaking of one or masks of the ICs mask set. Changing the
`
`placement of an IP circuit block or interconnection busing structure will result in the remaking ofall of the masks of
`
`the ICs mask set. The cost of making an IC maskset have increased sharply with mask geometries below 150nm,
`
`andis limiting the development of ICs with smaller market volumes.
`/
`
`[10] MEMS[Micro-Electro Mechanical Systems]
`
`MEMSdevicesare a rapidly developing manufacturing technology which use semiconductor fabrication processes
`
`but has only limited compatibility for integration with IC fabrication processes and technologies. MEMStake the
`
`form of such devices as accelerometers, DMD [Digital Mirror Devices], video imaging sensors, micro-switches and
`
`Lenovo
`
`Ex. 1045 - Page 10
`
`Lenovo
`Ex