United States Patent (19)
`Ogawa
`
`11)
`45
`
`Patent Number:
`Date of Patent:
`
`4,740,922
`Apr. 26, 1988
`
`54 SEMICONDUCTOR MEMORY DEVICE
`HAVING A READ-MODIFY-WRTE
`CONFIGURATION
`75 Inventor: Junji Ogawa, Tokyo, Japan
`73 Assignee: Fujitsu Limited, Kawasaki, Japan
`21 Appl. No.: 788,398
`22 Filed:
`Oct. 17, 1985
`30
`Foreign Application Priority Data
`Oct. 23, 1984 JP
`Japan ................................ 59.22,165
`
`51) Int. Cl." .............................................. G11C 11/40
`52 U.S. Cl. ...............
`8 × 8
`365/189; 365/238
`58 Field of Search .......
`365/189, 230, 238;
`364/200
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,763,480 10/1973 Weimer ............................... 365/238
`4,272,829 6/1981 Schmidt et al. .
`4,276,609 6/1981 Patel .
`4,422,161 12/1983 Kressel et al. .
`1/1984 Kobayashi.
`4,429,375
`
`FOREIGN PATENT DOCUMENTS
`334662 12/1973 Austria .
`0040001 4/1980 European Pat. Off. .
`0056240 7/1981 European Pat. Off. .
`WO82/02615 8/1982 PCT Int'l Appl. .
`OTHER PUBLICATIONS
`European Search Report EP 85307600.8, Apr. 1986.
`Primary Examiner-Terrell W. Fears
`Attorney, Agent, or Firm-Staas & Halsey
`57
`ABSTRACT
`A semiconductor memory device having a read-modi
`fy-write (RMW) configuration suitable for modifying a
`large number of data with high speed and a simple cir
`cuit. The RMW configuration includes a data input and
`output circuit (11, 14, 16) for simultaneously storing or
`reading a plurality of data into or from the memory
`cells, a data output circuit (10, 12, 13) for serially read
`ing a plurality of data from the memory cells, and data
`modification circuits (15) for successively receiving the
`plurality of data from the data output circuit, modifying
`the received data if necessary and transmitting the mod
`ified data to the data input and output circuit.
`
`11 Claims, 8 Drawing Sheets
`
`
`
`Petitioner Ex 1018, p. 1
`BOE v. Samsung, IPR2024-00620
`
`

`

`U.S. Patent
`
`Apr. 26, 1988
`
`Sheet 1 of 8
`
`
`
`OGO NWOO
`
`4,740,922
`lnog
`
`NI
`
`Petitioner Ex 1018, p. 2
`BOE v. Samsung, IPR2024-00620
`
`

`

`U.S. Patent Apr. 26, 1988
`
`Sheet 2 of 8
`
`4,740,922
`
`Fig. 2
`
`He
`
`SR
`1 bit
`
`as-
`
`SR2
`bit
`
`al
`
`Fig. 3
`
`Fig. 4
`
`
`
`15
`
`152
`
`153
`
`Petitioner Ex 1018, p. 3
`BOE v. Samsung, IPR2024-00620
`
`

`

`U.S. Patent Apr. 26, 1988
`
`Sheet 3 of 8
`
`4,740,922
`
`E, D
`Fig. 5a
`... ))—
`Fig.5b
`Fig.5c Sout—Do—
`
`Fig. 6
`
`TR
`
`
`
`
`
`OO
`
`COLUMN O
`
`COLUMN
`
`
`
`
`
`
`
`
`
`
`
`COLUMN2
`
`SR255
`
`
`
`i
`
`Petitioner Ex 1018, p. 4
`BOE v. Samsung, IPR2024-00620
`
`

`

`
`US. Patent—Apr. 26, 1988 Sheet4 of 8 4,740,922
`
`U.S. Patent Apr. 26, 1988
`Sheet 4 of 8
`4,740,922
`
`
`
`Fig. 7
`
`PO2 PSRe2
`
`
`FROM
`
`Petitioner Ex 1018, p. 5
`BOEv. Samsung, IPR2024-00620
`
`Petitioner Ex 1018, p. 5
`BOE v. Samsung, IPR2024-00620
`
`

`

`US. Patent
`Apr. 26, 1988
`U.S. Patent Apr. 26, 1988
`
`
`
`Sheet5 of8
`Sheet 5 of 8
`
`4,740,922
`
`4,740,922
`
`Petitioner Ex 1018, p. 6
`BOEv. Samsung, IPR2024-00620
`
`Petitioner Ex 1018, p. 6
`BOE v. Samsung, IPR2024-00620
`
`

`

`US. Patent
`Apr. 26, 1988
`U.S. Patent Apr. 26, 1988
`
`Sheet 6 of 8
`Sheet 6 of 8
`
`4,740,922
`4,740,922
`
`
`
`
`
`COLUMNDEC
`
`Petitioner Ex 1018,p. 7
`BOEv. Samsung, IPR2024-00620
`
`Petitioner Ex 1018, p. 7
`BOE v. Samsung, IPR2024-00620
`
`

`

`U.S. Patent Apr. 26, 1988
`
`Sheet 7 of 8
`
`4,740,922
`
`SLVO O/1
`OO NW? O)
`
`
`
`
`
`
`
`
`
`s
`
`Petitioner Ex 1018, p. 8
`BOE v. Samsung, IPR2024-00620
`
`

`

`
`US. Patent—Apr. 26, 1988 Sheet8 of8 4,740,922
`
`U.S. Patent
`Apr. 26, 1988
`Sheet 8 of 8
`4,740,922
`
`030 NWN109
`
`Doutis)
`
`
`ROWDEC
`
`
` Dout,DIN
`s
`Fig.14
`
`a ee
`S3 Ivo O-1
`saivo O74
`OO NW (TOO
`950 NWN7109
`
`Petitioner Ex 1018, p. 9
`BOEv. Samsung, IPR2024-00620
`
`Petitioner Ex 1018, p. 9
`BOE v. Samsung, IPR2024-00620
`
`

`

`1.
`
`SEMCONDUCTOR MEMORY DEVICE HAVING
`A READ-MODIFY-WRITE CONFIGURATION
`
`5
`
`O
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to a semiconductor
`memory device and, more particularly, to a semicon
`ductor memory device for performing a high speed
`read-modify-write (hereinafter referred to as an RMW)
`operation for a large number of data.
`2. Description of the Related Art
`Demand has arisen for effectively writing image data
`in or reading image data from an image processing
`memory or the like and for effectively performing a
`high-speed RMW operation, i.e., the storage contents
`are read out from the memory, the read out data is
`modified, and the modified data is restored in the men
`ory. A typical RMW application is exemplified by color
`20
`inversion for inverting a color currently displayed on a
`display unit with a given relationship and providing
`pattern emphasis emphasizing a specific pattern.
`A conventional RMW scheme is applied in such a
`manner that data is read out using an RMW function of as
`a dynamic-random access memory (D-RAM) device,
`the read out data is modified by an external circuit, and
`the modified data is restored in the corresponding mem
`ory cell. However, the conventional RMW scheme
`requires a relatively long processing time defined by the
`30
`operating cycle of the D-RAM device, resulting in
`inconvenience.
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a
`35
`semiconductor memory device for performing a high
`speed RMW operation for a large number of data for
`selected memory cells.
`According to the present invention, there is provided
`a semiconductor memory device including: a random
`access memory cell array including a plurality of mem
`ory cells; and a RMW configuration. The RMW config.
`uration includes a data access circuit, operatively con
`nected to the memory cell array, and includes one or
`more register circuit arrays, each having a data input
`45
`and output circuit for simultaneously storing or reading
`a plurality of data into or from the memory cells, and a
`data output circuit for serially reading a plurality of data
`from the memory cells. The RMW configuration also
`includes one or more data modification circuits, each
`operatively connected to the corresponding register
`circuit array of the data access circuit, and, succes
`sively, receiving the plurality of data from the data
`output circuit, modifying the received data in a prede
`termined logical manner and transmitting the modified
`55
`data to the data input and output circuit. The data ac
`cess circuit may include a circuit for designating a pre
`determined range of data output from the data output
`circuit and data restore in the data input circuit, to
`perform a predetermined range of data modification.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Other objects and features of the present invention
`will be described below in detail with reference to the
`accompanying drawings, in which:
`65
`FIG. 1 is a block diagram of a semiconductor mem
`ory device according to an embodiment of the present
`invention;
`
`4,740,922
`2
`FIG. 2 is a circuit diagram of shift registers in the
`device shown in FIG. 1;
`FIG. 3 is a timing chart for explaining the operation
`of the shift registers shown in FIG. 2;
`FIG. 4 is a circuit diagram of a modifying circuit in
`the device shown in FIG. 1;
`FIGS. 5a to 5c are circuit diagrams showing modifi
`cations of the circuit of FIG. 4, respectively;
`FIG. 6 is a block diagram of a semiconductor mem
`ory device according to another embodiment of the
`present invention;
`-
`FIG. 7 is a circuit diagram showing connections be
`tween the shift register and a data bus in the device
`shown in FIG. 6;
`FIG. 8 is a timing chart for explaining the operation
`of the circuit arrangement shown in FIG.7;
`FIG. 9 is a circuit diagram of pointer shift registers in
`the device of FIG. 6;
`FIG. 10 is a timing chart for explaining the operation
`of the registers shown in FIG. 9;
`FIG. 11 is a circuit diagram showing a modification
`of the device shown in FIG. 6;
`FIG. 12 is a block diagram of a semiconductor mem
`ory device according to still another embodiment of the
`present invention; and
`FIGS. 13 and 14 are block diagrams of semiconduc
`tor memory devices according to other embodiments of
`the present invention, respectively.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIG. 1 is a block diagram of a semiconductor men
`ory device according to a first embodiment of the pres
`ent invention. The semiconductor memory device in
`FIG. 1 has a plurality of dynamic RAM (D-RAM) cells
`(MC) 1 arranged in a matrix form, a row decoder 5 for
`selecting word lines WL0 to WL255 of the memory cells
`in response to row address signals RA0 to RA7. A sense
`amplifier array 2 of sense amplifiers SAO to SA255 con
`nected to bit lines BL0 to BL255 and BL0 to BL255 is
`included along with a gate array 3 including 256 gates,
`a column decoder 4 for selecting one of the gates of the
`gate array 3 in accordance with column address signals
`CA0 to CA7. Also included are a data bus DB con
`nected to one gate of the gate array 3 with is selected by
`the column decoder 4 and an I/O amplifier 25 con
`nected to the data bus DB. This arrangement is the same
`as the conventional D-RAM configuration. The same
`operation as in the conventional D-RAM device can be
`also applied to the semiconductor memory device of the
`first embodiment. It should be noted that the D-RAM
`device of the first embodiment has a memory capacity
`of 64 kbits (=256 bitsX256 bits).
`The semiconductor memory device in FIG. 1 further
`has a data read shift register array 12 including 256
`series-connected shift registers SRA0 to SRA255 con
`nected to the bit lines BL0 to BL255 through a first trans
`fer gate array 10 including 256 transfer gates, and a data
`write shift register array 14 having 256 series-connected
`shift registers SRBo to SRB255 and connected to the bit
`lines BL0 to BL255 through a second transfer gate array
`11 including 256 transfer gates. An output amplifier 13
`is connected to the read shift register array 12. An out
`put signal SouT from the output amplifier 13 is supplied
`together with a modifying input signal SIN from a cen
`tral processor unit (CPU), not shown, to the modifying
`circuit 15. An output signal from the modifying circuit
`15 is supplied to the write shift register array 14.
`
`15
`
`50
`
`Petitioner Ex 1018, p. 10
`BOE v. Samsung, IPR2024-00620
`
`

`

`5
`
`O
`
`15
`
`4,740,922
`4
`3
`A typical example of the read and write shift registers
`The semiconductor memory device mentioned above
`performs an RMW operation for all shift registers. In
`SRA0 to SRA255 and SRBo to SRB255 of FIG. 1 is a
`general, however, the RMW operation is performed for
`two-phase ratio type shift register as shown in FIG. 2. A
`timing chart of the two-phase ratio type shift register is
`desired bit lines. An embodiment suitable for this appli
`illustrated in FIG. 3. In the shift register SR2, a value at
`cation will be described hereinafter.
`FIG. 6 shows an arrangement of a semiconductor
`a node N14 of the preceding stage of the shift register
`memory device according to a second embodiment of
`SR1 is transferred as master data, and a transistor Q22 is
`the present invention. Reference numeral 100 denotes a
`turned ON in response to a clock pulse P1 to receive the
`circuit corresponding to the D-RAM device (FIG. 1)
`master data at a node N21. When a voltage level at the
`including the memory cell array 1, the sense amplifier
`node N21 is set at logic “1”, the level at a node N22 is
`array 2, the gate array 3, the column decoder 4, the row
`inverted. In order to perform a slave transfer, a transis
`decoder 5, and the I/O amplifier 25 so as to schemati
`tor Q26 is turned ON in response to a clock pulse P2 to
`cally show the connections between the respective
`set the level at a node N23 to be equal to that at the node
`components with the bit lines in units of columns.
`N22. The signal level at a node N24 is inverted in accor
`A shift register array 21a is connected to the bit lines
`dance with the signal level at the node N23. Therefore,
`BL0 to BL255 through a transfer gate array 20a includ
`the data can be shifted bit by bit in each shift register.
`ing 256 transfer gates. The output terminals of the shift
`The operation of the semiconductor memory device
`register array 21a are connected to the corresponding
`in FIG. 1 will be described hereinafter. The D-RAM
`input terminals of an output gate array 22a including
`side is not synchronized with the shift register side and
`operates independently thereof. The D-RAM can be
`256 gates, i.e., transistors. The drains of the transistors
`20
`of the output gate array 22a are connected to a data bus
`accessed in a conventional manner. At the same time,
`DB. The data bus DB is connected to a modifying cir
`when the D-RAM is held in a nonaccess mode, an
`RMW operation can be performed in the following
`cuit 25a. A pointer shift register (PSR) array 23a is
`arranged to control the respective gates of the output
`a.
`gate array 22a. A column decoder 24a is arranged to
`In the RMW mode, a transfer instruction TR and a
`25
`load a value into the pointer shift register array 23a.
`read instruction R/W = 0 are supplied to a transfer
`Each shift register in the shift register array 21a may
`clock driver 16, and the driver 16 generates a clock
`be the same as that shown in FIG. 3. One arrangement
`signal TcLKA. The transfer gate array 10 is turned ON in
`representing the connections between the shift registers
`response to the clock signal TCLKA, so that data, on the
`SR1 and SR2, the output gate 22a, and the PSR and
`bit lines BL0 to BL255 connected to the accessed word
`line WLi, is simultaneously supplied to the read shift
`PSR2 is shown in FIG. 7. The timing chart of the ar
`register array 12. The data in the shift register array 12
`rangement of FIG. 7 is shown in FIG. 8. The data is
`shifted bit by bit in response to the clock signals P1 and
`is then consecutively read as an output signal SouT by
`the output amplifier 13, supplying the read signal SouT
`P2 in the same manner as in the first embodiment. Ac
`to the modifying circuit 15.
`cording to the second embodiment, in addition, the
`35
`contents in the shift registers appears on the data bus
`As shown in FIG.4, the modifying circuit 15 includes
`DB consisting of data buses SDB and SDB in response
`an amplifier 151 for amplifying the input signal SIN, an
`OR gate 152 for producing a logical OR of the signals
`to a pointer instruction signal PO; from the pointer shift
`register array 23a.
`SIN and SouT, and an amplifier 153 for amplifying an
`FIG. 9 is a circuit diagram of a part of the pointer
`output from the OR gate 152. The original signal (the
`40
`shift register array 23a. The n-th pointer shift register
`signal SouT) is logically ORed with the input signal SIN
`PSR consists of a depletion-type transistor Q56 and
`in the circuit of FIG. 4. However, the data modification
`enhancement-type transistors Q.57 and Q60 to Q65. Other
`is not limited to the logic sum (OR), but can be extended
`pointer shift registers are applied in the same way. FIG.
`to a logic product (FIG. 5a), a logical exclusive OR
`(FIG. 5b) or a simple inversion (FIG. 5c), etc.
`10 is a view of waveforms of a clock signal TCLK1 for
`45
`driving the pointer shift register array 23a. The clock
`The modified signal is stored in the write shift register
`pulse signal TcLK1 shown in FIG. 10 for driving the
`array 14. When the modified signals are loaded into all
`pointer shift registers includes a first pulse PE and a
`the shift registers, the transfer instruction TR and the
`second pulse NPE, which are phase-shifted by 180
`write instruction R/W = 1 are supplied to the transfer
`clock driver 16. The gate array 11 is turned ON in
`from each other.
`The operation of the pointer shift registers will now
`response to the clock signal TCLKB from the driver 16.
`The contents in the shift register array 14 are stored in
`be described. First, when the pulse PE is at a high level,
`it is assumed that an output SLn-1 at the (n-1)-th
`the memory cells connected to the above-mentioned
`pointer shift register PSR-1 is the high level or logical
`word line WLi.
`In this case, when the data in the memory cells is used
`'1', and all other outputs SLO to SL-2 and SL and
`55
`only for display, an output amplifier (not shown) con
`SL255 are at a lower level or logical "0". Due to the
`application of the high level voltage of the output
`nected to the end stage SRB255 of the shift register array
`14 serially outputs the data to be displayed on the dis
`SLn-1, the transistor Q64 in the n-th pointer shift regis
`play unit while the gate array 11 is kept OFF.
`ter PSRn is turned ON, with a resultant charging-up of
`node SP to the high level. By applying the high level
`As described above, a simultaneous high-speed RMW
`60
`operation can be performed for memory cells con
`signal at the node SP to a gate of a transistor Q75 in the
`pointer shift register PSR-1, the transistor Q75 is
`nected to a given word line.
`In the above embodiment, two shift register arrays
`turned ON, resulting in the low level at the node SP 1.
`are used for the RMW operation. However, the RMW
`The states at the node SP and SP are maintained as
`operation can be performed by a single shift register
`is when the pulse PE becomes low. When the pulse
`65
`array. In this case, the single shift register array is con
`NPE becomes high, the transistors Q62 and Q72 are
`nected to the word lines through a single transfer gate
`turned ON, applying the high level signal at the node
`array so as to achieve write/read access.
`SP to a gate of the transistor Q60 and the low level
`
`50
`
`Petitioner Ex 1018, p. 11
`BOE v. Samsung, IPR2024-00620
`
`

`

`10
`
`5
`
`4,740,922
`5
`6
`signal at the node SP-1 to a gate of the transistor Q70.
`circuit 25a together with the input signal SIN. In the
`The signals applied to the respective gates of the transis
`next cycle, the modified value is stored in the shift regis
`tors Q60 and Q70 are maintained if the pulse NPE be
`ter SRO, and at the same time the data in the shift regis
`comes low. Again, by applying a pulse PE having a
`ters SRO to SR-2 is shifted to the shift registers SR1 to
`high level to the pointer shift registers PSR and
`SR-1, so that the content of the shift register SR-2
`PSR-1, the signal levels at nodes SLn and SL-1 are
`appears on the data buses SDB and SDB.
`respectively rendered high and low. As a result, a
`The same modification operation as described above
`unique “1” a bit of data is transferred from the pointer
`is performed for n bits.
`shift register PSR-1 to the adjacent pointer shift regis
`In another mode of RMW operation, one of the
`ter PSR.
`pointer shift registers PSRoto PSR255 is set at logic “1”
`The transistors Q734 and Q73B prevent the application
`and both the shift register arrays 21a and 23a are shifted
`of the high voltage to a gate of the transistor Q70, to
`synchronously. During operation, n shift registers SR0
`securely maintain the node SL-1 at the low level. As
`to SR-1 store the same data which is a result of the
`the gate of the transistor Q60 is supplied with a suffi
`modification of the initially accessed data accessed by
`ciently high voltage, the gate voltage of the transistor
`the one pointer register and modified by the input signal
`Q63B is rapidly changed to the low level together with a
`SIN, with the number n corresponding to the number of
`change of the node SLn to a high level.
`shifts.
`The transistors Q56, Q57, and Q61 in the pointer shift
`The modified contents need not be restored in the
`register PSR and the transistors Q66, Q67, and Q71 are
`memory cells to update the contents thereof but can be
`used for preventing malfunctions which may arise due
`supplied from the shift register array 21a to another
`to the floating signal level, i.e., low level, because many
`device.
`nodes SL are at the low level. The depletion transistors
`As may be apparent from the above description, a
`Q56 and Q66 may be replaced by resistors.
`high-speed RMW operation can be performed for a
`By applying one clock signal TCLK1 consisting of the
`predetermined range of 1st to nth bit lines BLO to
`pair of pulses PE and NPE to the pointer shift register
`BLn-1, and the row decoder can be controlled to per
`array 23a, the 1 bit data held in a first pointer shift
`form the RMW operation within a predetermined range
`register is transferred to the next pointer shift register
`of word lines.
`and that first pointer shift register is reset. This is suc
`In the above embodiment, data on the first to n-th bit
`cessively effected in response to application of the clock
`lines are modified. However, any modification range of
`signal TCLK1. The pointer shift registers PSR0 to
`n1-th to n2-th bit lines can be selected.
`PSR255 feature a unique "1" bit shift therein.
`Still another embodiment of the present invention is
`In the embodiment, an arbitrary number of serial data
`shown in FIG. 11. In the circuit of FIG. 11, the shift
`appearing on the bit lines between the first bit line BLo
`register array 21a in FIG. 6 is replaced with a set-reset
`and n-th bit line BLn-1 can be successively output via
`(R-S) flip-flop array. More specifically, instead of the
`the shift registers SRO to SR-1 and via the gate 22a,
`shift register, a latch circuit 27b consisting of a flip-flop
`one of which is selected in response to the unique “1”
`273, an OR gate 271, and an inverter 272 is used to
`bit shifting in the pointer shift register array 23a. Via the
`gether with gates 22b and 28b associated with the latch
`selected gate 22a, output data successively appear on
`circuit 27b,
`the data bus DB, which may be output to the exterior of
`During operation, the contents of the memory cells
`the device via an output amplifier (not shown) so that
`40
`on a bit line BLi are read out and stored in the flip-flop
`serial data for the display unit can be obtained. Alterna
`273 through a gate 20a and the OR gate 271. An output
`tively, n-th pointer register PSR-1 may be set at logic
`Q of the flip-flop 273 is extracted by a pointer instruc
`'1' and held there while a desired number of shifts of
`tion POi from the pointer shift register PSR and placed
`the shift register array 21a is carried out. This operation
`on the data bus DB through the gate 22a. The data on
`also brings about serial data output of the desired num
`45
`the data bus DB is modified by the modifying circuit
`ber of bits via the data bus DB, but in a reverse direction
`25a. The modified content is stored in the flip-flop. 273
`to the data shift.
`through the gate 22b and the OR gate 271. The output
`A modification circuit 25a is the same as that of the
`Q of the modified and stored content is stored in the
`first embodiment.
`memory cell connected to the bit line BLi through the
`The RMW operation of the semiconductor memory
`50
`gate 28b in response to the clock signal TCLKB.
`device according to the second embodiment in FIG. 6
`In order to increase the RMW operation time (in
`will be described hereinafter. When a transfer instruc
`crease its speed), an n-parallel RMW arrangement is
`tion TR is set at logic “1”, the gate array 20a is turned
`ON in response to a clock signal TcLK from the transfer
`shown in FIG. 12. The connection between the circuit
`of FIG. 12 and the memory cell array 100 is the same as
`clock driver 26a, so that the data are simultaneously
`55
`described above. However, in order to perform the
`transferred from 256 memory cells defined by the pre
`n-parallel RMW operation, n data buses DB-1 to DB-n
`determined word line and the bit lines BL0 to BL255 to
`the register array 21a.
`and in modifying circuits 25-1 to 25-n are provided.
`In one preferred mode of RMW operation, an output
`Furthermore, n pointer register arrays 23-1 to 23-n can
`be operated in parallel with n register arrays 21-1 to
`from an arbitrary one of the pointer shift registers PSR0
`21-in. The pointer register arrays 23-1 to 23-n and the
`to PSR255 is set at logic “1”, and the output gate con
`register arrays 21-1 to 21-n may be shift registers or
`nected to the "1" holding shift register of the register
`array 21a is turned ON, while data in the shift registers
`flip-flops. The modifying circuits 25-1 to 25-n each are
`the same as the modifying circuit 25. The modifying
`SRO to SR-1 is shifted by one bit in response to the
`clock pulse (not shown). At the same time, the output
`circuit may include a circuit as shown in FIGS. 4 and 5a
`from the shift register SR-1 appears on the data buses
`to 5c or others. The circuits shown in FIGS. 4 and 5a to
`5c can be selectively used to perform various RMW
`SDB and SDB. The data on the data buses SDB and
`operations.
`SDB, as reference data, is modified by the modifying
`
`35
`
`25
`
`30
`
`65
`
`Petitioner Ex 1018, p. 12
`BOE v. Samsung, IPR2024-00620
`
`

`

`5
`
`O
`
`4,740,922
`8
`7
`The contents of the memory cells temporarily trans
`Embodiments for performing RMW operations for
`memory cells (mxn) of a specific area are shown in
`ferred to data latches DL0 to DL511 are modified by the
`modifying circuit 25a together with the input data Din
`FIGS. 13 and 14, respectively.
`The circuit in FIG. 13 has a gate array 31 consisting
`within the specific range of i to i+n, and the modified
`of gates Q0 to Q511 each having one end connected to a
`contents are latched by the data latches DL0 to DL511.
`corresponding one of bit lines BL to BL511, a latch
`The modified contents can be stored in the memory
`array 32 consisting of data latches DL0 to DL51 each
`cells during the nonaccess mode of the memory cell
`having one end connected to the other end of the corre
`array in the same manner as described above.
`sponding gates Q0 to Q511, a gate array 33 consisting of
`In this circuit, high-speed RMW operation can be
`gates QA0 to QA511 each connected to the other end of
`performed for the memory contents for the specific
`the corresponding data latches DL0 to DL511, and a
`memory cell area (mxn), and the contents of other
`shift register array 34 consisting of shift registers SRO to
`memory cell areas can be left unchanged.
`SR511 for controlling the gates of the gate array 33. The
`Many widely different embodiments of the present
`gate array 33 is connected to the data bus DB to which
`invention may be constructed without departing from
`the modifying circuit 25a is connected. In this embodi
`the spirit and scope of the present invention. It should
`15
`ment, the memory cell array has a 512X512 matrix, and
`be understood that the present invention is not limited
`other arrangements of the circuit are the same as those
`to the specific embodiments described in this specifica
`of the previous circuit.
`tion, except as defined in the appended claims.
`The operation of the circuit shown in FIG. 13 will be
`I claim:
`described. When the memory cell side is not accessed,
`1. A semiconductor memory device, comprising:
`the specific word line WLi is selected by the row de
`a random access memory cell array including mem
`coder 5. When a clock signal psis enabled (high), all the
`ory cells;
`gates Q0 to Q511 of the gate array 34 are turned ON, so
`data access means operatively connected to said
`that the contents of the memory cells connected to the
`memory cell array and including:
`word line WLiare transferred to the data latches DLoto
`25
`one or more register circuit arrays, each having a
`DL511 through the bit lines BL0 to BL511 and the gates
`data input and output circuit for simultaneously
`Q0 to Q511. The clock signal dbS is disabled after the
`storing or reading data into or from said memory
`above-mentioned data transfer period. Thereafter, the
`cells; and
`memory cells can be accessed.
`a data output circuit for serially reading a plurality
`Among the contents latched by the data latches DL0
`of data from said memory cells; and
`to DL511, the contents of specific registers for the shift
`one or more data modification circuits, each opera
`register array 34, e.g., SRito SRin are subjected to the
`tively connected to said corresponding register
`RMW operation. The shift registers SR0 to SR-1 are
`circuit array of said data access means, including at
`kept OFF in response to signals CLO to CL-1 from the
`least one logical gate circuit and, successively re
`column decoder 24a, and the outputs from the shift
`ceiving data from said data output circuit, modify
`registers SR0 to SR-1 are kept OFF. Therefore, the
`ing said receive data in a predetermined manner
`gates QAoto QA(i-1) are kept off, and the contents of the
`defined by said logical gate circuit and transmitting
`data latches DLoto DLi-1 are left unchanged. The shift
`said modified data to said data input and output
`registers SR to SRin are sequentially turned ON in
`circuit.
`response to the signals CLi to CLin from the column
`2. A semiconductor memory device according to
`decoder 24a. The gates QAi to QA(i+n) are sequentially
`claim 1, wherein said data input and output circuit in
`turned ON in response to the ON outputs CLi to CLin.
`cludes:
`In this case, the input data Din is supplied to the data bus
`first gates connected in parallel with each other and a
`DB, and the contents modified by the modifying circuit
`first terminal of each first gate operatively con
`25a are sequentially latched by the data latches DLi to
`nected to a corresponding memory cell selection
`DLi-in. The data latches DLin-1 to DL51 and DL0 to
`line and each having a second terminal;
`DLi-1 store the contents of the memory cells without
`first registers connected in parallel with each other
`modification. The modified contents within the range of
`and each connected to the second terminal of the
`bit lines BLito BLin for the word line WLi are held in
`corresponding gate; and
`the data latches DLito DLin, while other latches store
`a gate drive circuit driving simultaneously said first
`the contents of the memory cells without modification.
`gates to simultaneously store or read said plurality
`In this state, the clock signal dbsis enabled for a prede
`of data into or from said memory cells.
`termined period of time while the memory cells are not
`3. A semiconductor memory device, comprising:
`accessed. The gate array 31 is turned ON, and the con
`a random access memory cell array including mem
`tents of the data latch array 32 are stored in the memory
`55
`ory cells;
`cells connected to the word line WL. The modified
`data access means operatively connected to said
`contents can be stored in the memory cells within the
`memory cell array and including:
`range of bit lines BL to BLin. Other memory cells
`one or more register circuit arrays, each having a
`hold the previous data.
`data input and output circuit for simultaneously
`The same operations are performed for the word lines
`60
`storing or reading data into or from said memory
`WLi+1 to WLim, and thus high-speed RMW opera
`tion can be performed for the specific memory cell area
`cells, each data input and output circuit includ
`(mxn).
`1ng:
`first gates connected in parallel with each other
`FIG. 14 shows a modification wherein the gate array
`33 in FIG. 13 includes a gate array 35 consisting of gates
`and a first terminal of each first gate opera
`65
`tively connected to a corresponding memory
`QBO to QB511 connected to an input data bus DB(I) and
`a gate array 33 consisting of gates Q40 to Q451 1 con
`cell selection line and each having a second
`nected to an output data bus DB(O).
`terminal;
`
`35
`
`45
`
`50
`
`Petitioner Ex 1018, p. 13
`BOE v. Samsung, IPR2024-00620
`
`

`

`15
`
`4,740,922
`10
`first registers connected in parallel with each
`mined manner and transmitting said modified data
`to said data input and output circuit.
`other and each connected to the second termi
`nal of the corresponding gate; and
`6. A semiconductor memory device, comprising:
`a gate drive circuit driving simultaneously said
`a random access memory cell array including mem
`first gates, to simultaneously store or read data 5
`ory cells;
`into or from said memory cells; and
`data access means operatively connected to said
`a data output circuit for serially reading plurality of
`memory cell array and including:
`data from said memory cells, said data output
`one or more register circuit arrays, each having a
`circuit including:
`data input and output circuit for simultaneously
`second gates connected in parallel with each 10
`storing or reading data into or from said memory
`other and each having first and second termi
`cells, each data input and output circuit includ
`nals;
`ing:
`second registers connected to said second gates;
`first gates connected in parallel with each other
`an output amplifier connected to said second
`and a first terminal o