UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner
`
`v.
`
`YANGTZE MEMORY TECHNOLOGIES COMPANY, LTD.,
`Patent Owner
`
`Case No.: IPR2024-00794
`U.S. Patent No. 10,950,623
`Issue Date: March 16, 2021
`
`Title: 3D NAND MEMORY DEVICE AND METHOD
`OF FORMING THE SAME
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 10,950,623
`PURSUANT TO 35 U.S.C. §§311-319 AND 37 C.F.R. §42
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`TABLE OF CONTENTS
`
`IV.
`
`Introduction ...................................................................................................... 1
`I.
`II. Mandatory Notices........................................................................................... 5
`A.
`Real Party-in-Interest ............................................................................ 5
`B.
`Related Matters ...................................................................................... 5
`C.
`Counsel, Service, and Fee Information ................................................. 6
`III. Requirements for IPR ...................................................................................... 7
`A. Grounds for Standing ............................................................................ 7
`B.
`Identification of Challenge and Statement of Precise Relief Requested
` ............................................................................................................... 7
`Institution Should Be Granted ......................................................................... 8
`A.
`There Are No Grounds for a § 314 Discretionary Denial in this Case . 8
`1.
`Possibility of a Stay .................................................................... 9
`2.
`Proximity of the Court’s Trial Date ............................................ 9
`3.
`Investment in the Parallel Proceeding ........................................ 9
`4.
`Issue Overlap .............................................................................10
`5.
`Party Overlap ............................................................................10
`6.
`Other Circumstances .................................................................10
`B. Denial Under § 325(d) Would Be Inappropriate ................................11
`The ’623 Patent ..............................................................................................11
`A.
`Technological Background .................................................................11
`B. Overview .............................................................................................15
`C.
`Prosecution History .............................................................................18
`
`V.
`
`-i-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`VI. Claim Construction ........................................................................................18
`VII. Level of Ordinary Skill in the Art .................................................................19
`VIII. Prior Art Overview ........................................................................................19
`A.
`Park ......................................................................................................19
`B.
`Shibata .................................................................................................22
`IX. The ’623 Patent’s Claims Are Obvious .........................................................25
`A. Ground 1: Claims 1-11 Are Obvious Over Park .................................25
`1.
`Claim 1 ......................................................................................25
`2.
`Claim 2 ......................................................................................39
`3.
`Claim 3 ......................................................................................45
`4.
`Claim 4 ......................................................................................46
`5.
`Claim 5 ......................................................................................48
`6.
`Claim 6 ......................................................................................49
`7.
`Claim 7 ......................................................................................51
`8.
`Claim 8 ......................................................................................52
`9.
`Claim 9 ......................................................................................53
`10. Claim 10 ....................................................................................54
`11. Claim 11 ....................................................................................56
`B. Ground 2: Claims 1-11 Are Obvious Over Park in View of Shibata .57
`C. Ground 3: Claims 1-11 Are Obvious Over Shibata in View of Park .63
`1.
`Claim 1 ......................................................................................64
`2.
`Claim 2 ......................................................................................81
`3.
`Claim 3 ......................................................................................83
`
`-ii-
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Claim 4 ......................................................................................85
`4.
`Claim 5 ......................................................................................87
`5.
`Claim 6 ......................................................................................88
`6.
`Claim 7 ......................................................................................89
`7.
`Claim 8 ......................................................................................90
`8.
`Claim 9 ......................................................................................91
`9.
`10. Claim 10 ....................................................................................92
`11. Claim 11 ....................................................................................94
`Secondary Considerations ...................................................................94
`D.
`Conclusion .....................................................................................................95
`
`X.
`
`-iii-
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`LISTING OF EXHIBITS
`
`Exhibit
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`U.S. Patent No. 10,950,623 B2 to Song et al.
`
`File History of U.S. Patent No. 10,950,623 to Song et al.
`
`Declaration of Dr. Jack C. Lee (“Lee”)
`
`U.S. Patent No. 10,559,583 B2 to Park et al. (“Park”)
`
`U.S. Patent Publ. No. 2019/0122734 A1 to Shibata et al.
`(“Shibata”)
`
`Aritome, “NAND Flash Memory Technologies” (2016)
`
`Silvagni, “3D NAND Flash Based on Planar Cells,” Computers
`2017
`
`U.S. Patent Publ. No. 2015/0162084 A1 to Morooka et al.
`
`U.S. Patent Publ. No. 2015/0255478 A1 to Tanzawa
`
`U.S. Patent No. 9,589,978 to Yip
`
`U.S. Patent Publ. No. 2017/0062337 A1 to Park et al.
`
`Micheloni et al., “Inside Solid State Drives (SSDs)” (2nd Ed. 2018)
`
`Docket from Yangtze Memory Technologies Company, Ltd. v.
`Micron Technology, Inc. and Micron Consumer Products Group,
`LLC, Case No. 3:23-cv-05792-RFL
`
`Combined Civil and Criminal Federal Court Management Statistics
`(December 31, 2023), available at https://www.uscourts.gov/sites/
`default/files/data_tables/fcms_na_distcomparison1231.2023.pdf
`
`File History of U.S. Patent No. 11,430,811 (Appl. No. 17/154,054)
`to Song et al.
`
`1016
`
`U.S. Patent No. 10,355,010 B2 to You et al.
`
`-iv-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Exhibit
`
`Description
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`U.S. Patent No. 9,299,718 B2 to Park et al.
`
`U.S. Patent Publ. No. 2019/0035798 A1 to Hwang et al.
`
`U.S. Patent Publ. No. 2015/0137216 A1 to Lee et al.
`
`Yangtze Memory Technologies Company, Ltd. v. Micron
`Technology, Inc. and Micron Consumer Products Group, LLC,
`Case No. 3:23-cv-05792-RFL, Zoom Civil Minute Order, dated
`February 22, 2024 (Dkt. No. 42)
`
`U.S. Patent Pub. 2019/0214404 A1 to Ahn et al.
`
`Curriculum Vitae of Dr. Jack C. Lee
`
`U.S. Patent No. 8,945,996 to Tang et al.
`
`-v-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`I.
`
`Introduction
`Petitioner requests IPR of claims 1-11 of U.S. Patent 10,950,623 (“the ’623
`
`patent”), assigned to Yangtze Memory Technologies Co., Ltd. (“Patent Owner”).
`
`The ’623 patent relates to 3D NAND memory devices. Typical, prior art 3D
`
`NAND devices are formed from alternating layers of conductive and insulating
`
`material stacked on a substrate. The conductive layers include a lower “bottom
`
`select gate” (or “BSG”), intermediate word lines, and an upper “top select gate” (or
`
`“TSG”). Conductive columns pass through the layers to form vertical strings of
`
`memory cells. There are many such vertical strings in a 3D NAND device
`
`resulting in a three-dimensional array of memory cells. Conductive interconnects
`
`to a lower common source can also pass through the layers.
`
`Typical prior art 3D NAND devices arrange the strings of memory cells into
`
`“blocks” that can be independently controlled. To allow for this control, each
`
`block includes its own BSG and TSG. According to the ’623 patent, as the blocks
`
`become larger their operation slows. Thus, the patent attempts to differentiate
`
`itself from prior art 3D NAND devices by dividing its memory blocks into “sub-
`
`blocks.” It does this by including “dielectric trenches” in at least the BSG layer.
`
`This divides the BSG into individually controllable “sub-BSGs” associated with
`
`the “sub-blocks.” Similarly, separate trenches optionally can be included in the
`
`TSG layer to divide it into “sub-TSGs.”
`
`-1-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Claim 1—the ’623 patent’s only independent claim—requires one set of
`
`“dielectric trenches” in the BSG layer. Dependent claim 2 requires another set of
`
`“dielectric trenches” in the TSG layer. Dependent claims 3-11 reference a
`
`collection of standard 3D NAND features—like memory “channels” or “dummy”
`
`structures—and a few other basic “dielectric trench” structural requirements.
`
`There was nothing new about this. This Petition focuses on two exemplary
`
`references: (1) U.S. Patent 10,559,583 (Ex. 1004, “Park”), and (2) U.S. Pub.
`
`2019/0122734 A1 (Ex. 1005, “Shibata”). Both Park and Shibata—like the ’623
`
`patent—teach 3D NAND devices with blocks of memory divided into smaller sub-
`
`blocks. Both references also achieve this in the same way as the ’623 patent: their
`
`select gate layers are divided into individually controllable portions by trenches of
`
`dielectric material.
`
`More particularly, Park explains that its memory blocks can be divided into
`
`multiple independently controllable “unit areas.” To do so, Park’s BSG—referred
`
`to as a “ground select line” or “GSL”—is separated into portions by “isolation
`
`insulating layers 111.” Each GSL portion is associated with and controls one of
`
`the “unit areas.”
`
`Shibata similarly divides its blocks of memory into independently
`
`controllable “string units.” To effectuate this, Shibata employs dielectric
`
`“separation portions 62a” to divide its TSG—referred to as a “drain-side select
`
`-2-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`gate” or SGD—into portions that are associated with and control the “string units.”
`
`In view of this, Park and Shibata render the ’623 patent’s claims
`
`unpatentable in multiple different ways.
`
`Ground 1 details how Park itself renders claims 1-11 obvious. Park
`
`employs a “dielectric trench” (isolation insulating layers 111) dividing its “BSG”
`
`(GSL) into individually controllable portions associated with memory unit areas.
`
`This ground is expressed in terms of obviousness—and not anticipation—because
`
`Park uses somewhat different language than the ’623 patent. For instance, it does
`
`not refer to its isolation insulating layers 111 as “trenches.” This, however, is
`
`exactly what a person having ordinary skill in the art (“POSITA”) would have
`
`understood Park’s insulating layer 111 to be: trenches of insulating material that
`
`divide Park’s BSG into sub-BSGs. Next, while Park teaches that its “TSG” (a
`
`string select line) also is divided into portions corresponding to the unit areas, it
`
`does not provide an example where isolation insulating layers 111 do so.
`
`Regardless, given Park’s discussion of these layers’ purpose, a POSITA would
`
`have considered it obvious to employ them to divide both Park’s BSG and TSG.
`
`See, e.g., Game and Tech. Co. v. Activision Blizzard Inc., 926 F.3d 1370, 1381
`
`(Fed. Cir. 2019) (single reference can support obviousness); Realtime Data, LLC v.
`
`Iancu, 912 F.3d 1368, 1373 (Fed. Cir. 2019) (similar).
`
`-3-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Ground 2 details how Park—when modified by Shibata—also renders the
`
`claims obvious. It is possible that Patent Owner may argue that Park’s layers 111
`
`are not the claimed “dielectric trenches” because they only separate Park’s BSG in
`
`cooperation with other structure (a collection of common source lines 105). Even
`
`if this were pertinent to the claims—it is not—the claims would still be obvious.
`
`Shibata explains that the use of narrower dielectric separation portions instead of
`
`wider common source lines to divide select gates allows memory devices to be
`
`made smaller and denser. It also provides a specific example that uses such a
`
`trench to divide a device’s TSG.
`
`Ground 3 explains how Shibata—modified in view of Park—also renders
`
`claims 1-11 obvious. Shibata teaches a memory device that employs a “dielectric
`
`trench” (like separation portions 62a) to divide its “TSG” (drain-side select gate)
`
`into individually controllable portions associated with memory string units.
`
`Shibata’s BSG also can be controlled on a string unit basis. But Shibata
`
`accomplishes this in its examples by employing multiple BSG layers. Park teaches
`
`that the same type of control can be achieved by dividing a single BSG layer into
`
`portions. As explained in this ground, a POSITA would have been motivated to
`
`apply this teaching to Shibata because doing so would allow it either to employ
`
`fewer layers (resulting in smaller size) or include more word lines (increasing
`
`memory density).
`
`-4-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`II. Mandatory Notices
`A.
`Real Party-in-Interest
`Petitioner Micron Technology, Inc. (“MTI”) and its subsidiaries, including
`
`Micron Consumer Products Group LLC, are the real-parties in interest.
`
`Related Matters
`B.
`Patent Owner YMTC has asserted the ’623 patent and U.S. Patents
`
`10,658,378, 10,861,872, 10,868,031, 10,937,806, 11,468,957, 11,501,822 and
`
`11,600,342 in a co-pending litigation, Yangtze Memory Technologies Company,
`
`Ltd. v. Micron Technology, Inc. and Micron Consumer Products Group, LLC, Case
`
`No. 3:23-cv-05792-RFL (N.D. Cal., filed November 9, 2023).
`
`In addition to this Petition, Petitioner is filing (or has filed) petitions for inter
`
`partes review of each of these asserted patents: IPR2024-00788 (’378 patent),
`
`IPR2024-00789 (’872 patent), IPR2024-00790 (’031 patent), IPR2024-00791
`
`(’806 patent), IPR2024-00792 (’957 patent), IPR2024-00795 (’822 patent), and
`
`IPR2024-00793 (’342 patent).
`
`-5-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Counsel, Service, and Fee Information
`C.
`Petitioner designates the following counsel:
`
`Lead Counsel
`K. Patrick Herman
`Registration No. 75,018
`(pherman@orrick.com)
`
`Back-Up Counsel
`Jeremy Jason Lang
`Registration No. 73,604
`(jlang@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`51 West 52nd Street
`New York, NY 10019
`T: 212-506-5000; F: 212-506-5151
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025-1015
`T: 650-614-7400; F: 650-614-7401
`
`Jared Bobrow
`Pro Hac Vice to be submitted
`(jbobrow@orrick.com)
`
`Postal & Hand-Delivery Address:
`Orrick, Herrington & Sutcliffe LLP
`1000 Marsh Road
`Menlo Park, CA 94025
`T: 650-614-7400; F: 650-614-7401
`
`Petitioner consents to service by electronic mail at the following addresses:
`
`P52PTABDocket@orrick.com, PTABDocketJJL2@orrick.com, PTABDocketJ3B3
`
`@orrick.com, and micron-ymtc_ohs@orrick.com.
`
` Pursuant
`
`to 37 C.F.R.
`
`§42.10(b), Petitioner attaches a Power of Attorney.
`
`The USPTO is authorized to charge the filing fee and any other fees incurred
`
`by Petitioner to the deposit account of Orrick, Herrington, & Sutcliffe LLP: 15-
`
`0665.
`
`-6-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`III. Requirements for IPR
`A.
`Grounds for Standing
`Petitioner certifies that the ’623 patent is available for IPR, and that
`
`Petitioner is not barred or estopped from requesting this IPR. Petitioner was
`
`served with a complaint alleging infringement of the ’623 patent on November 14,
`
`2023. This petition was filed within 1 year of this date.
`
`B.
`
`Identification of Challenge and Statement of Precise Relief
`Requested
`Petitioner requests IPR of claims 1-11. This petition discusses claim
`
`construction, explains why the claims are unpatentable, provides details regarding
`
`where the various claim limitations are found in the prior art, and is supported by
`
`the accompanying Declaration of Dr. Jack C. Lee (Ex. 1003, “Lee”), a leading
`
`expert in the 3D NAND field.
`
`The application underlying the ’623 patent—U.S. App. 16/365,725—was
`
`filed March 27, 2019 and facially identifies itself as a continuation of a December
`
`7, 2018 PCT filing. Ex. 1001, Cover.
`
`Petitioner relies on the following references: (1) Park (Ex. 1004) and
`
`(2) Shibata (Ex. 1005). These references are all prior art. See Section VIII.
`
`Petitioner challenges the claims on the following grounds:
`
`Ground 1: Claims 1-11 are obvious over Park;
`
`Ground 2: Claims 1-11 are obvious over Park in view of Shibata; and
`
`-7-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Ground 3: Claims 1-11 are obvious over Shibata in view of Park.
`
`IV.
`
`Institution Should Be Granted
`Petitioner has established a reasonable likelihood of success on the merits.
`
`All other requirements for IPR have been met. The Board should institute IPR.
`
`A.
`
`There Are No Grounds for a § 314 Discretionary Denial in this
`Case
`There is a pending district court action involving the ’623 patent. The
`
`PTAB has explained that it “will not … discretionarily deny institution in view of
`
`parallel district court litigation where a petition presents compelling evidence of
`
`unpatentability.” 6/21/22 Interim Procedure, 2, 4-5. Petitioner submits that it
`
`presents a compelling case here: the claims of the ’623 patent are unambiguously
`
`unpatentable.
`
`Petitioner also notes that the factors considered by the Board when assessing
`
`whether to institute IPR in light of a parallel proceeding collectively weigh in favor
`
`of institution. See Apple Inc. v. Fintiv, Inc., Case No. IPR2020-00019, Paper No.
`
`11 (Mar. 20, 2020) (precedential) (“Fintiv”). In particular: the district court may
`
`stay the case, any potential trial will occur years from now, little district court work
`
`has occurred, petitioner diligently prepared this petition, and the petition is
`
`substantively strong.
`
`-8-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Possibility of a Stay
`1.
`Petitioner intends to seek a stay if the Board institutes IPR. Until this issue
`
`is adjudicated, any attempt to predict the outcome would require speculation. This
`
`factor is neutral. See Sand Revolution II, LLC v. Continental Intermodal Group –
`
`Trucking LLC, IPR2019-01393, Paper 24 at 7 (PTAB June 16, 2020) (informative)
`
`(“Sand Revolution”); Fintiv at 12 (similar).
`
`Proximity of the Court’s Trial Date
`2.
`On February 22, 2024, the district court entered a scheduling order which set
`
`a trial date of December 1, 2025. See Ex. 1020. If IPR is instituted, it should be
`
`completed before this date. See also Ex. 1014 (indicating an average of 48.9
`
`months to trial). This weighs strongly in favor of institution.
`
`Investment in the Parallel Proceeding
`3.
`To date, the parties and Court have invested very little in the parallel
`
`proceeding. Beyond engaging in some motion practice regarding the pleadings, no
`
`substantive progress has been made. The parties are months away from the
`
`exchange of infringement and invalidity contentions and have not taken any
`
`depositions. Fact discovery is in its infancy. No claim construction positions have
`
`been exchanged, no claim construction order has issued, no infringement or
`
`invalidity expert discovery has occurred, and no summary judgment motions have
`
`been filed. This weighs in favor of institution. See Sand Revolution at 11.
`
`The Board also has explained that institution is appropriate where “the
`
`-9-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`petitioner filed the petition expeditiously….” Fintiv at 11. Here, Patent Owner
`
`asserted eight different patents against Petitioner. See Ex. 1013. Yet, Petitioner
`
`proceeded with diligence filing a mere five months after being served with the
`
`original complaint and a little over two months after the filing of an amended
`
`complaint. See id. This also weighs strongly in favor of institution.
`
`Issue Overlap
`4.
`Given the early stage of the parallel proceeding, it is not yet possible to
`
`determine the amount of overlap. Patent Owner has not yet served infringement
`
`contentions or identified the asserted claims. Moreover, should the Board institute,
`
`Micron stipulates that it will not advance in District Court any invalidity defense
`
`that formed the basis of any of the grounds in this Petition. Micron submits that
`
`this eliminates any potential overlap in issues between the proceedings here and in
`
`District Court. The Board has found that such stipulations weigh in favor of
`
`institution. Sand Revolution at 11-12.
`
`Party Overlap
`5.
`Both Petitioner and Patent Owner are parties in the parallel proceeding.
`
`This, however, is of little moment as there is often party overlap when there is a
`
`parallel proceeding.
`
`Other Circumstances
`6.
`Here, Petitioner submits that its petition has significant substantive merit. It
`
`is premised on clear, understandable prior art that the Patent Office did not
`
`-10-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`previously consider. Thus, this factor also weighs in favor of institution.
`
`Denial Under § 325(d) Would Be Inappropriate
`B.
`Neither Park nor Shibata was cited by Patent Owner or considered by the
`
`Examiner during prosecution of the ’623 patent. See generally Ex. 1002. Indeed,
`
`as explained in Section V.C, the Examiner did not specifically address or assess
`
`any prior art references or issue any prior art-based rejections in connection with
`
`the ’623 patent. While the Examiner later used Shibata to reject the claims in an
`
`application claiming priority to the ’623 patent, this did not occur until almost a
`
`year after the ’623 patent had already issued. See Ex. 1015, 123-132. Moreover,
`
`the Examiner did not consider the features of Shibata that are the focus of this
`
`petition: separation portions 62a and interconnects LI in slits 60. See id. The
`
`Examiner’s rejection of the claims over Shibata also forced applicant to amend the
`
`claims to include further limitations that are not part of the ’623 patent’s claims.
`
`See id., 141-147. Thus, the later consideration of Shibata has no bearing on
`
`whether institution is appropriate here. Moreover, while other, different references
`
`naming an inventor with the last name “Park” were cited in certain applications
`
`related to the ’623 patent, the Park reference discussed in this petition was not.
`
`V.
`
`The ’623 Patent
`A.
`Technological Background
`The ’623 patent and the prior art discussed in this petition relate to NAND
`
`flash memory. “Flash memory” is a form of “non-volatile memory.” Ex. 1010,
`
`-11-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`1:24-26. “Non-volatile memory … can retain its data values … without the
`
`application of power.” Id., 1:26-28. NAND flash stores data in a “cell” formed
`
`from a transistor. Ex. 1006, 38-39; Ex. 1012, 109; Lee, ¶¶ 39-46.
`
`NAND cells are arranged in “strings” with multiple cells “connected in
`
`series.” Ex. 1006, 38. The cells are surrounded by “select transistors (SGD,
`
`SGS).” Id. The “SGD connects” at the string’s drain side “to isolate it from the bit
`
`line (BL),” and the “SGS connects” at the string’s source side “to isolate it from a
`
`source line (SL).” Id. Word lines connect to each memory cell’s control gate. Id.,
`
`38-39. One such string is shown below:
`
`Id., 39.
`
`Early NAND devices were formed as two-dimensional arrays of cells on a
`
`substrate surface. Ex. 1006, 38.
`
`-12-
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
`
`Id., 40. The cells are grouped into “page[s]” extending along the word lines and
`
`“block[s].” Id. “[R]ead and program operations are performed per page” while
`
`“the erase operation is performed per block.” Id., 39. “[T]o further scale down the
`
`memory cell size,” 3D NAND was developed in 2006. Id., 292. “Conceptually, a
`
`modern 3D NAND structure could be conceived by starting from the 2D NAND
`
`string building block” and “turning the 2D NAND string upside” “resulting” in a
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`“3D structure” with a “vertical channel.” Ex. 1007, 3.
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`Ex. 1012, 122. Multiple such vertical channels are then repeated in a three-
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`dimensional array:
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`Ex. 1006, 296; Lee, ¶¶ 47-57.
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`3D NAND includes “multi-stacked layers of gate (plate)” material alternated
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`with “dielectric” in a “[s]tack.” Ex. 1006, 294. A “through-hole” channel “filled
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`by memory film … and channel poly-Si” passes through the layers to form the
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`string of vertically arranged memory cells. Id., 295. “Each” layer of “electrode
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`plate acts as a control gate.” Id. A particular vertical memory cell “string is
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`selected by a bit line and an upper select gate (upper SG).” Id., 296. A memory
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`cell “is located in the intersection of a control gate plate” and the memory
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`film/poly-Si channel. Id. The lowest layer is a “select gate (lower SG)” allowing
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`the strings to connect to a lower “common source.” Id., 295, 297. An example
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`3D NAND vertical memory cell string follows:
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`Id., 296. In some 3D NAND, “[t]he control gates and lower SG are commonly
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`connected in each layer in [a] block.” Id., 295. “[T]he control gates and
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`upper/lower SG are connected” to the memory’s “metal layers at [a] stair-like gate
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`structure” located outside the memory array. Id., 295, 297.
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`Id. at 296; Lee, ¶¶ 58-64 .
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`Overview
`B.
`The ’623 patent relates to a “3D NAND memory device.” Ex. 1001, 1:33-
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`36. According to the patent, in existing devices, “memory cell strings of the same
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`block can share a bottom select gate (BSG).” Id., 1:51-52. “The shared BSG
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`accordingly controls” all the “bottom select transistors (BSTs)” “of the vertical
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`NAND memory cell strings in that block simultaneously during” operation. Id.,
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`1:40-41, 1:53-58. This is a problem, according to the patent, because “the shared
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`BSG can induce longer erasing time, longer data transfer time, and lower storage
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`efficiency.” Id., 1:58-60.
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`The patent purports to address this by employing a “divided block
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`structure.” Id., 1:33-36. “[E]ach of the blocks can be separated into a plurality of
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`sub-blocks by dividing the shared BSG into a plurality of sub-BSGs” using “one or
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`more first dielectric trenches.” Id., 1:61-64. This in turn allows the “sub-blocks”
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`to be “operated individually through controlling the respective sub-BSG.” Id.,
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`1:64-67. The patent similarly explains that “a shared/common TSG” can also be
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`“divid[ed]” by “second dielectric trenches” into “sub-TSGs” that can also be
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`independently controlled. Id., 2:8-13.
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`Figure 1A provides an example. Here, the depicted “memory device 100”—
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`like all 3D NAND devices—includes a BSG 62p (dark blue), a TSG 62a (light
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`blue), and multiple “word lines” separated by “insulating layers” stacked over a
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`“substrate 10.” Id., 6:44-54. Electrical connection to these layers is made via the
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`same type of “staircase region[]” present in prior art 3D NAND. Id., 8:44-60; Fig.
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`2. A “common source region 52” (purple) passes through all the layers and “is
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`electrically coupled with the substrate 10….” Id., 7:59-67. The memory strings
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`are formed around “channel structures” 30/32/34/36/38. Id., 8:23-26. As shown,
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`“first dielectric trenches” 26 and 28 (orange) are formed in the lower BSG, while
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`“second trenches” 56 and 58 (also orange) are formed in the upper TSG. Id., 7:17-
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`35. The trenches divide the BSG and TSG into “sub-BSGs” and “sub-TSGs”
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`associated with memory “sub-blocks” that “can be operated individually[.]” Id.,
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`7:45-53.
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`Id., Fig. 1A.1
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`Figure 1B provides a top view. Trenches 26/56 and 28/58 (orange) run
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`parallel to common source regions 52a-c (purple) along the “X-direction … of the
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`substrate.” Id., 7:20-62.
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`1 Petitioner has added all color to the figures.
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`Id., Fig. 1B.
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`Prosecution History
`C.
`The ’623 patent’s claims were not rejected over the prior art during
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`prosecution. See generally Ex. 1002. When allowing the claims, the Examiner did
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`not discuss any prior art. See id., 611-613.
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`VI. Claim Construction
`The Board applies the same Phillips claim construction standard used by
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`district courts. Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc).
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`For purposes of this petition, Petitioner submits that the terms of the ’623 patent’s
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`claims do not require further construction and can be afforded their plain and
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`ordinary meaning. See Lee, ¶¶ 88-91.
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`VII. Level of Ordinary Skill in the Art
`A POSITA in the field of the ’623 patent would have had a bachelor’s
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`degree in electrical engineering or a similar discipline, along with 2-3 years of
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`professional experience working with (e.g., researching, designing, or teaching)
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`NAND flash memory devices, or an equivalent level of skill, knowledge, and
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`experience (e.g., an advanced degree may substitute for professional experience).
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`Lee, ¶¶ 36-37. This POSITA would also have been aware of and generally
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`knowledgeable about 3D NAND’s structure, its component parts, how it operates,
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`and how it is controlled. Id.
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`VIII. Prior Art Overview
`A.
`Park
`Park was filed January 25, 2017. Park, Cover. It is prior art under AIA §
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`102(a)(2).
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`Park teaches a “3D-NAND memory device.” Park, 1:37-46. This device
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`includes the standard 3D NAND layers: a lower “ground select line” GSL, an
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`intermediate “plurality of word lines” WL, and an upper “string select line” SSL.
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`Id., 1:63-2:1. Multiple “common source line[s] 102” pass through these layers.
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`Id., 7:40-43. Electrical connection to the layers is made via “a stepped structure.”
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`Id., 6:56-60. The device’s memory cells are formed along “a plurality of channel
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`structures extending vertically through” the GSL, WL, and SSL layers. Id., 1:49-
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`52. Like the ’623 patent, Park sub-divides its memory “blocks” into smaller “unit
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`Petition for Inter Partes Review of U.S. Patent No. 10,950,623
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`areas.” Id., 4:61-5:7. For instance, the memory device can include a “first block
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`BK1” with “unit areas UA1 to UA4” and a “second block BK2” with “unit areas
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`UA5 to UA8.” Id., 5:8-10.
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`Id., Fig. 3.
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`“[T]he memory cell devices” can be “independently control[led]” on a unit-
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`by-unit basis. Park, 5:67-6:4. To achieve this, Park’s SSL and GSL “may be
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`separated from each other between the … unit areas….” Id. “[I]solation insulating
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`layers 111” (orange below) formed in slits or openings through the GSL, along
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`with “first common source lines 102” and “second common source lines 105”
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`(