United States Patent (19)
`Harmel et al.
`
`54 CONTACTING PROCESS USING O-SIPOS
`LAYER
`
`75) Inventors: Hartmut Harmel, Hofgeismar; Uwe
`Kellner-Werdehausen, Pretzfeld, both
`f German
`of G
`y
`73) Assignee: Temic Telefunken microelectronic
`GmbH, Heilbronn, Germany
`
`21 Appl. No.: 490,487
`
`US005661079A
`Patent Number:
`11
`45 Date of Patent:
`
`5,661,079
`Aug. 26, 1997
`
`61-147581 7/1986 Japan.
`2143083 1/1985 United Kingdom.
`2173035 10/1986 United Kingdom.
`
`OTHER PUBLICATIONS
`Matsushita et al., “A SIPOS-Si Heterojunction Transistor",
`Jap. Jour. Appl. Phys., vol. 20, 1981, pp. 75-81.
`A. Mimura et al.: "High-Voltage Planar Structure Using
`SiO-SIPOS-SiOFilm”. In: IEEEElectron Device Letters,
`vol. EDL-6, No. 4, Apr. 1985, pp. 189-191.
`Y. H. Kwark et al.: "SIPOS Heterojunction contacts to
`Silicon". In: IEDM 84, pp. 742-745, 1984.
`
`Jun. 14, 1995
`22 Filed:
`30
`Foreign Application Priority Data
`Primary Examiner-John Niebling
`Jul. 12, 1994 DEl Germany .......................... 44.24 420.7
`Assistant Examiner-Thomas G. Bilodeau
`(51
`Int. Cl. ... HOL 21/28
`Attorney, Agent, or Firm-Spencer & Frank
`52 U.S. Cl. .............
`... 438/660; 438/763; 438/958
`58 Field of Search ..................................... 437/187,188,
`7
`ABSTRACT
`437/233, 194, 197,967,980; 257/914.
`The invention relates to a method for contacting SIPOS
`passivated semiconductor Zones on a semiconductor body,
`References Cited
`where the removal of the oxide layer from the wafer surface
`U.S. PATENT DOCUMENTS
`takes place at the same time as the oxide etching before
`SIPOS passivation. The double-layered SIPOS passivation
`H665 8/1989 Knolle et al. ............................. 357/52
`consists here of a N-SIPOSlayer and a O-SIPOSlayer. For
`3,983.264 9/1976 Schroenet al.
`.
`... 239 contact opening, only the N-SIPOSlayer is removed by wet
`4,062,707 12/1977 Mochizuki et al. .................... 437/233
`chemical etching. By annealing the previously vaporized
`4,332,837
`6/1982 Peyre-Lavigne ....................... 437/188
`4,489,103 12/1984 Goodman et al.
`... 437/233
`and structured metallization, a good contact results which
`4,778,776 10/1988 Tong et al.........
`...
`i?
`can also carry a high current. The process according to the
`4,827.324 5/1989 Blanchard.
`323s
`invention involves a simple sequence of operations and an
`5,41077 4/1995 Hameletal. 257/567
`underetching of the passivation layers and the disadvantages
`resulting from this are reliably avoided.
`FOREIGN PATENT DOCUMENTS
`3138324 4/1983 Germany.
`
`56)
`
`12 Claims, 2 Drawing Sheets
`
`
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`y -ra:/77
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`22.2
`
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`Petitioner Canadian Solar Inc. - Ex. 1045, p. 1
`
`

`

`U.S. Patent
`
`Aug. 26, 1997
`
`Sheet 1 of 2
`
`5,661,079
`
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`
`Petitioner Canadian Solar Inc. - Ex. 1045, p. 2
`
`

`

`U.S. Patent
`
`Aug. 26, 1997
`
`Sheet 2 of 2
`
`5,661,079
`
`
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`Petitioner Canadian Solar Inc. - Ex. 1045, p. 3
`
`

`

`5,661,079
`
`1.
`CONTACTNG PROCESS USING O-SPOS
`LAYER
`
`BACKGROUND OF THE INVENTION
`The invention relates to a method for contacting SIPOS
`passivated semiconductor Zones of a semiconductor body
`with at least one pnjunction and where part of the surface
`of the semiconductor body is protected by an oxide layer.
`The use of so-called SIPOS passivation layers (Semi
`Insulating-Poly-Silicon) for the manufacture of semiconduc
`tor components, in particular of high-voltage power
`transistors, is known. In general, a double layer is applied
`where the first layer is of O-SIPOS (oxygen-doped) and the
`second layer is of N-SIPOS (nitrogen-doped). To manufac
`ture a SIPOS double layer of this kind, it is customary to
`apply a CVD (Chemical Vapor Deposition) process.
`Before the places to be contacted, for example, the emitter
`or base Zones, can come into contact with a metallization
`that is usually made of aluminum, it must first be ensured,
`with the help of a so-called contact opening process, that the
`N-SIPOS, O-SIPOS and oxide layers previously applied in
`other steps of the process are removed again from these
`places. Frequently, the contact opening is accomplished by
`a wet chemical etching, and less frequently by a plasma
`etching process because of the considerably greater techno
`logical effort involved. Another possibility, which also
`involves a great deal of technological effort, is to make the
`contact in several masking steps. In most cases, however, the
`contact opening process applied is that of wet chemical
`etching, the process involving little technology. A disadvan
`tage of this etching method is that hollow spaces are often
`formed between the passivation layers and a metallization
`due to under-etching, as well as discontinuities in the
`metallization.
`
`10
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`5
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`20
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`25
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`35
`
`SUMMARY OF THE INVENTION
`The object of the invention is to provide a method
`requiring, on the one hand, only little technological effort
`and where, on the other hand, metallization discontinuities
`and hollow spaces in the region of the contact opening
`places are reliably avoided.
`According to the invention there are provided the follow
`ing steps:
`a) opening of the oxide layer at least over those semicon
`ductor Zones that are to be contacted;
`b) application of a single or double-layered SIPOS pas
`sivation over the entire area of the surface of the
`semiconductor body;
`c) if a double layered SIPOS passivation is used, removal
`of the upper layer of the double-layered SIPOS passi
`vation over those zones that are to be contacted;
`d) application and structuring of metallization on the
`SIPOS passivation at desired contact locations corre
`sponding to those contact openings from which previ
`ously the upper layer of the double-layered SIPOS
`passivation was removed when using a double layered
`passivation; and
`e) heat treatment (annealing) of the semiconductor body.
`Accordingly, at the same time as the oxide etching takes
`place before the application of the SIPOS double layer over
`the entire area, the oxide layers that have been created in the
`contact zones while diffusion of base and emitter has taken
`place are removed by a wet etching process. This is followed
`by the application of a single or double-layered SIPOS
`passivation. If a double-layered SIPOS passivation is used,
`
`2
`only the top layer is removed by etching in the subsequent
`contact opening process.
`The particular advantages resulting from the invention are
`that hollow spaces between the metallization and passivation
`layers, in which contamination with corrosive effects can
`collect, and discontinuities in the metallization are avoided
`simply by making minor changes to individual process steps
`and with modified masks, without there being a need to
`provide additional masks or process steps or indeed to
`develop a new process.
`BRIEF DESCRIPTION OF THE DRAWINGS
`An embodiment example of the process according to the
`invention will now be shown in the drawings and be
`described in more detail below.
`The FIGS. 1a to 1e show the sketched cross-section of a
`partial semiconductor body with the Zones, layers and met
`allization that are relevant to the invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`FIG. 1a shows, on the basis of a NPN transistor, a
`semiconductor body 1 comprising, an n-doped substrate 2,
`p-doped base zones 3 included in it, and an oxide layer 5
`situated on the surface of the substrate 2 having with the
`base zones 3 being included in the substrate 2 by means of
`an already known process called base diffusion. In a further
`process step known as emitter diffusion or emitter drive in,
`higher-doped and n-conductive emitter zones 4 are included
`in the substrate 2 and in the base zones 3.
`FIG. 1b shows the state that results after the oxide layer
`5 has been removed by means of an etching process at the
`junction termination and partially from the base and emitter
`Zones 3 and 4.
`The removal of the oxide layer 5 over the entire surface
`area by means of an etching process, requiring no mask, is
`another possibility for the process sequence described
`above. This variant should be selected if a he loss can be
`accepted and it is of greater importance for the user to have
`one mask less to make.
`FIG. 1c shows the semiconductor body1 with the double
`layered SIPOS passivation layer, made up of N-SIPOS 6a
`and O-SIPOS 6b, applied over the whole surface area.
`The so-called photo lithography process (coating with
`photoresist, mask alignment, exposure to light) follow on
`from passivation. As shown in FIG. 1d, the N-SIPOSlayer
`6a is then removed in an etching process at all those places
`where contacting is to take place later. The so-called contact
`openings 8 in the N-SIPOS layer result from this. The
`surface of the semiconductor body 1 is then vaporized with
`aluminum over the entire Surface and structured in a further
`photo lithography and etching process.
`As can be seen from FIG. 1e, the metallization 7, which
`is preferably of aluminum is applied directly to the non
`removed O-SIPOSlayer 6b on the contact openings 8 (FIG.
`1d) made in the previous process step.
`It has been found that, once the intermediate steps of
`photoresist removal and cleaning have taken place, the
`aluminum of the metallization 7 migrates into the silicon
`through the O-SIPOS layer 6b during the subsequent heat
`treatment (or annealing), and that in accordance with all test
`results obtained so far a very good contact is formed which
`has a high current carrying capacity.
`The annealing of the metallization takes place in a con
`ventional heating furnace at a temperature of between 450°
`C. and 500° C.
`
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`Petitioner Canadian Solar Inc. - Ex. 1045, p. 4
`
`

`

`5,661,079
`
`5
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`10
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`3
`The process steps that follow, known to the expert in this
`field and therefore not shown in the Figures, include the
`so-called back-side process in which the back-side of a
`wafer is coated with, for example, a chrome-nickel-gold
`layer in order to ensure a low transition resistance and a high
`current carrying capacity for this contact which is generally
`used as a collector connection.
`The process described here is suitable for contacting of
`SIPOS passivated semiconductor zones in diode, transistor,
`GTO, IGBT, Power-MOS or IC structures.
`What is claimed is:
`1. Process for contacting SIPOS passivated semiconduc
`tor Zones of a semiconductor body with at least one pn
`junction, and with the surface of the semiconductor body
`being protected by an oxide layer, wherein said process
`involves the following process steps:
`a) opening the oxide layer at least over those semicon
`ductor Zones that are to be contacted;
`b) applying a double-layered SIPOS passivation over the
`entire area of the surface of the semiconductor body;
`c) removing only the upper layer of the double-layered
`SIPOS passivation over those zones that are to be
`contacted to provide contact openings in the upper
`layer of the SIPOS passivation;
`d) applying and structuring metallization on the lower
`layer of the double-layered SIPOS passivation within
`those contact openings from which previously the
`upper layer of the double-layered SIPOS passivation
`was removed; and
`e) heat treating (annealing) the semiconductor body.
`2. Process in accordance with claim 1, wherein the
`double-layered SIPOS passivation is made up of a nitrogen
`doped N-SIPOSlayer and an oxygen-doped O-SIPOS layer,
`where the O-SIPOSlayer is applied first to the surface of the
`semiconductor body and then the N-SIPOS layer on the
`O-SIPOS layer.
`3. Process in accordance with claim 1, wherein the single
`SIPOS passivation layer is made up of an oxygen-doped
`O-STPOS layer that is applied to the surface of the semi
`conductor body.
`4. Use of the process in accordance with claim 1 for the
`production of diode, transistor, GTO, IGBT, Power-MOS or
`IC structures.
`5. Process for contacting SIPOS passivated semiconduc
`45
`tor Zones of a semiconductor body having at least one pn
`
`35
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`25
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`4
`junction, with the surface of the semiconductor body being
`protected by an oxide layer, said process comprising the
`following process steps:
`a) providing openings in the oxide layer at least over those
`semiconductor zones of the semiconductor body to be
`contacted;
`b) applying a SIPOS passivation over the entire surface
`area of the semiconductor body;
`c) applying and structuring metallization on the layer of
`SIPOS passivation over the portions of the semicon
`ductor body that are to be contacted; and,
`d) heat treating (annealing) the semiconductor body to
`cause the metallization to contact the semiconductor
`body surface via the layer of SIPOS passivation.
`6. Process in accordance with claim 5 wherein the SIPOS
`passivation is a single SHPOS passivation layer.
`7. Process in accordance with claim 5 wherein the step of
`heat treating is carried out at 450°-500° C.
`8. Process in accordance with claim 5 wherein the SIPOS
`passivation layer is a double-layered SIPOS passivation
`including an upper SIPOS passivation layer and a lower
`SIPOS passivation layer; said process further comprises
`removing, prior to said step of applying and structuring, only
`the upper layer of the double-layered SIPOS passivation
`over those portions of the semiconductor body to be con
`tacted to provide openings in the upper SIPOS passivation
`layer; and said step of applying and structuring includes
`applying the metallization directly on the lower SiPOS
`passivation layer within the openings found in the upper
`SIPOS passivation layer.
`9. The process in accordance with claim 8 wherein the
`double-layered SIPOS passivation is formed of a nitrogen
`doped N-SIPOSlayer and an oxygen-doped O-SIPOSlayer,
`where the O-SIPOSlayer is applied first to the surface of the
`semiconductor body and then the N-SIPOS layer is applied
`on the O-SIPOS layer.
`10. Process in accordance with claim.9 wherein aluminum
`is used for the metallization.
`11. Process in accordance with claim3 wherein aluminum
`is used for the metallization.
`12. Process in accordance with claim2 wherein aluminum
`is used for the metallization.
`
`Petitioner Canadian Solar Inc. - Ex. 1045, p. 5
`
`