2506
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
`
`Impact of Ex-Situ and In-Situ Cleans on the
`Performance of Bipolar Transistors With Low
`Thermal Budget In-Situ Phosphorus-Doped
`Polysilicon Emitter Contacts
`
`Ahmad Ismat Abdul Rahim, Chris D. Marsh, Peter Ashburn, and G. R. Booker
`
`Abstract—This paper investigates the effects of an in-situ
`hydrogen bake and an ex-situ hydroflouric acid (HF) etch prior to
`polysilicon deposition on the electrical characteristics of bipolar
`transistors fabricated with low thermal budget in-situ phosphorus-
`doped polysilicon emitter contacts. Emitter contact deposition
`in a UHV-compatible low pressure chemical vapor deposition
`(LPCVD) cluster tool
`is also compared with deposition in a
`LPCVD furnace. Transmission electron microscopy (TEM) and
`secondary ion mass spectroscopy (SIMS) are used to characterize
`the emitter contact material and the interface structure and a
`comparison is made with Gummel plots and emitter resistances
`on bipolar transistors. The SIMS results show that an in-situ
`hydrogen bake in a cluster tool gives an extremely low oxygen
`1013 cm 2, compared with 7.7
`dose at the interface of 6.3
`1014 and 2.9
`1015 cm 2 for an ex-situ HF etch and deposition
`in a cluster tool or a LPCVD furnace, respectively. TEM shows
`that the in-situ hydrogen bake results in single-crystal silicon
`with a high density of defects, including dislocations and twins.
`The ex-situ HF etch gives polycrystalline silicon for deposition
`in both a cluster tool and a LPCVD furnace. The single-crystal
`silicon emitter contact has an extremely low emitter resistance
`of 21
` m2 in spite of the high defect density and the light
`emitter anneal of 30 s at 900 C. This compares with emitter
`resistances of 151 and 260
` m2 for the polycrystalline silicon
`contacts produced using an ex-situ HF etch and deposition in a
`cluster tool or a LPCVD furnace, respectively. These values of
`emitter resistance correlate well with the interface oxygen doses
`and the structure of the interfacial oxide layer. The high defect
`density in the single-crystal silicon is considered to be due to
`1019 cm 3) in the
`the high concentration of phosphorus ( 5
`as-deposited layers.
`in-situ doped
`Index Terms—Bipolar transistor, cluster tool,
`polysilicon, polycrystalline silicon, polysilicon, polysilicon emitter.
`
`I. INTRODUCTION
`
`P OLYSILICON emitter contacts [1] have become a vital
`
`part of today’s bipolar and BiCMOS technologies because
`they provide a means of realizing an exceptionally shallow
`
`Manuscript received June 24, 1999; revised August 17, 2000. This work was
`supported by the EPSRC through the award of a research contract and the Uni-
`versiti Sains Malaysia through the award of a studentship. The review of this
`paper was arranged by Editors P. Asbeck and T. Nakamura.
`A. I. A. Rahim and P. Ashburn are with the Department of Electronics and
`Computer Science, University of Southampton, Southampton SO17 1BJ, U.K.
`(e-mail: pa@ecs.soton.ac.uk).
`C. D. Marsh and G. R. Booker are with the Department of Materials, Univer-
`sity of Oxford, Oxford OX1 3PH, U.K.
`Publisher Item Identifier S 0018-9383(01)09061-X.
`
`emitter/base junction while maintaining a reasonable peripheral
`emitter/base capacitance. In polysilicon emitter contacts, an
`interfacial oxide layer is invariably present at the polysilicon/
`silicon interface, which has the advantage of increasing the
`current gain [2], [3] but the disadvantage of increasing the
`emitter resistance of the transistor [4]–[7]. A considerable
`amount of work has been published in the literature on the
`effects of the interfacial oxide on the base current [8]–[11] and
`emitter resistance [4]–[7], [12], [13] of polysilicon emitter con-
`tacts. It has been found that the nature of the interfacial oxide
`is significantly influenced by a number of factors, including
`the type of ex-situ clean (typically an HF etch) used prior to
`polysilicon deposition [9], [14],
`the polysilicon deposition
`conditions [15], [16], and the subsequent annealing conditions
`[8]. A common requirement in all the work mentioned above
`is the need to achieve a well controlled interfacial oxide that
`gives low values of emitter resistance.
`The use of a cluster tool for polysilicon deposition is one ap-
`proach that has been used to achieve good control over the in-
`terfacial oxide. Cluster tools are designed to integrate several
`process steps in one system, so in the context of polysilicon
`emitter contacts a cluster tool can be used to carry out an in-situ
`interface clean prior to the deposition of in-situ doped polysil-
`icon [17]–[25]. Berthold et al. [23], using an ex-situ HF dip
`etch and reoxidation in a cluster tool, showed that the interfacial
`oxide can be varied in a controlled manner from 0.2–1.0 nm.
`This approach allows the interfacial oxide thickness to be op-
`timized to give an improved gain and an acceptable value of
`emitter resistance [17], [19]–[23]. For example, Decoutere et
`al. [19] and Simeon et al. [20] showed that an interfacial oxygen
`dose of 2.6
`10
`cm (equivalent to a uniform layer of thick-
`ness
`0.5 nm, assuming that the oxide is stoichiometric SiO )
`gave an emitter resistance of 170–200
`m and at the same
`time a current gain enhancement by a factor of two. This was
`achieved by carrying out an in-situ HF vapor etch followed by
`dry reoxidation in a cluster tool. Similar results were obtained
`by Hendriks [17], who grew interfacial oxides with thicknesses
`of 0.5–1.0 nm, and obtained an emitter resistance of 100
`m
`and a gain improvement by a factor of two. Other authors have
`used an in-situ HF vapor etch [17]–[21] in a cluster tool and
`obtained emitter resistances of 90 [17], 74–80 [22] and 106
`m [19], [20]. However, for deep submicron polysilicon
`emitters, lower emitter resistance values are required.
`
`0018–9383/01$10.00 © 2001 IEEE
`
`HANWHA 1034
`
`

`

`RAHIM et al.: IMPACT OF EX-SITU AND IN-SITU CLEANS ON THE PERFORMANCE OF BIPOLAR TRANSISTORS
`
`2507
`
`A related area of research where surface cleaning techniques
`are of paramount
`importance is low temperature epitaxy
`[26]–[32]. Two alternative approaches have been used to
`generate a clean surface prior to epitaxy. In the first approach,
`an ex-situ HF etch is used to give a hydrogen-passivated,
`hydrophobic silicon surface. This hydrogen passivated surface
`is air-stable and remains oxide-free for around 10 min [33].
`Using this method, device quality Si and SiGe epi-layers were
`obtained at 550 C or lower without employing any in-situ
`surface cleaning process. In the second approach, an in-situ
`hydrogen bake is used to desorb the surface oxide prior to
`growth [34]. The surface oxide is generally removed by thermal
`desorbtion at a temperature above 800 C in hydrogen or above
`950 C in ultrahigh vacuum [34].
`The use of a cluster tool for emitter contact deposition of-
`fers the prospect of achieving very low values of emitter re-
`sistance as a result of the clean growth environment and the
`ability to carry out an in-situ clean immediately prior to growth
`of the emitter contact material. However, to date, little has been
`published on the best combination of ex-situ and in-situ cleans
`needed to achieve this goal, particularly under conditions where
`low thermal budget emitter anneals are used. In this paper, a
`comparison is made of the effects of an ex-situ HF etch and an
`in-situ hydrogen bake emitter contact clean on the performance
`of bipolar transistors given low thermal budget emitter anneals.
`The deposited layers are in-situ doped with phosphorus rather
`than arsenic, because it has a higher diffusivity and hence, is
`potentially a better candidate for low thermal budget polysil-
`icon emitters. A comparison is made between the in-situ phos-
`phorus doped and conventional arsenic implanted emitter con-
`tacts. TEM images show that the in-situ hydrogen bake results in
`an emitter contact that is single-crystal silicon with a high den-
`sity of defects, including dislocations and twins. Bipolar tran-
`sistors fabricated using this high defect density silicon emitter
`m even after
`contact have an emitter resistance as low as 21
`a light emitter anneal of only 30 s at 900 C.
`
`II. EXPERIMENTAL PROCEDURE
`A very light emitter anneal of 30 s at 900 C was chosen
`for this work in order to investigate the properties of low
`thermal budget polysilicon emitter contacts of the type that
`may be required in future deep submicron technologies or SiGe
`HBT technologies. This thermal budget is considerably lighter
`than that currently used for production polysilicon emitter
`contacts, where the emitter anneal is generally carried out at a
`temperature in the range 1000–1055 C [25], [35]–[39]. With a
`thermal budget as low as 30 s at 900 C, it is difficult to obtain
`sufficient out-diffusion of dopant from the polysilicon to push
`the emitter/base depletion region away from the polysilicon/sil-
`icon interface. This is particularly problematic for the arsenic
`implanted control devices, because of the lower diffusion
`coefficient of arsenic than phosphorus. In order to facilitate
`the comparison of in-situ doped phosphorus emitters with ion
`implanted arsenic emitters, a low doped emitter was fabricated
`by ion implantation prior to emitter fabrication. The doping was
`chosen to be low enough to minimize Auger recombination, so
`that the low-doped emitter was transparent to minority carriers
`
`injected from the base [40]. This has the effect of making the
`base current very sensitive to the properties of the interface.
`The starting material used for this work was (100) n on n+ ma-
`terial with an epitaxial resistivity of 0.5
`cm. The base was fab-
`10
`cm boron at 80 keV through
`ricated by implanting 2.5
`an 80 nm thermal oxide layer and then annealing for 150 min at
`1025 C in nitrogen. The low-doped emitter was used in all the
`10
`cm
`devices and was formed by implanting 70 keV, 5
`phosphorus through an 80 nm screen oxide and annealing for
`120 minutes at 950 C in nitrogen. SIMS profiles indicate that
`this process delivers a low-doped emitter with a width of 220 nm
`10
`cm .
`and a peak doping concentration of 1
`Two interface cleans carried out prior to growth were investi-
`gated. The first was a clean which is commonly used in polysil-
`icon emitter contacts, namely an ex-situ etch in 7 : 1 buffered
`HF for 15 s. The second was a clean that is commonly used
`in low temperature epitaxy [26]–[34] and is a combined ex-situ
`and in-situ clean. The ex-situ clean comprised an RCA clean
`plus a 100 : 1 HF dip etch for half the time taken for the wafer
`to become hydrophobic. The in-situ clean consisted of a 5 min
`in-situ hydrogen bake at 900 C in 100 sccm of hydrogen at
`1 Torr. The purpose of the hydrogen bake was to remove the in-
`terfacial oxide remaining after the RCA clean and the 100 : 1 HF
`dip etch. In-situ phosphorus doped polysilicon was deposited in
`a Thermo VG Semicon CV 200 System [41], which consists of
`two identical growth chambers linked by a load lock. The depo-
`sition time was 13 min and used a mixture of 100% SiH and
`0.01% PH with flow rates of 100 and 50 sccm at a temperature
`of 750 C and a pressure of 1 torr.
`For comparison purposes, a conventional arsenic implanted
`polysilicon emitter contact was also fabricated. This was given
`an ex-situ HF etch, and 200 nm of polysilicon was deposited
`in a conventional ASM LPCVD furnace in 25%, 200 sccm of
`SiH at 610 C and 0.39 Torr. The polysilicon was doped by
`10
`cm arsenic at 45 keV. A low
`implanting a dose of 1
`temperature oxide was deposited at 400 C on all devices to pre-
`vent dopant loss during the 30 s emitter anneal at 900 C. An
`unpatterned in-situ phosphorus doped test wafer (i.e., not a de-
`vice wafer) was also produced. This wafer was given a hydrogen
`bake, a 20 min deposition using the same growth conditions as
`the device wafers and was not given an emitter anneal.
`Electrical characterization in the form of Gummel plots and
`emitter resistance measurements of the transistors were per-
`formed on a HP 4145 parameter analyzer attached to an HP 9133
`personal computer. TEM and SIMS analysis were performed on
`the same wafers as the devices to determine the micro-structure
`and the phosphorus and oxygen profiles. The TEM analysis was
`cross-sections and
`on-axis images
`carried out using
`were obtained.
`
`III. RESULTS
`A. Material and Interface Characterization
`Fig. 1 shows cross-section TEM images of the three types
`of sample after completion of device processing (i.e., after the
`emitter anneal). Fig. 1(a) shows the sample given an ex-situ HF
`etch prior to the deposition of in-situ phosphorus doped polysil-
`icon. The layer is 350 nm thick and TEM selected area diffraction
`
`

`

`2508
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
`
`Fig. 2. Cross section TEM image of an unpatterned sample after deposition.
`The sample was given an in-situ hydrogen bake prior to in-situ phosphorus-
`doped deposition.
`
`in Fig. 2, which shows a TEM image of an unpatterned wafer
`immediately after deposition. The wafer was given a hydrogen
`bake at 900 C prior to deposition of the in-situ phosphorus
`doped layer and not given an emitter anneal. The layer is 850 nm
`thick and shows a 90-nm-wide region immediately above the in-
`terface that is relatively defect-free below a region that contains
`a high density of defects. The fact that the layer is single-crystal,
`i.e., epitaxial growth has occurred, suggests that the interfacial
`oxide was not continuous after the hydrogen bake. The thicker
`layer in this sample compared to that in Fig. 1(b) is due to the
`use of a longer growth time.
`Fig. 3 shows SIMS profiles for layers after the emitter anneal.
`Fig. 3(a) shows the phosphorus SIMS profiles for the in-situ
`doped layers given either an in-situ hydrogen bake or an ex-situ
`HF etch. The phosphorus concentration is between 5 and 8
`10
`cm for both layers over the majority of the thickness
`of the layer. However, for the layer given a hydrogen bake, the
`10
`phosphorus concentration decreases to a value of 3.5
`cm immediately adjacent to the interface. Interface peaks
`occur for both layers, which are presumably due to segregated
`phosphorus at the original silicon surface. The ex-situ HF etch
`sample is 350 nm thick, and the in-situ hydrogen bake sample
`is 570 nm thick. The deposition time was the same for the two
`layers, so the difference in thickness suggests either a differ-
`ence in incubation time for layers grown after an ex-situ HF etch
`and an in-situ hydrogen bake or a difference in growth rate for
`polysilicon and single-crystal silicon.
`Fig. 3(b) shows oxygen SIMS profiles for the phosphorus
`in-situ doped layers and the arsenic implanted control layer. For
`the arsenic implanted control sample there is a large oxygen in-
`10 /cm . For the
`terface peak with an integrated dose of 2.9
`in-situ phosphorus-doped layer given an HF etch, there is a sim-
`10 /cm , i.e., 3.8
`smaller. For
`ilar peak with a dose of 7.7
`the in-situ phosphorus-doped layer given a hydrogen bake, there
`10 /cm , i.e., a further
`is a similar peak with a dose of 6.3
`12 smaller. These three oxygen doses correspond to equivalent
`oxide layer thicknesses of 0.66, 0.17 and 0.014 nm respectively.
`The latter thickness for the in-situ phosphorus doped layer given
`a hydrogen bake corresponds to significantly less than a mono-
`layer of silicon dioxide. Hence, the SIMS results also indicate
`that when the layer deposition commenced the interfacial oxide
`layer was discontinuous.
`
`Fig. 1. Cross-section of TEM images of the device samples after the emitter
`anneal of 30 s at 900 C. (a) Ex-situ HF etch and in-situ phosphorus doped
`deposition. (b) In-situ hydrogen bake at 900 C and in-situ phosphorus doped
`deposition. (c) Ex-situ HF etch and arsenic implanted LPCVD deposition.
`
`patterns (not shown) show that it is polycrystalline. There is no
`significant epitaxial regrowth of the polysilicon, though there is
`some evidence of roughening at the polysilicon/silicon interface
`that is indicative of small holes in the interfacial oxide and local
`epitaxial regrowth. Fig. 1(b) shows the sample given an in-situ
`hydrogen bake prior to the deposition of in-situ phosphorus
`doped material. The layer is 570 nm thick and TEM selected
`area diffraction patterns (not shown) show that it is single-crystal
`silicon. The dark line in the micrograph is due to small discrete
`balls of interfacial oxide at the position of the original interface.
`The single-crystal layer contains different types of defects,
`including dislocations and twins. The defect density increases
`300 nm, and
`with distance from the interface up to a depth of
`between this depth and the surface the layer contains a high
`density of defects. Fig. 1(c) shows the arsenic implanted control
`device. This layer is 160 nm thick and TEM selected area diffrac-
`tion patterns indicate that it is polycrystalline, as expected. The
`polysilicon/silicon interface is smooth, indicating that there is
`little or no interfacial oxide break up or epitaxial regrowth.
`The in-situ phosphorus doped layers given the hydrogen bake
`are single-crystal silicon even after deposition. This is illustrated
`
`

`

`RAHIM et al.: IMPACT OF EX-SITU AND IN-SITU CLEANS ON THE PERFORMANCE OF BIPOLAR TRANSISTORS
`
`2509
`
`Fig. 4. Gummel plots for transistors produced using the different types of
`ex-situ and in-situ cleans and different deposition systems. T = 300 K, V
`=
`0 V, and A = 80  320 m .
`
`Fig. 3. SIMS profiles of layers produced using the different ex-situ and
`in-situ cleans and the different deposition systems: (a) phosphorus profiles and
`(b) oxygen profiles.
`
`B. Electrical Characterization
`Fig. 4 shows Gummel plots for transistors with in-situ phos-
`phorus doped layers given an in-situ hydrogen bake or an ex-situ
`HF etch, and for comparison, a transistor with a conventional ar-
`senic implanted polysilicon emitter. The lowest values of base
`current are obtained for the transistor with the arsenic implanted
`polysilicon emitter and the highest values for the transistor with
`the in-situ phosphorus doped emitter given the hydrogen bake.
`The difference in base current between these two types of tran-
`sistor is a factor of 3.8 at a base/emitter voltage of 0.6 V. A com-
`parison of the two in-situ phosphorus doped transistors shows
`that the HF etch gives a lower base current than the hydrogen
`bake. The difference is a factor of 1.6 at a base/emitter voltage
`of 0.6 V. A comparison of the Gummel plots with the oxygen
`SIMS profiles in Fig. 3(b) shows that a decreasing oxygen inter-
`face dose correlates with an increasing base current. A compar-
`ison with the TEM results in Fig. 1 indicates that the lowest base
`currents are obtained when the interfacial oxide is intact and the
`silicon is polycrystalline, and the highest base current when the
`interfacial oxide is broken up and the silicon is single-crystal.
`These results are consistent with a base current dominated by
`
`Fig. 5. Ning–Tang intercept [42] as a function of reciprocal emitter area
`for transistors produced using the different types of ex-situ and in-situ cleans
`and different deposition systems. The Ning–Tang intercept was measured on
`different geometry transistors and the slope of the graph gives the specific
`interface resistivity [43].
`
`hole transport through the interfacial oxide layer when the oxide
`is intact and through holes in the oxide when the oxide is broken
`up [1].
`Fig. 5 shows the determination of the specific interface re-
`on the three types of transistor using the Ning–
`sistivity
`Tang method [42]. For each type of device, the emitter resis-
`tance was measured on devices with different geometries and
`the Ning–Tang intercept [42] plotted as a function of reciprocal
`emitter area. A linear regression was performed through the data
`given by the
`points with the specific interface resistivity
`m
`slope of the linear fit [43]. It can be seen that
`for the in-situ phosphorus-doped transistors given the hydrogen
`m for the equivalent transistors given
`bake and
`m
`the HF etch. This compares with a value of
`for the transistor with a conventional arsenic implanted polysil-
`icon emitter. A comparison with the oxygen SIMS profiles in
`
`

`

`2510
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
`
`Fig. 6. Comparison of measured and literature values of base saturation
`current density as a function of interface oxygen dose. T = 300 K.
`
`Fig. 3(b) shows that a decreasing interface oxygen dose corre-
`lates with a decreasing emitter resistance. A comparison with
`the TEM results in Fig. 1 indicates that the highest emitter re-
`sistances are obtained when the interfacial oxide is intact and the
`deposited silicon is polycrystalline and the lowest emitter resis-
`tances when the interfacial oxide is broken up and the deposited
`silicon is single-crystal. This is consistent with a current dom-
`inated by electron transport through the interfacial oxide layer
`when the oxide is continuous and through holes in the oxide
`when the oxide is broken up [1].
`
`IV. DISCUSSION
`The values of base saturation current density obtained in this
`work are compared with those reported in the literature in Fig. 6,
`where they are plotted against integrated interface oxygen dose.
`In cases where the literature data was taken at a temperature other
`than 300 K, a correction has been applied using the equation
`, where the symbols have their usual
`meaning. Fig. 6 shows that the results obtained in this work are in
`reasonable agreement with those in the literature, although there
`is a wide spread in the data at interface oxygen doses between
`10
`and 3.1
`10
`cm . The data shows that the base
`1.3
`saturation current density decreases with increasing interface
`oxygen dose, with the rate of decrease being slow for low oxygen
`doses and fast for high oxygen doses. The slow rate of decrease
`in base saturation current density corresponds to an interfacial
`oxide that is broken up, and the fast rate of decrease corresponds
`to an interfacial oxide that is continuous. This result indicates
`that the base saturation current is dominated by hole transport
`through the interfacial oxide layer [1]. When the interfacial
`oxide is broken up, there is little impediment to the flow of holes
`across the interface, so a high base saturation current is obtained.
`In contrast, when the interfacial oxide layer is continuous, there
`is a barrier to hole transport across the interface, and the base
`saturation current is limited by mechanisms such as tunneling
`[2] and thermionic emission [44].
`Fig. 7 compares the interface oxygen doses obtained in this
`work for the different ex-situ and in-situ cleans with those re-
`
`Fig. 7. Comparison of measured and literature values of interface oxygen dose
`for different ex-situ and in-situ cleans.
`
`ported in the literature [17], [20], [35], [36]. In general, this
`figure shows that the cluster tool delivers lower values of oxygen
`dose than the LPCVD furnace, by a factor of typically three.
`Similar results have been reported by Simeon et al. [20], where
`it was found that the cluster tool produces typically a factor of
`1.9 lower values of oxygen dose than the LPCVD furnace. For
`the ex-situ HF etch followed by polysilicon deposition in the
`10
`cm
`LPCVD furnace, the interface oxygen dose of 3
`obtained in this work is in the middle of the reported range of 2
`10
`cm . For the HF dip followed by polysilicon depo-
`to 5
`10
`sition in the cluster tool, our interface oxygen dose of 7.7
`cm is at the bottom of the range of reported values, but nev-
`10
`cm . The
`ertheless close to the reported values of 1.0
`interface oxygen doses for an in-situ HF vapor etch in a cluster
`tool are similar to those for an ex-situ HF dip etch. This result
`indicates that the wafer transfer from the ex-situ HF etch to the
`cluster tool is sufficiently rapid to avoid the growth of additional
`interfacial oxide. This conclusion is consistent with the work of
`Meyerson et al. [33] who showed that the hydrogen passivated
`surface produced by an HF dip etch was stable in air for 10 min-
`utes. For the hydrogen bake, our interface oxygen dose of 6.3
`10
`cm is 14.3
`lower than the lowest value of Simeon et
`al. [20]. This result demonstrates the effectiveness of the hy-
`drogen bake for eliminating the interfacial oxide. Sun et al. [45]
`have also reported the use of an in-situ hydrogen bake prior to
`selective deposition of the polysilicon emitter, but no value of
`interface oxygen dose was given. For completeness, Fig. 7 also
`shows the interface oxygen doses for an ex-situ RCA clean per-
`formed in this work and an in-situ dry/wet ozone clean reported
`in the literature [35]. The latter has a higher interface oxygen
`dose than the HF etch, but was reported to have the advantages
`of removing hydrocarbon residues from the silicon surface and
`of stabilizing the interfacial oxide with time [35].
`Fig. 8 compares the values of emitter resistance obtained in
`this work with those reported in the literature. The values of
`emitter resistance taken from the literature have been converted
`m using the quoted values of emitter area [17],
`into units of
`[20]. For the devices (in this work) given an ex-situ HF etch (with
`10
`using a cluster tool and 3
`interface oxygen doses of 7.7
`
`

`

`RAHIM et al.: IMPACT OF EX-SITU AND IN-SITU CLEANS ON THE PERFORMANCE OF BIPOLAR TRANSISTORS
`
`2511
`
`V. CONCLUSIONS
`A study has been made of the effects of an ex-situ HF etch
`and an in-situ hydrogen bake on the emitter resistance and base
`current of low thermal budget, in-situ phosphorus-doped polysil-
`icon emitter contacts for bipolar transistors. SIMS measurements
`have shown that an in-situ hydrogen bake in a cluster tool gives
`10
`cm , while an
`a very low interface oxygen dose of 6.3
`10
`cm when
`ex-situ HF etch gives a dose of either 7.7
`10
`cm
`the deposition is performed in a cluster tool or 2.9
`when it is performed in a LPCVD furnace. TEM shows that the
`in-situ hydrogen bake results in a material that is single-crystal
`silicon with a high density of defects, including dislocations and
`twins. Bipolar transistors fabricated using this high defect den-
`sity silicon emitter contact have an emitter resistance as low as
`m even after a light emitter anneal of 30 s at 900 C. This
`21
`lower than the emitter resistance obtained
`is a factor of 7.2
`for cluster tool deposition after an ex-situ HF etch and 12.4
`lower than that obtained for LPCVD furnace deposition after
`an ex-situ HF etch. The lower value of emitter resistance cor-
`relates with an increased base current by a factor of 3.8 for the
`two extreme cases. The high concentration of phosphorus in the
`deposited layers is considered to be the cause of the high defect
`density. In general, the very low value of emitter resistance ob-
`tained with the high defect density single-crystal silicon emitter
`contact suggests that this material could prove useful in future
`deep submicron Si bipolar or SiGe HBT technologies where the
`thermal budget is severely constrained.
`
`REFERENCES
`[1] I. R. C. Post, P. Ashburn, and G. Wolstenholme, “Polysilicon emitters
`for bipolar transistors: A review and re-evaluation of theory and ex-
`periment,” IEEE Trans. Electron Devices, vol. 39, pp. 1717–1731, July
`1992.
`[2] H. C. De Graff and J. G. De Groot, “The SIS tunnel emitter: A theory
`for emitters with thin interfacial layers,” IEEE Trans. Electron Devices,
`vol. ED-26, pp. 1771–1776, 1979.
`[3] P. Ashburn and B. Soerowirdjo, “Comparison of experimental and the-
`oretical results on polysilicon emitter bipolar transistors,” IEEE Trans.
`Electron. Devices, vol. ED-31, pp. 853–860, 1984.
`[4] T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of
`silicon bipolar devices,” in IEDM Tech. Dig., vol. 26, 1979, pp. 473–476.
`[5] E. F. Chor, P. Ashburn, and A. Brunnschweiler, “Emitter resistance of
`arsenic- and phosphorus-doped polysilicon emitter transistors,” IEEE
`Electron Device Lett., vol. EDL-6, pp. 516–518, 1985.
`[6] P. A. Potyraj and D. W. Greve, “Emitter resistance in polysilicon emit-
`ters and the influence of interfacial oxides,” in Proc. BCTM Tech. Dig.,
`Minneapolis, MN, 1987, pp. 82–85.
`[7] E. Crabbe, S. Swirhun, J. Del Alamo, F. F. W. Pease, and R. M. Swanson,
`“Majority and minority carrier transport in polysilicon emitter contacts,”
`in IEDM Tech. Dig., Jan. 1986, pp. 28–31.
`[8] G. L. Patton, J. C. Bravman, and J. D. Plummer, “Physics, technology
`and modeling of polysilicon contacts for VLSI bipolar transistors,” IEEE
`Trans. Electron Devices, vol. ED-33, pp. 1754–1768, 1986.
`[9] P. A. Potyraj, D. Chen, M. K. Hatalis, and D. W. Greve, “Interfacial ox-
`ides, grain size and hydrogen passivation effects on polysilicon,” IEEE
`Trans. Electron Devices, vol. ED-26, p. 1771, 1979.
`[10] P. Ashburn, D. J. Roulston, and C. R. Selvakumar, “Comparison of
`experimental and computed results on arsenic- and phosphorus-doped
`polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices,
`vol. ED-34, pp. 1346–1353, 1987.
`[11] K. Sagara, T. Nakamura, Y. Tamaki, and T. Shiba, “The effect of thin
`interfacial oxide on the electrical characteristics of silicon bipolar de-
`vices,” IEEE Trans. Electron Devices, vol. ED-34, pp. 2286–2290, 1987.
`[12] J. M. C. Stork, M. Arienzo, and C. Y. Wong, “Correlation between the
`diffusive and electrical barrier properties of the interface in polysilicon
`contacted n+–p junctions,” IEEE Trans. Electron Devices, vol. ED-32,
`pp. 1766–1770, 1985.
`
`Fig. 8. Comparison of measured and literature values of emitter resistance as
`a function of interface oxygen dose.
`
`cm using a LPCVD furnace), the values of emitter re-
`10
`sistance are broadly similar to the values in the literature, though
`there is a large spread in the literature data. In spite of the large
`spread in emitter resistance values, it can be seen that the in-situ
`hydrogen bake gives a value of emitter resistance that is a factor
`of three lower than the lowest value reported in the literature.
`This result clearly demonstrates that the in-situ hydrogen bake
`gives extremely low values of emitter resistance. Sun et al. [45]
`have also used an in-situ hydrogen bake prior to the selective
`deposition of undoped polysilicon. The resulting polysilicon
`emitter bipolar transistors had emitter resistance values of less
`m . This is in good agreement with the value of
`than 30
`m obtained in this work. In contrast with our results,
`21
`Sun et al. [45] reported that the material was polycrystalline
`after deposition. This may be due to the fact that the layer was
`undoped or to the use of a H /HCl/SiH Cl gas mixture, rather
`than the H /SiH /PH gas mixture used in this work.
`The TEM image in Fig. 2 shows that the in-situ phosphorus-
`doped material given a hydrogen bake was single-crystal after
`growth with a high density of defects, but the silicon is rela-
`tively defect free in a 50-nm-thick region immediately above
`the interface. A comparison with the phosphorus SIMS pro-
`file in Fig. 3(a) shows that the phosphorus concentration de-
`10
`cm to 3.5
`10
`cm over
`creases from about 5
`a distance of 50 nm above the interface. This result suggests
`that the high phosphorus concentration may be responsible for
`the high density of defects in the top part of the silicon layer,
`with the decrease in phosphorus concentration adjacent to the
`interface the reason for the lower defect density in this region.
`SIMS measurements on silicon layers with high phosphorus
`concentrations tend to confirm this explanation. For example, in
`10
`layers with a uniform phosphorus concentration above 1
`cm , the high density of defects extends all the way from the
`surface to the interface. The defects might result from misfit due
`to the smaller tetragonal radius of phosphorus than silicon [46].
`High concentrations of phosphorus in silicon are well known to
`produce defects, for example dislocation networks in emitters
`implanted with a high dose of phosphorus [47]. Further work is
`underway to confirm the origins of the defects.
`
`

`

`2512
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
`
`[18]
`
`[13] J. S. Hamel, D. J. Roulston, C. R. Selvakumar, and G. R. Booker, “Two-
`dimensional analysis of emitter resistance in the presence of interfacial
`oxide breakup in polysilicon emitter bipolar transistors,” IEEE Trans.
`Electron Devices, vol. 39, pp. 2139–2146, 1992.
`[14] G. R. Wolstenholme, N. Jorgenson, P. Ashburn, and G. R. Booker, “An
`investigation of the thermal stability of the interfacial oxide in polycrys-
`talline silicon emitter bipolar transistors by comparing device results
`with high-resolution electron microscopy observations,” J. Appl. Phys.,
`vol. 61, pp. 225–233, 1987.
`[15] D. J. Doyle, J. D. Barrett, W. A. Lane, M. O’Neill, D. Bain, R. Baker,
`and P. J. Mole, “Comparison of bipolar npn polysilicon emitter interface
`formation at three different manufacturing sites,” IEEE Trans. Semicon-
`duc