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`An investigation of the thermal stability of the interfacial oxide in
`polycrystailine silicon emitter bipolar transistors by comparing device
`results with high-resolution electron microscopy observations
`G. A. Wolstenholme
`Department ofElectronics and Information Engineering, University ofSouthampton,
`Southampton, England
`
`N. Jorgensen
`Department ofMetallurgy and Science ofMaterials, University of Oxford, Oxford, England
`P. Ashburn
`Department ofElectronics and Information Engineering, University ofSouthampton,
`Southampton, England
`
`G. RA. Booker
`Department ofMetallurgy and Science ofMaterials, University ofOxford, Oxford, England
`
`(Received 6 May 1986; accented for publication 9 September 1986)
`
`A comparison is made between the results of high-resolution electron microscope observations
`and the electrical characteristics of polycrystalline silicon emitter bipolar transistors. Devices
`are fabricated with and without a deliberately grown interfacial oxide layer, and the thermal
`stability of this oxide layer is investigated by carrying out a preanneal at temperatures between
`800 and 1100 °C after polysilicon deposition, but prior to emitter implant and 900 °C drive-in.
`The electron microscope observations show that the deliberately grown interfacial oxide is of
`uniform thickness ~ 14 A, but breaks up when annealed at ~ 950°C and above, with “balling-
`up” occurring at ~ 1100°C. This correlates with a transistor gain that decreases from ~ 1400
`to ~ 40. The electron microscopy also shows that a thin interfacial oxide layer is present even
`when not deliberately grown. This oxide breaks up when annealed at ~ 900 °C and above, with
`“balling-up” occurring at ~ 1060 °C. This correlates with a transistor gain that decreases from
`~ 240 to ~ 50, Calculations of the effect that such interfacial oxide layers will have on the
`characteristics of polysilicon emitter bipolar transistors are made, and these predictions
`correlate well with the measured characteristics.
`
`L INTRODUCTION
`
`Polycrystailine silicon (“polysilicon”) is now widely
`used in bipolar technology as a means of making contact to
`the emitter and base of the transistor’ and this can lead toa
`dramatic improvement in both switching speed and packing
`density.°? An additional advantage of using a polysilicon
`emitter is that an improvement in gain by a factor of
`between 3 and 30 can be obtained compared with conven-
`tional transistors.* This improvement in gain can be partly
`attributed to the transport properties of the polysilicon? al-
`though this mechanism can only explain an improvement by
`a factor of ~3. The muchlarger gain improvements are ob-
`tained when a thin interfacial oxide layer is deliberately in-
`troduced between the polysilicon and single-crystal sili-
`con.*°” In this case the gain improvement can be attributed
`to tunneling through this oxide layer.* Eitoukhy and Roul-
`ston,”!° and later Yu et al.,'! have published unified theories
`that incorporate both these mechanisms, the formergiving a
`solution suitable for numerical implementation, the latter a
`versatile analytical sclution.
`If high-gain polysilicon emitter transistors incorporat-
`ing an interfacial oxide layer are to be used in commercial
`integrated circuit processes, it is important that the oxide
`layer is fully characterized in terms of thickness and wnifor-
`mity, and that it is stable during subsequent high-tempera-
`ture processing. Our previous structural studies’*"*° showed
`
`that the oxide layer progressively breaks up during high-
`temperature heat treatments. In order to investigate this be-
`havior in more detail and to relateit directly to device perfor-
`mance, we have carried out a detailed comparison of
`electrical results on polysilicon emitter transistors with
`structural results from high-resolution transmission elec-
`tron microscopy. The thermaistability ofthe oxide layer was
`investigated by carrying cut preanneais at temperatures
`between 800 and 1100 °C immediately after polysilicon dep-
`osition but prior to emitter implant and drive-in at 900 °C. In
`this way, the oxide layer could be subjected to a high-tem-
`perature heat treatment without significantiy affecting the
`rest of the emitter structure, and therefore changes in gain
`could be correlated directly with changes in the structure of
`the oxide layer.
`
`i. EXPERIMENT
`
`Twe types of polysilicon emitter bipolar transistor were
`fabricated using identical standard processing up to the sur-
`face treatment of the (100) silicon slices prior to polysilicon
`deposition. For the first type (RCA treatment), the slice was
`given a dip in buffered HF followed by an RCA clean*
`(NH,OB-H,O.:H,O as 1:1:5 for 16 min; HCi:H,O,:H,0 as
`1:1:6 for 10 min) to produce a surface oxide layer of nominal
`thickness ~ 15 A. For the second type (HF treatment), the
`slice was given a dip in buffered HF with the intention of
`
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`J. Appl. Phys. 64 (1), 1 January 1987
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`0021 -8879/87/010225-09$02.40
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`© 1986 American institute of Physics
`225
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`The interfacial oxide layer was seen as a thin bright band
`separating the silicon from the polysilicon. The band exhibit-
`ed a random wormlike contrast in the lattice-image micro-
`graphs, this being the characteristic behavior for an amor-
`phous material. The oxide layer was continuous and uniform
`with a thickness of ~14-+ 1 A and it followed the undula-
`tions ofthe surface of the silicon slice with an “amplitude” of
`~6-9 A (perpendicular to the interface) and a “wave-
`length” of ~ 200-400 A (parallelto the interface). The good
`uniformity of the oxide layer indicates that its structure had
`been little changed by the subsequent 900 °C preanneal and
`900 °C drive-in, and so Fig. 1 showsit in effect as it was when
`initially produced by the RCA treatment. The directly mea-
`sured oxide layer thickness of 14 A is in good agreementwith
`the values of 13-15 A obtained from ellipsometry,’ and 10-
`15 A obtained from Auger spectroscopy profiles,'® for sili-
`con slices given an RCA treatment. The TEM results are
`summarized in Table I.
`For specimens given an RCAtreatment, a 950 °C prean-
`neal and full processing, the interfacial oxide layer was non-
`uniform (Fig. 2}. Some regions had increased in thickness to
`a maximum of 19 A, some regions were thinner, and in some
`regions holes (B) were present in the layer. Small areas (C)
`of the polysilicon had been regrown through such heles to
`become single-crystal material with the same crystallo-
`graphic orientation as the underlyingsilicon, this being de-
`duced from the micrograph contrast and the alignment of
`
`
`Polysilicon
`
`Grain size
`(A)
`Fraction of
`interface ao Transistor
`regrown
`Surface
`Bulk
`gain
`
`03
`0.7
`0.97
`0.2
`6.95
`
`1200
`£200
`2000
`1200
`1200
`
`600
`1900
`1000
`406
`1600
`
`350
`90
`40
`240
`30
`
`Hi. TEM RESULTS
`
`For specimens given in an RCA treatment, a 900°C
`preanneal and full processing (Ast implant and 900°C
`drive-in}, cross-section micrographs of the interface region
`showed the single-crystal silicon with the characteristic
`(111), C111), and (200) lattice planes clearly delineated
`(Fig. 1}. The individual polysilicon grains only showedlat-
`tice planes when the grains were favorably oriented with
`respect to the electron beam, e.g., as at A. When such planes
`were observed in the individual polysilicon grains, they were
`in general not aligned with the planes present in the silicon.
`
`TABLE LL. Summary ofresults.
`
`
`
`Silicon
`slice
`surface
`treatment
`
`RCA
`RCA
`RCA
`RCA
`HF
`HF
`
`Interfacial oxide layer
`
`Preanneal
`temperature
`CC}
`
`900
`950
`1000
`1106
`None
`1006
`
`Maximum
`thickness
`{A}
`
`~i4
`~ 19
`~~ 22
`~ 55
`~8
`~50
`
`Geometry
`
`continuous
`broken up
`broken up
`balled up
`broken up
`balled up
`
`
`removing any native oxide which might have been present.*
`These surface layer treatments were immediately followed
`by the deposition of a ~0.4-um-thick layer of undoped
`LPCVDpolysilicon at ~ 610°C. One of each type of slice
`was given a 10 min preanneal in dry nitrogen at one ofseveral
`temperatures in the range 800-1100 °C in order to breakup
`the interfacial oxide iayer to different extents. The emitters
`of the transistors were then formed by implanting 1 10°°-
`em”*, 70-keV As* into the polysilicon and drivingit in at
`900 °C in wet oxygen for 30 min. The active emitter area was
`20 um by 18 um. The aluminium contact to the emitter was
`remote from the active emitter area, being madeavia polysil-
`FIG. 1. HREM micrograph of a fully processed specimen given an RCA
`icon track 60 um in length.
`treatment and a 900°C preanneal. Notethe interfacial oxide layer and the
`Detailed electrical measurements were carried out on
`polysilicon grain A. s/o-——single-crystal silicon; oxide—interfacial oxide
`the transistors including measurements of collector and base
`layer; poly—polysilicon layer.
`current as a function of base/emitter voltage. Unpatterned
`checkslices which had been given identical base and emitter
`processing were used for the TEM studies. Cross sections
`were prepared corresponding to the (O11) plane of the
`(100) single-crystal silicon slice by grinding, polishing, and
`argon ion-beam thinning. These were examined using a
`JEOL 200CX TEM with the electron beam aligned parallel
`io the [011] direction of the single-crystal silicon. High-
`resolution electron microscopy (HREM) was performed to
`give lattice images using conventional procedures. All of the
`specimens examined (except for that of Fig. 6} corre-
`sponded to the final processed slices and so the observed
`TEM structures could be directly correlated with the device
`results. Large numbers of micrographs were taken of each
`specimen in order to determine its characteristic structure.
`The micrographs of Figs. 1-6 are typical of those obtained,
`but de not show all the features described in the text.
`
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`J. Appl. Phys., Vol. 81, No. 1, 1 January 1987
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`FIG. 2. HREM micrograph ofa fully processed specimen given an RCA
`treatment and a 950 °C preanneal. Note the hole B in the interfacial oxide
`laver and the regrown polysilicon area C.
`
`FIG. 4. HREM micrograph of a fully processed specimen given an HF
`treatment and nce preanneal. Note the regrown polysilicon areas E.
`
`the lattice planes. The regrown areas had often spread out
`laterally in the polysilicon and so were sometimes wider than
`the holes in the oxide layer through which they had been
`grown. Individual areas extended typically 35 A along the
`interface and 35 A into the polysilicon. When the individual
`lengths of the regrown areas of the polysilicon were mea-
`sured along the interface and added together, this represent-
`ed ~0.3 of the total length of the interface.
`Forthe specimens given an RCA treatment, a 1000 °C
`preanneal and full processing (micrograph not included),
`the breakup of the interfacial oxide layer was more pro-
`nounced. Some regions had increased in thickness to a maxi-
`rum of 22 A, and more holes were present in the layer.
`However, no substantial “balling-up” of the layer had oc-
`curred, Individual regrown areasofthe polysilicon extended
`typically 120 A along the interface and 40 A into thepolysili-
`con. The fraction of the length of the interface that had re-
`grown was ~0.7.
`For specimens given an RCA treatment, a 1100°C
`preanneal and full processing, the breakup of the interfacial
`oxide layer was almost complete (Fig. 3), the layer now
`consisting mainly ofbails of oxide (ED) up to 55 A in diame-
`ter or worms ~ 30> 100 A across. Individual regrown areas
`of the polysilicon overlapped to give almost complete cover-
`age of the interface with the regrowth extending typically
`176 A into the polysilicon. The large difference between the
`
`
`
`oxide layer in the specimens given the 95G, 1000, and 1100 °C
`preanneals, and the specimen given the 900°C preanneal,
`indicates that the breakup of the oxide in the 950, 1000, and
`1100 °C specimens occurred during the preanneals.
`For specimens given an HF treatment, no preanneal and
`full processing, an interfacial oxide layer was present but it
`was not continuous (Fig. 4}. In some regions it was up to a
`maximum thickness of 8 A, in other regions it was thinner,
`and in some regions there were holes. Small areas (E) of the
`polysilicon had regrown through the holes, individual areas
`extending typically 25 A along the interface and 25 A into
`the polysilicon. The fraction of the interface that had been
`regrown was ~0.2.
`For specimens given an HF treatment, 2 1000 °C prean-
`neal and full processing, the breakup of the interfacial oxide
`layer was severe, the layer consisting mainly of balls of oxide
`up to 50 A diameter (Fig. 3}. Individual areas (F) ofre-
`grown polysilicon extended typically 300 A along the inter-
`face and 150 A into the polysilicon, each area often covering
`several oxide balls (G) and holes CH). The fraction of the
`length of the interface that had regrown was ~0.95. The
`
`
`
`FIG. 3. HREM micrograph ofa fully processed specimen given an RCA
`treatment and an 1100 °C preanneal. Note the balled-up oxide D.
`
`FIG. 5. HREM micrograph of a fully processed specimen given an HF
`treatment and a 1000 °C preanneal. Note the regrown polysilicon area F, the
`balled-up oxide G, and the holes in between H.
`
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`J. Appl. Phys., Vol. 61, No. 1, 1 January 1987
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`FIG. 6. HREM micrograph of a specimen given an HF treatment, but no
`preanneal, implant, or drive-in.
`
`large difference between the oxide layers in the specimen
`given the 1000°C preanneal, and the specimen given no
`preanneal, indicates that the “balling-up” of the oxide in the
`1000 °C specimen mainly occurred during the preanneal.
`In order to obtain further information concerning the
`interfacial oxide layer that was present after an HF treat-
`ment, additional specimens were examined that corre-
`sponded to an HF treatment and polysilicon deposition, but
`no further processing. A white band wasseen at the interface
`(Fig. 6) but this was extremely thin, and so the oxide thick-
`ness could not be directly measured accurately. The inter-
`face was very uniform, and in a few places adjacent to the
`interface small areas ofthe polysilicon were ofthe same crys-
`tallographic orientation as the single-crystal silicon. These
`areas could have arisen by either direct epitaxial growth
`through holesinitially present in the oxide layer or regrowth
`through holes created initially present in the oxide layer dur-
`ing the deposition of the polysilicon at 610°C. The results
`indicate that an extremely thin and mainly continuous oxide
`layer was present immediatelyafter the polysilicon deposi-
`tion. The results also indicate that for the specimens that
`were given an HF treatment, no preanneal and full process-
`ing, the significant breakup of the oxide layer that was ob-
`served occurred during the 900 °C drive-in.
`In our previous TEM studies’* of the breakup of an
`analogous interfaciai oxide layer formed by a sulfuric acid/
`hydrogen peroxide surface chemical treatment, it was shown
`that the volumeofthe oxide present after complete balling-
`up of the layer corresponded closely to the volume of the
`~ 10-A-thick uniform oxide layer that was presentinitially.
`This suggested that the breakup of the oxide layer occurred
`mainly by a local diffusion mechanism. Application of this
`principle to the present work gives the following results. For
`the specimens given an HF treatment, a 1000 °C preanneal,
`and full processing, the balled-up oxide corresponded to an
`approximately planar array of spheres of mean diameter 40
`A and mean spacing 100 A. Calculation shows thatthis is
`equivalent to an initial uniform oxide layer of thickness ~4
`A, a result which is consistent with the TEM observations
`for the specimens given an HF treatment and polysilicon
`deposition, but no further processing (Fig. 6). For the speci-
`mens given an RCA treatment, an 1100 °C preanneal, and
`full processing, a similar calculation showed that the balled-
`up oxide layer is equivalent to an initial uniform oxide layer
`
`of thickness ~ 15 A. This result is in good agreement with
`the TEM value of ~ 14 A for the specimens given an RCA
`treatment, preannealed at 900 °C, and fully processed (Fig.
`1).
`
`Present evidence indicates that there are genuine differ-
`ences in the thickness of oxide layers formed on silicon slices
`by the HF treatments of different organizations. These dif-
`ferences may depend on the HF solution, the dip procedure,
`or the elapsed timeprior to the subsequent deposition of the
`polysilicon. Gur TEM examinations of silicon specimens
`given nominally the same HF treatment, and subsequently
`processed, by different organizations have showndifferences
`in the behavior of the oxide layer which weattribute to dif-
`ferences in its initial thickness.'? Furthermore, measure-
`ments by different organizations of the thickness of oxide
`layers presentonsilicon slices after HFtreatments have Biv-
`en markedly different values, e.g., 8-9A from ellipsometry*”
`and ~3 A from Auger spectroscopy.”
`The above TEM results show that the interfacial oxide
`layers break up faster when they are heated at higher tem-
`peratures, and when theyare initially thinner. Thus, for the
`oxide layers arising from the HF treatment, which were ini-
`tially ~4 A thick, breakup had already occurred during a
`heat treatment at 900°C (drive-in), while for oxide layers
`arising from the RCA treatment, which wereinitially ~ 14
`A thick, breakup only began to occur during a treatment at
`950°C (preanneal). These present results are consistent
`with our previous TEM results’*?° which indicated that an
`initially ~ 1C-A-thick oxide layer was just beginning to
`break up at 900°C. The results are also consistent with the
`TEM results of Schaber et al.°° which showed that for an
`oxide layer ~ 30 A thick, breakup did not occur at 950°C.
`However, some caution is required when making compari-
`sons of such results obtained by different organizations be-
`cause the precise behavior depends on a numberof factors,
`e.g., it has been shown that such oxide layers break up more
`rapidly when the arsenic concentration is higher.’>'®
`Grain sizes for the polysilicon layers in fully processed
`specimens were determined from TEM cross-section micro-
`graphs taken at lower magnifications. For individual speci-
`mens, the grain size near the polysilicon layer surface was in
`general larger than in the remainderofthe polysilicon layer.
`This was because the upper portion of the polysilicon layer
`had been made amorphous by the arsenic implant. Conse-
`quently, during the drive-in at 900°C, larger grains had
`formed in this porticn of the layer by regrowth from amor-
`phous material than in the remainder of the layer by re-
`growth from fine grains. For the grains in the main portion
`of the layer, ie., away from the layer surface, the results
`showed that the mean grain size was typically 400, 600,
`1000, and 1000 A for preanneal temperatures of 900, 950,
`1600, and 1100 °C, respectively. Conversely, for the grains
`near the surface, the mean grain size was typically 1200 A for
`all ofthese preanneal temperatures, except for 1100 °C when
`it was typically 2000 A.
`
`HY. ELECTRICAL RESULTS
`
`Figures 7 and § show Gummel plots for the RCA- and
`HF-treated devices, respectively, that were given preanneals
`
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`J. Appi. Phys., Vol. 61, No. 1, 1 January 1987
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`between 800 and 1100°C. The collector characteristics for
`both the HF- and RCA-treated devices are all ideal over at
`least three orders of collector current (60 mV/decade). Sim-
`ilarly the base characteristics of the HF-treated devices are
`also ideal, although the base characteristics of the RCA-
`treated devices are slightly nonideal (70 mV/decade) corre-
`sponding to an ideality parameter of nz = 1.12. To show the
`effect of the preanneal on the electrical characteristics of the
`RCA- and HF-treated devices, /,) and /,, have been plotted
`against the preanneal temperature in Fig. 9. Because of the
`nonideality of the base current characteristics of the RCA-
`treated devices, the values of J,, were calculated from the
`ideal collector characteristics and maxirnum current gain
`Bnay USINg the relationship?! J, = Lg/Binax-
`For the RCA-treated devices, Figs. 7 and 9 show that
`the collector current is relatively unaffected by a preanneal.
`Conversely, the base current is strongly affected with the
`electrical results falling into two distinct regimes. Below
`~ S00 °C, the base current is approximately constant. In this
`regime, the 900°C drive-in is the dominant process as far as
`the interfacial oxide layer is concerned. Above ~ 900 °C, the
`base current increases rapidly with preanneal temperature.
`In this regime, the preanneal is the dominant process as far
`as the oxide layer is concerned. For example, the base cur-
`rent increases after a 950°C preanneal by ~6>, after a
`1006 °C preanneal by ~28 x, and after a 1100 °C preanneal
`by ~ 100x. This trend correlates well with the TEM results.
`Thus, after a 900°C preamneal, the oxide layer is uniform
`and continuous (Fig. 1) and the gain is not significanths
`affected by the preanneal. After 2 950°C preanneal, the Ox
`ide layer begins to break up (Fig. 2} and a large increase ing
`20:29:
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`~ B00
`
`900
`
`100
`1000
`TEMPERATURE[°C]
`
`Os
`
`¥ (Noits]
`be
`
`FiG. 7. Gummeiplots ofdevices given an RCA treatment and preanneals in
`
` 07
`the range 800-1100°C.
`
`05
`
`“06.~—«<ti(té‘«C
`Ving fVolts!
`
`FIG. 8. Gummelplots of devices given an HF treatment and preannealsin
`the range 800-1000 °C.
`
`FIG. 9. I,. and J, vs preanneal temperature for devices given RCA and HF
`treatments.
`
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`the base current occurs. As the preanneal temperature is
`further increased, the breaking up of the oxide layer contin-
`ues (Fig. 3) and this corresponds to a continuing increase in
`the base current. Over the preanneal temperature range of
`800-1100 °C, the transistor gain decreases from ~ 1800 to
`~ 40.
`For the HF-treated devices, Figs. 8 and $ showa similar
`but less pronounced trend to that of the RCA-treated de-
`vices. Thus, the collector currentis relatively unaffected by a
`preanneal. For the base current, after a preanneal below
`~ 900°C, no significant increase occurs. After a 950°C
`preannealit increases ~ 3 x, and after a 1000 °C preannealit
`increases ~ 5.5. This increase in the base current again
`correlates with a progressive increase in the breaking up of
`the interfacial oxide layer (Figs. 4 and 5), although it should
`be noted that some polysilicon grain growth also occurs (Ta-
`ble I). Over the pre-anneal temperature range of 800-
`1000 °C, the transistor gain decreases from ~ 240 to ~ SO.
`A comparison of the RCA- and HF-treated devices
`showsthe following. After a preanneal below ~ 900 °C, the
`base current for the RCA-treated devices is ~ 10> less than
`for the HF-treated devices. This difference correlates with
`the former devices having a relatively thick, continuous ox-
`ide layer, and the latter devices having a thin broken-up ox-
`ide layer. After a preanneal at 1000 °C, the base current for
`the RCA-treated devices is ~ 2 less than for the HF-treat-
`ed devices. This difference correlates with the former devices
`having a broken-up oxide layer, and the latter devices having
`a completely balled-up oxide layer.
`
`¥. INTERPRETATION OF ELECTRICAL RESULTS
`
`The larger gain that occurs for polysilicon emitter bipo-
`"lar transistors when a thin interfacial oxide layer is incorpo-
`rated in the emitter can be explained qualitatively in terms of
`tunneling through the oxide layer as follows. For x-p-n tran-
`sistors, the collector current /., is determined mainly by the
`flow of electrons through the emitter to the base and collec-
`tor. Considerable evidence has shown that the potential bar-
`rier to electrons y, associated with the oxide layer is smail,
`the tunnelling probability is high, and so the electron flow is
`little reduced. Conversely, the base current J, is determined
`mainly by the flow of holes from the base into the emitter.
`The potential barrier to holes y, associated with the oxide
`layeris high, the tunneling probability is low, and so the hole
`flow is significantly reduced. The current gain is the ratio
`f,/f, and so the gain is increased.
`We shall now try to interpret our device results more
`quantitatively. Yu ef al.’' in their theoretical analysis of
`polysilicon emitter bipolar transistors which incorporated a
`thin uniform oxide layer within the emitter, obtained the
`following equation for the base current density J,:
`(1)
`J, = [qS.gni,./Na (w) lexp(q,./kT),
`where V,, is the base/emitter applied voltage, 1, (w) is the
`emitter carrier concentration at the base/emitter depletion
`region edge, n,, is the intrinsic carrier concentration of the
`emitter taking into account band-gap narrowingeffects, and
`Seg is an effective recombination velocity which incorpo-
`rates the various recombination processes occurring for the
`
`holes injected from the base into the emitter. It can be seen
`that J, depends directly on S.,, and also on the emitter do-
`pant profile through the parameters n,, and NV, (w). Earlier
`work? showed that an interfacial oxide layer can retard the
`emitter dopant diffusion, and hence change thefinal dopant
`profile. However, for the oxide layer thicknesses considered
`here, this effect is very small. We shall therefore assumethat
`n, and V,(w) are constant, and so variations in J, can be
`predicted from changes in the value of Sy.
`A simplification of the analysis occurs if carrier recom-
`bination in the single-crystal part of the emitter located be-
`low the interfacial oxide layeris ignored. In the present work
`this assumption is justified, partly because the emitter/base
`junction is only ~ 100 A below the oxide layer,' and partly
`because we shall only be considering the changein J,, rather
`than its absolute value. The equation for S$. then reduces
`toc! t
`
`(2)
`Seq = S; + {C/T,) + (1/08; +. 5,334
`where S, is the recombination velocity for holes at the oxide
`layer/single-crystal silicon interface, T;
`is an effective re-
`combination velocity corresponding to the tunnelling of
`holes through the oxide layer, and S, is an effective recom-
`bination velocity for holes in the polysilicon.
`The parameter 7, depends on the oxide layer thickness
`A and is given by”?
`T, = (AT/2ampy (eA — ey kT),
`
`(3)
`
`where
`
`b, = (47A/h) (2m¥y,)'?,
`c, = (2r&/h) (2m¥/y,)'”,
`
`and y,, is the potential barrier for holes and mF is the effec-
`tive mass for holes.
`To gain a clear insight into the relative importanceof the
`three components of S,,, curves showing the relationship
`between S,, and A were calculated using Eqs. (2) and (3)
`(Fig. 10). A value for S, of 1.5 10° cm s~’ was used,this
`being calculated by the method of Yu et al.'' for a grain size
`of 1000 A using the datalisted in Table II. This value may be
`compared with the range of values of ~8 x 10* to 2x 10°
`cms‘ obtained by Yu et ai." for similar polysilicon layers
`with various thicknesses and grain sizes. A value for S, of
`1.510? cm s~! was assumed, again following Yu et al.' In
`order to calculate T,, a value of y, is required. Measure-
`ments ofy,, by Ng and Card’’ for oxide layers in the thick-
`ness range ~ 20 to ~26 A gave values of ~ 1.0 eV, i.e., con-
`siderably less than for thick oxide layers where y, ~3.0 eV.
`In the absence of any experimental vaiues of y, for oxide
`layers ofthickness < 20 A, three values have been chosen for
`our calculations, namely, y, = 0.5, 1.0, and 1.5 eV. It was
`also assumed that m? = mio, the free electron mass.
`From Fig. 10 it can be seen that there are three distinct
`regions of device operation for a polysilicon emitter transis-
`tor. For large A, Sig 5S; and is determined mainly by re-
`combination at the oxide layer/single-crystal silicon inter-
`face. Other mechanisms such as recombination in the
`single-crystal part of the emitter and recombination in the
`base may also contribute to the base current in this region of
`
`230
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`J. Appl. Phys., Vol. 61, No. 4, 4 January 1987
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`230
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`20:49:b1pzozAineZO
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` 02 July 2024 11:57:07
`
`would correspond to a uniform oxide layer of thickness ~ 4
`to ~8 A,the range arising because of the uncertainty in the
`value ofy,,. This prediction is in reasonable agreement with
`the observation of a uniform oxide layer of thickness -~4 A
`immediately after polysilicon deposition, and a broken up
`oxide layer ofmaximum thickness ~ 8 A after no preanneal,
`but a 900 °C drive-in.
`Let us now consider the effect of the interfacial oxide
`layer on the devices by comparing the ~ 100 x difference in
`base current between the RCA-treated devices given no
`preanneal with those given a 1100°C preanneal. For no
`preanneal, the oxide layer is continuous and uniform, and
`Suge eS; ~ 1.5 10° cm s7!. Fora 1100 °C preanneal, the ox-
`ide layer is balled-up. If it is assumed that such a bailed-up
`oxide fayer has little effect on the flow of holes through the
`interface, then S., will correspond to the value for A = 0,
`ie. to Sag =S, «1.5% 10° om s7! (Fig. 10). Hence, an in-
`crease in base current of ~ 100 x is predicted, in good agree-
`ment with the experimental value of ~ 100 CFig. 9).
`With regard to the effect of the interfacial oxide layer on
`the RCA-treated devices as the preanneal temperature is
`progressively increased, comparison cf the device results
`and TEM observations suggest the following behaviors. On
`going from no preanneal to ~ 800°C, /, is constant and is
`determined mainly by recombination of holes at the oxide-
`layer/single-crystalsilicon interface (mechanism A). From
`~ 800 to ~925 °C, £,, increases slowly and is determined by
`mechanism A, together with tunnelling of holes through the
`thinner portions of the oxide layer (mechanism B). From
`~ 925 ta ~975 °C, I, increases rapidly and is determined by
`mechanism B, together with an increasing contribution from
`the fiow of holes througi the penetrated regions of the oxide
`layer and the transport properties in the polysilicon layer
`(mechanism C). From ~975 to ~ 1100 °C, J, continues to
`increase and then approaches a constant value, and is deter-
`mined mainly by mechanism C, the constant value arising
`when the oxide layer is completely balled up.
`An additional factor that could contribute to the in-
`crease in the base current as the preanneal temperature in-
`creases is the progressive coarsening ofthe polysilicon grains
`that occurs. The grain size for the part of the layer adjacent
`to the interfacial oxide layer increases from ~ 400 to ~ 1000
`A on going from no preannealto both 1000 to 1100 °C prean-
`neals (Table I}. Such coarsening could change S,, and this
`would change S.¢ if A were small. The caiculations of Yu et
`ai." indicate a maximum change in 5, due to this effect of
`~2or ~3X. However, such a change in S, would have no
`effect on the ~ [00x difference in J, calculated above for
`the RCA-treated devices on going from no preanneal to a
`1100 °C preanneal. This is because for no preanneal, the vai-
`ue ofS,, =S, used is appropriate for a grain size of ~ 400 A
`(8, corresponds tc mechanism A and is independentofgrain
`size), and for a L100 °C preanneal, the value ofSg &5, used
`is appropriate for a grain size of ~ 1000 A (S,, was calculated
`from the data of Table II}. However, the coarsening of the
`grains could slightly affect the shape ofthe curve of Fig. 9 for
`the RCA-treated devices on going from no preanneal to a
`1100 °C preanneal because mechanisms B and C both de-
`pend on the transport properties in the polysilicon layer.
`
`1
`
`21
`
`23
`
`24
`
`25,26
`
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`
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`
`FIG. 10. Theoretical plots of effective recombination velocity (Sq, ) vg in-
`terfacial oxide layer thickness (A) for hole potential barriers (y, ) associat-
`ed with the oxide of (a) 1.5, (b) 1.0, and (c) 0.5 eV.
`
`operation.”* For small A, most holes tunnel through the ox-
`ide layer, S.q ~S, and is determined mainly by transport
`and recombination in the polysilicon. For intermediate A,
`tunneling through the oxide layer is the dominant mecha-
`nism, and S,, is extremely sensitive to srnall changes in A.
`Let us initially consider the effect of the interfacial oxide
`layer on the device operation by comparing the ~ 10x dif-
`ference in base current between the RCA- and HF-treated
`devices given no preanneal, as shown in Fig. 9, with that
`predicted by Fig. 10. For the RCA-treated devices, the oxide
`layer is uniform and of thickness ~ 14 A. Consequently,
`Fig. 10 predicts that S.g =S; = 1.510? cms’, and this
`value does not depend significantly on the precise value of
`¥,. For the HF-treated devices, S.¢ should then be