CE
`
`Operating Principles,
`Technology and
`System Applications
`
`MARTIN A.GREEN
`
`National Library of Australia
`Cataloguing-in-Publication entry
`
`Green, Martin A.
`Solar cells.
`
`Bibliography.
`Includes index.
`ISBN 0 85823 580 3
`
`1. Solar cells. 2. Photovoltaic power generation.
`I. University of New South Wales.
`II. Title.
`
`621.31'244
`
`First published by Prentice-Hall, Inc., Englewood Cliffs, N.J. 07632, 1982.
`ISBN 0-13-82270. Reprinted with permission.
`
`All rights reserved. No part of this book may be reproduced in any form or by any
`means without permission from the author.
`
`~ Prepared by the Publications Section
`-< - Department of the Registrar
`
`Published by The University of New South Wales
`P.O. Box 1
`Kensington, NSW 2033
`
`December 1986
`
`Printed by Bridge Printery Pty Ltd, 29-35 Dunning Avenue, Rosebery, NSW 2018
`
`I 1
`
`HANWHA 1049
`
`

`

`CONTENTS
`
`PREFACE
`
`Chapter 1.
`
`SOLAR CELLS AND SUNLIGHT
`
`1.1
`Introduction
`1.2
`Outline of Solar Cell Development
`1.3
`Physical Source of Sunlight
`2
`1.4
`The Solar Constant
`4
`1.5
`Solar Intensity at the Earth's Surface
`1.6 Direct and Diffuse Radiation
`6
`1.7
`Apparent Motion of the Sun
`8
`1.8
`Solar lnsolation Data
`8
`1.9
`Summary
`9
`
`2
`
`5
`
`Chapter 2.
`
`REVIEW OF SEMICONDUCTOR PROPERTIES
`
`2.1
`2.2
`2.3
`
`Introduction
`13
`Crystal Structure and Orientations
`Forbidden Energy Gaps
`17
`
`14
`
`xiii
`
`1
`
`13
`
`V
`
`

`

`vi
`
`Contents
`
`2.4
`
`2.5
`2.6
`2.7
`2.8
`2.9
`
`2.10
`2.11
`2.12
`
`2.13
`2.14
`
`2.15
`
`Probability of Occupation of Allowed
`States
`18
`20
`Electrons and Holes
`Dynamics of Electrons and Holes
`Energy Density of Allowed States
`Densities of Electrons and Holes
`Bond Model of a Group IV
`Semiconductor
`26
`Group 111 and V Dopant,
`Carrier Densities
`30
`Location of Fermi Level in Doped
`Semiconductors
`32
`Effect of Other Types of Impurities
`Carrier Transport
`34
`2.14.1 Drift, 34
`2. 14.2 Diffusion. 36
`Summary
`37
`
`28
`
`21
`23
`24
`
`33
`
`Chapter 4.
`
`p-n JUNCTION DIODES
`
`Contents
`
`4.1
`4.2
`4.3
`4.4
`4.5
`
`4.6
`
`4.7
`4.8
`4.9
`
`4.10
`
`63
`
`62
`Introduction
`Electrostatics of p-n Junctions
`Junction Capacitance
`67
`68
`Carrier Injection
`Diffusive Flow in Quasi-Neutral
`Regions
`70
`72
`Dark Characteristics
`4.6. 1 Minority Carriers in
`Quasi-Neutral Regions, 72
`4.6.2 Minority-Carrier Currents, 74
`Illuminated Characteristics
`76
`Solar Cell Output Parameters
`79
`Effect of Finite Cell Dimensions
`on 10
`81
`Summary
`
`82
`
`Chapter 3. GENERATION, RECOMBINATION, AND
`THE BASIC EQUATIONS OF DEVICE PHYSICS
`
`40
`
`Chapter 5.
`
`EFFICIENCY LIMITS, LOSSES,
`AND MEASUREMENT
`
`vii
`
`62
`
`85
`
`3.1
`3.2
`
`3.3
`
`3.4
`
`3.5
`
`3.6
`
`43
`
`3.3.2
`
`40
`Introduction
`Interaction of Light with
`Semiconductor
`40
`Absorption of Light
`3.3. 1 Direct-Band-Gap
`Semiconductor, 43
`Indirect-Band-Gap
`Semiconductor, 45
`3.3.3 Other Absorption Processes, 47
`Recombination Processes
`50
`3.4. 1 Relaxation to Equilibrium, 50
`3.4.2 Radiative Recombination, 50
`3.4.3 Auger Recombination, 52
`3.4.4 Recombination through Traps, 53
`3.4.5 Recombination at Surfaces, 55
`Basic Equations of Semiconductor-Device
`Physics
`56
`3.5.1
`Introduction, 56
`3.5.2 Poisson's Equation, 56
`3.5.3 Current Density Equations, 57
`3.5.4 Continuity Equations, 57
`3.5.5 Equation Set, 58
`Summary
`59
`
`5.1
`5.2
`
`5.3
`5.4
`
`5.5
`5.6
`
`Chapter 6.
`
`STANDARD SILICON SOLAR CELL
`TECHNOLOGY
`
`103
`
`6.1
`6.2
`
`103
`Introduction
`Sand to Metallurgical-Grade Silicon
`
`105
`
`85
`
`85
`
`92
`
`Introduction
`Efficiency Limits
`5.2. 1 General, 85
`5.2.2 Short-Circuit Current, 86
`5.2.3 Open-Circuit Voltage and
`Efficiency, 86
`5.2.4 Efficiency Limit1i for
`Black-Body Cells, 90
`Effect of Temperature
`91
`Efficiency Losses
`5.4. 1 General, 92
`5.4.2 Short-Circuit Current
`Losses,92
`5.4.3 Open-Circuit Voltage
`Losses, 93
`5.4.4 Fill Factor Losses, 96
`Efficiency Measurement
`Summary
`101
`
`98
`
`

`

`viii
`
`Contents
`
`Contents
`
`ix
`
`6.4
`
`6.5
`6.6
`
`108
`111
`
`6.3 Metallurgical-Grade Silicon to
`106
`Semiconductor-Grade Silicon
`Semiconductor-Grade Polysilicon to
`Single-Crystal Wafers
`107
`Single-Crystal Wafers to Solar Cells
`Solar Cells to Solar Cell Modules
`6_6, 1 Module Construction, 111
`6.6.2 Cell Operating
`Temperature, 113
`6.6.3 Module Durability, 114
`6.6.4 Module Circuit Design, 115
`Energy Accounting
`117
`Summary
`119
`
`6.7
`6.8
`
`Chapter 7.
`
`IMPROVED SILICON CELL TECHNOLOGY
`
`121
`
`7.1
`7.2
`7.3
`
`7.4
`
`7.5
`7.6
`
`121
`
`121
`Introduction
`Solar-Grade Silicon
`SiliconSheet
`123
`7.3.1 Sheet Requirement,;, 123
`7.3.2
`Ingot Technologies, 123
`7.3.3 Ribbon Silicon, 124
`Cell Fabrication and
`127
`Interconnection
`Analysis of Candidate Factories
`Summary
`135
`
`Chapter 8.
`
`DESIGN OF SI LICON SOLAR CELLS
`
`138
`
`8.1
`8.2
`
`8.3
`8.4
`8.5
`
`8.6
`
`138
`Introduction
`138
`Major Considerations
`8.2. 1 Collection Probability of
`Generated Carriers, 138
`8.2.2 Junction Depth, 143
`8.2.3 Lateral Resistance of
`Top Layer, 745
`Doping of the Substrate
`Back Surface Fields
`Top-Layer Limitations
`8.5.1 Dead Layers, 150
`8.5.2 High-Doping Effect,;, 151
`8.5.3 Contribution to Saturation
`Current Density, 153
`Top-Contact Design
`153
`
`147
`149
`150
`
`131
`
`Chapter 10.
`
`OTHER SEMICONDUCTOR MATERIALS
`
`187
`
`161
`8.7 Optical Design
`8.7.1 Antireflection Coating, 161
`8.7.2 Textured Surfaces, 164
`Spectral Response
`165
`Summary
`167
`
`8.8
`8.9
`
`Chapter 9. OTHER DEVICE STRUCTURES
`
`170
`
`172
`
`177
`
`170
`Introduction
`9.1
`170
`Homojunctions
`9.2
`Semiconductor Heterojunctions
`9.3
`9.4 Metal-Semiconductor
`Heterojunctions
`175
`Practical Low-Resistance Contacts
`9.5
`178
`9.6 MIS Solar Cells
`9.7
`Photoelectrochemical Cells
`9.7. 1 Semiconductor-Liquid
`Heterojunctions, 181
`9.7.2 Electrochemical Photovoltaic
`Cells, 181
`9.7.3 Photoelectrolysis Cell, 183
`Summary
`183
`
`181
`
`9.8
`
`192
`
`187
`Introduction
`10.1
`187
`10.2 Polycrystalline Silicon
`190
`10.3 Amorphous Silicon
`10.4 Gallium Arsenide Solar Cells
`70.4.1 Properties of GaAs, 192
`10.4.2 GaAs Homojunctions, 193
`10.4.3 Ga,-xAlxAs/GaAs Heteroface
`Cells, 194
`10.4.4 AIAs/GaAs Heterojunctions,
`196
`196
`10.5 Cu 2S/CdS Solar Cells
`10.5.1 Cell Structure, 196
`10.5.2 Operating Characteristics,
`197
`10.5.3 Advantages and
`Disadvantages of Cu,S/CdS
`Cells, 199
`10.6 Summary
`200
`
`

`

`Contents
`
`Chapter 14. RESIDENTIAL AND CENTRALIZED
`PHOTOVOLTAIC POWER SYSTEMS
`
`14.1
`249
`Introduction
`14.2 Residential Systems
`250
`14.2.1 Storage Options, 250
`14.2.2 Module Mounting, 252
`14.2.3 Thermal Generation, 252
`14.2.4 System Configurations, 254
`14.2.5 Demonstration Program, 254
`14.3 Central Power Plants
`256
`14.3.1 General Considerations, 256
`14.3.2 Operating Mode, 258
`14.3.3 Satellite Solar Power
`Stations, 262
`14.4 Summary
`263
`
`Appendix A PHYSICAL CONSTANTS
`
`Appendix B SELECTED PROPERTIES OF SILICON
`
`Appendix C LIST OF SYMBOLS
`
`BIBLIOGRAPHY
`
`INDEX
`
`xi
`
`249
`
`265
`
`266
`
`267
`
`269
`
`270
`
`X
`
`Contents
`
`Chapter 11. CONCENTRATING SYSTEMS
`
`204
`
`204
`11.1
`Introduction
`205
`11.2
`Ideal Concentrators
`11.3 Stationary and Periodically Adjusted
`Concentrators
`206
`11.4 Tracking Concentrators
`11.5 Concentrator Cell Design
`11.6 Ultra-High-Efficiency Systems
`11.6.1 General,213
`11.6.2 Multigap-Ce/1 Concepts, 213
`11.6.3 Thermaphotovoltaic
`Conversion, 217
`219
`11.7 Summary
`
`208
`209
`
`213
`
`Chapter 12. PHOTOVOLTAIC SYSTEMS: COMPONENTS
`AND APPLICATIONS
`
`222
`
`222
`12.1
`Introduction
`223
`12.2 Energy Storage
`12.2.1 Electrochemical
`Batteries, 223
`12.2.2 Large-Capacity Approaches,
`225
`12.3 Power Conditioning Equipment
`227
`12.4 Photovoltaic Applications
`228
`12.5 Summary
`
`226
`
`Chapter 13. DESIGN OF STAND-ALONE SYSTEMS
`
`230
`
`230
`
`Introduction
`230
`13.1
`13.2 Solar Module Performance
`232
`13.3 Battery Performance
`13.3.1 Performance Requirements,
`232
`13.3.2 Lead-Acid Batteries, 232
`13.3.3 Nickel-Cadmium Batteries,
`235
`13.4 Power Control
`13.5 System Sizing
`13.6 Water Pumping
`247
`13.7 Summary
`
`235
`237
`246
`
`

`

`120
`
`Standard Silicon Solar Cell Technology
`
`Chap. 6
`
`IEEE Photovoltaics Specialists Conference, Baton Rouge, 1976, pp.
`347-352.
`[6.2] C. L. YAWS et al., "Polysilicon Production: Cost Analysis of Conven(cid:173)
`tional Process," Solid-State Technology, January 1979, pp. 63-67.
`[6.3] H. Yoo et al., "Analysis of ID Saw Slicing of Silicon for Low Cost Solar
`Cells," Conference Record, 13th IEEE Photovoltaics Specialists Confer(cid:173)
`ence, Washington, D.C., 1978, pp. 147-151.
`[6.4] N. F. SHEPARD AND L. E. SANCHEZ, "Development of Shingle-Type
`Solar Cell Module," Conference Record, 13th IEEE Photovoltaic Spe(cid:173)
`cialists Conference, Washington,D.C., 1978, pp. 160-164.
`(6.5) W. CARROL, E. CuomHY, AND M. SALAMA, "Materia1 and Design Con(cid:173)
`Sideration of Encapsulants for Photovoltaic Arrays in Terrestrial Appli(cid:173)
`cations," Conference Record, 12th Photoooltaic Specialists Conference,
`Baton Rouge, 1976, pp. 332-339.
`J. W. STULTZ AND L. C. WEN, Thennal Performance, Testing and Anal(cid:173)
`ysis of Photovoltaic Modules in Natural Sunlight, JPL Report No.
`5101-31, July 1977.
`(6.7] E. ANAGNOSTOU AND A F. FORESTIERI, "Endurance Testing of First
`Generation (Block 1) Commercial Solar Cel1 Modules," Conference
`Record, 13th IEEE Photovoltaic Specialists Conference, Washington,
`D.C., 1978, pp. 843-846.
`[6.8] M. MACK, "Solar Power for Telecommunications," Telecommunications
`Journal of Australia 29, No. 1 (1979), 20-44.
`[6.9] C. GONZALEZ AND R. WEAVER, "arcuit Design Considerations for
`Photovoltaic Modules and Systems," Conference Record, 14th IEEE
`Photovoltaics Specialists Conference, San Diego, 1980, pp. 528--535.
`
`[6.6]
`
`Chapter 7
`
`IMPROVED SILICON
`CELL TECHNOLOGY
`
`7.1
`
`INTRODUCTION
`
`In Chapter 6, the standard technology used in the past to produce sil(cid:173)
`icon solar cells was described. In converting quartzite, the source ma(cid:173)
`terial, to encapsulated cells, several steps were seen to be costly and
`energy-intensive.
`Activity worldwide is being directed at reducing these costs.
`The present chapter describes some of the most promising new silicon
`technology for each of the processing steps outlined in Chapter 6.
`Most of this technology is at an advanced stage of development. Some
`aspects are being evaluated at the pilot production stage, whereas
`others have already been incorporated into commercial products.
`
`7.2 SOLAR-GRADE SILICON
`
`It was seen in Chapter 6 • that solar cells presently use the ultrapure
`silicon produced for the semiconductor industry. However, in tran-
`
`121
`
`

`

`122
`
`Improved Silicon Cell Technology
`
`Chap. 7
`
`sistors and integrated circuits, the emphasis is on silicon quality, and
`material costs are relatively unimportant. For solar cells, it is worth(cid:173)
`while considering a trade-off between performance and cost.
`As mentioned in Section 3.4.4, impurities in solar cells gener(cid:173)
`ally introduce allowed levels into the forbidden gap and thereby act
`as recombination centers. It was seen in Section 5.4.2 that an increased
`density of such centers will decrease the cell ~fficiency. Fi~~e 7.1
`shows the experimental results for a range of different metalhc nnpu(cid:173)
`rities when each is the only impurity present apart from the dopant
`(Ref.' 7.1). Although some metallic impurities (Ta, Mo, Nb, Zr, W, Ti,
`and V) can reduce cell performance when present in extremely small
`concentrations others can be present in concentrations in excess of
`1015/cm3 befo;e becoming a problem. This is about 100 times higher
`than impurity levels in semiconductor-grade silicon (SeG-Si). It makes
`it likely that an alternative, less expensive process might produce a
`Jess pure solar-grade silicon (SoG-Si) which still gives cells ofadequate
`performance. Several alternative processes appear capable of prod~c(cid:173)
`ing silicon of quality not appreciably lowerthanSe-G but at a fraction
`of the cost of conventional technology.
`One of the more promising is that developed by the Union
`Carbide Corporation. It involves the preparation of silane (SiH•) from
`
`,o-5
`
`,o-4
`
`Metal impurity concentration (ppma)
`10 3
`
`,0-2
`
`10-1
`
`1.0
`
`10
`
`p
`
`1.0
`
`~ 0.8
`0-
`;.
`
`j
`u • :2 ;;;
`al .. ;;;
`E
`0 z
`
`Ti V
`
`Mn
`
`P-type silicon
`
`0.2
`
`0
`1011
`
`,012
`
`,o,s
`1014
`,01J
`Metal impurity concentration (atoms/cm3 J
`
`,016
`
`,on
`
`10,s
`
`Figure 7 .1. Effect of different secondary impurities on the
`performance of silicon solar cells (After Ref. 7.1, ©1978
`IEEE.)
`
`Seel. 7.3
`
`Silicon Sheet
`
`123
`
`metallurgical-grade silicon and the subsequent deposition of silicon
`from silane (Ref. 7.2). Analysis of this process indicates that it is ca(cid:173)
`pable of producing silicon at one-fifth the cost of the present com(cid:173)
`mercial process using only one-sixth of the processing energy. An al(cid:173)
`ternative process at an advanced stage of development is that developed
`by Batelle Columbus Laboratories. It is based on the zinc reduction
`of silicon tetrachloride (Ref. 7.3). It is probable that improved pro(cid:173)
`cesses such as these will replace the conventional Siemens process for
`producing silicon not only for the solar cell industry but also for the
`semiconductor electronics industry in general.
`
`7.3 SILICON SHEET
`
`7.3.1 Sheet Requirements
`
`Having produced purified silicon, it is then necessary to con(cid:173)
`vert it into the form of thin sheets of good crystallographic quality
`for use as solar cells. To obtain the full photovoltaic output from the
`material, it only has to be 100 µm or so thick. In the past, the ap(cid:173)
`proach used has been to form a large single-crystal ingot using the
`Czochralski (CZ) process and then slice thin wafers from this ingot.
`This approach is very inefficient in converting bulk silicon into large
`areas of solar cells. Not only is over half the silicon lost in sawing it
`into wafers, but cutting limitations result in thicker wafers than es(cid:173)
`sential. Also, the wafers are circular, which means that they cannot
`be packed very densely when encapsulated into solar modules unless
`trimmed to a square or hexagonal shape.
`
`7.3.2
`
`Ingot Technologies
`
`The Czochralski approach is an example of an ingot technol(cid:173)
`ogy. The fundamental limitation of such a technology is that the in(cid:173)
`gots produced have to be sliced up into wafers with the disadvantages
`already mentioned.
`The standard Czochralski process can be modified to operate
`on a semicontinuous basis with resultant cost savings (Ref. 7.4). The
`fact that the process produces cylindrical ingots 1 is also a disadvantage
`in solar cell applications.
`A simpler approach to producing ingots, particularly those of
`square cross section, is to use a process similar to casting. This will
`
`1 With modifications, ingots with an approximately square cross section can be
`prepared by the Czochralski process (Ref. 7.5).
`
`

`

`124
`
`Improved Silicon Cell Technology
`
`Chap. 7
`
`generally result in a polycrystalline ingot which is not ideal for solar
`cell applications. However, with careful control over the conditions
`under which molten silicon solidifies, silicon of large grain size can be
`formed. With a suitable "mold" material, such large-grained material
`can produce solar cells of good performance (Ref. 7.6).
`With a suitable seed and a method of controlling the rate of
`solidification as in the heat-exchanger method (Ref. 7. 7), it is possible
`to produce essentially single-crystal ingots of quite massive propor(cid:173)
`tions with a "casting" approach. The performance of cells fabricated
`from such material has been comparable to that of cells made of good(cid:173)
`quality Czochralski material. Studies indicate that this approach
`has a marked economic advantage over even the advanced Czochralski
`techniques (Ref. 7. 8).
`
`7.3.3 Ribbon Silicon
`
`The limitations of the ingot approach can be avoided if the
`silicon can be formed directly into sheets or ribbons. Several tech(cid:173)
`niques have been developed for achieving this.
`The first to be developed to the stage of producing commercial
`cells is the edge-defined film-fed growth (EFG) method, as illustrated
`in Fig. 7.2. This technique bears some relationship to the Czochralski
`process except that the shape of the crystal pulled is defined by a
`graphite "die." As a consequence, it is possible to obtain crystals in
`the form of thin ribbons directly from the melt (Ref. 7.9). Very high
`production rates of silicon can be obtained by pulling several ribbons
`simultaneously from the same melt (Ref. 7.10).
`The major problem with this technique relates to the quality
`of the material produced. The process produces material of relatively
`poor crystallographic quality compared to the Czochralski process.
`Owing to the nature of the growth process, impurities introduced in(cid:173)
`to the molten silicon from the die, crucible, and surrounding regions
`of the growth furnace are incorporated into the growing ribbon. (In
`other crystal growth processes, most of these are preferentially rejected
`from the growing crystal to the molten silicon.) In addition, the mol(cid:173)
`ten silicon tends to react with the graphite die. This can result in sil(cid:173)
`icon carbide precipitates in the ribbon which can disrupt its growth
`and degrade the properties of subsequently fabricated cells.
`The dendritic web method illustrated in Fig. 7 .3 overcomes
`some of these disadvantages. By controlling temperature gradients, it
`is possible to encourage the growth of parallel dendrites into the mol(cid:173)
`ten material. As these are pulled out of the melt, a film of molten
`silicon is trapped between them (Ref. 7 .11 ). This subsequently solid-
`
`II
`
`,,,Silicon ribbon
`
`Graphite die
`
`Figurt 7 .2. Essential features of the edge-defined mm-f: d
`growt method for producing ribbon crystals
`f
`iii e
`The molten silicon moves up the interior of the o s. co~.
`by capillary action. The ribbon shape is defined fyas:utehad,e
`of the top of the die.
`es pe
`
`D
`
`Supporting dendrite
`
`Molten silicon
`
`troll d. b ~ e :i requ~re • :rhe shape of the ribbon is con-
`
`F_'igure 7 .3. Dendritic web approach to produc,·n
`'li
`nbbon N di •
`g s1 con
`· d
`. e
`erm gradients m the molten si1icon. The den(cid:173)
`y
`drites down the edge of the ribbon solidify first AB th
`are drawn out of the melt a th·
`1
`. .. ese
`•
`molten silicon is trapped betw~n th m ayer of m1tlally
`em.
`
`125
`
`

`

`silicon
`
`Meniscus
`
`Crucible wall,,,
`
`Figure 7 .5. Horizontal or low-angle growth method for
`producing silicon ribbon. Ribbons can be produced at very
`high rates, but dimensional control has been a problem in
`the past.
`
`Several other ribbon growth processes are at a less advanced
`stage of development. One distinguished by very high rates of ribbon
`production is the horizontal or low-angle growth method of Fig. 7.5.
`The major developmental problems with this technique have related
`to control of the ribbon dimensions (Ref. 7.12). Casting of silicon
`directly into sheet or ribbon form has also been explored (Refs. 7 .6
`and 7.13).
`
`7.4 CELL FABRICATION AND INTERCONNECTION
`
`The disadvantage of the standard technique for fabricating cells on
`silicon wafers as described in Chapter 6 is that it is a "batch"-orien(cid:173)
`tated technique. As such, it is capable of only relatively low through(cid:173)
`put and also is extravagant in the use of materials, particularly metal
`for forming the cell contacts. Several approaches are now being used
`in commercial devices which overcome these limitations and, as a
`bonus, result in cells of higher performance.
`One major development has been the use of silicon wafers with
`textured surfaces. Using selective etching, it is possible to form small
`pyramids on the surface of silicon wafers (Ref. 7.14). The appearance
`of these pyramids greatly magnified under the scanning electron mi(cid:173)
`croscope is shown in Fig. 7 .6. Light reflected from the side of one of
`these pyramids is reflected downward, getting a second chance of
`being coupled into the cell. With the use of an antireflection coating,
`reflection losses can be reduced to less than a few percent. As shown
`
`127
`
`126
`
`Improved Silicon Cell Technology
`
`Chap. 7
`
`if•
`• e a thin ribbon of silicon bounded by the thicker dendrites.
`t
`,es o giv
`.
`.
`th "bb
`These can be removed and recycled after cell fabncat10n on en on
`section. No die is required and material properties are near!~ as good
`these obtained from the Czochralski process. The relatively l~w
`:eduction rate of silicon crystal material by this process has been its
`major disadvantage.
`Relatively small samples of silicon ribbon p~od~ced by both
`th EFG and dendritic web processes are compared m Fig. 7.4. Note
`th: corrugated surface finish typical of material prod~ced by the E~G
`process and the mirror finish characteristic of dendritic web matenal.
`
`- e
`
`---- -
`
`- , ,_~ ~ - : :
`------· --~..
`
`--~-
`
`-
`
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`
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`---
`
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`,_!"f•-•
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`. _,.;._
`
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`li'ia:l:::
`
`FM
`
`7 C
`
`trtt?t?' Wt ttntiVttrBFlM
`
`Figure 7 .4. Comparison of the physical appearance of
`EFG and dendritic web silicon ribbon crystals. The ~en(cid:173)
`drites are removed from the latter after cell pro_cessmg.
`(Ribbon courtesy of Japan Sol~ Energy Corporat10n and
`Westinghouse Research Laboratones.)
`
`

`

`I'
`
`!,
`! •
`
`'
`
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`
`,1.
`
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`
`Implant
`phosphorus
`
`Electron
`pul,e
`
`Entrance
`lock
`
`Evaporate
`anti reflective
`coating
`
`Exit lock
`
`Electron
`pul,e
`
`r:J
`
`Evaporate
`aluminum(cid:173)
`back contact
`
`Electron
`pulse
`
`Evaporate
`aluminum(cid:173)
`front contact
`
`Figure 7. 7. Schematic diagram of a continuous vacuum
`process for producing solar cells based on ion-implanted
`junctions, evaporated meta] contacts, and pulsed electron
`beam annealing. (After Ref. 7.16, © 1976 IEEE.)
`
`inappropriately called a back surface field (BSF) is one technique for
`achieving low effective recombination velocities at the rear of the cell.
`As indicated in Fig. 7 .8, a heavily doped region is included right at the
`back contact to the cell. From theoretical considerations, the interface
`between this region and the more lightly doped bulk regions can be
`shown to act as a low-recombination-velocity surface. Not only does
`this technique improve voltage and current output as mentioned but
`it also makes it easier to make a low-resistance contact to the silicon
`at the rear of the cell. In practice, the most effective technique for
`producing this "back surface field" has been to screen print an alu-
`
`N'
`
`p
`
`Figure 7 +8. Sketch of the N+pp+ solar cell. The heavily
`doped P region at the rear of the cell blocks minority car(cid:173)
`rier flows, making the pp+ junction plane an effective Iow(cid:173)
`recombination-velocity surface.
`
`129
`
`Figure 7 .6. Appearance of a textured silicon surface under
`a scanning electron microscope. The peaks are ty~ically 10
`µm high and are the tops of square-based pyramids. The
`sides of these pyramids are intersecting (111) planes within
`the crystal structure of the silicon.
`
`in Chapter 8, this technique can give acceptable performance even
`without antireflection coatings.
`In the previous standard process, the p-n junction was formed
`by diffusing impurities on a batch basis. A more cost-effective ap(cid:173)
`proach is to spray layers containing the required dopant onto the wa(cid:173)
`fer surface and to diffuse the impurity in using a continuous-belt
`process (Ref. 7.15). An alternative approach is to use a technique
`known as ion implantation (Ref. 7 .16). Ions of the dopant are accel(cid:173)
`erated to high velocities and directed at the wafer surface. These are
`embedded in the silicon wafer near the surface they impact. A sub(cid:173)
`sequent annealing step removes the damage inflicted on the silicon
`lattice by this process and also "activates" the dopants in an electronic
`sense. Pulsing by an electron beam or laser is an energy-efficient an(cid:173)
`nealing approach. A very tidy process for the high-volume produc(cid:173)
`tion of solar cells based on ion implantation is indicated in Fig. 7.7.
`Further improvement in solar cell performance has been ob(cid:173)
`tained by paying attention to obtaining a low-surface-recombination(cid:173)
`velocity contact to the rear of the cell. As indicated in Chapter 5,
`this improves the open-circuit voltage of the cell and it also mar(cid:173)
`ginally increases the current output. The use of what is somewhat
`
`128
`
`

`

`Sect. 7.5
`
`Analysis of Candidate Factories
`
`131
`
`minum-based paste onto the rear of the cell and alloy the aluminum
`into the silicon in a subsequent firing step (Ref. 7.15).
`Metallization was one of the weak links in the standard solar
`cell processing sequence of Chapter 6. Two lower-cost processes used
`in commercial cells are screen printing and electroplating. Both of
`these prevent wastage of metal and eliminate the requirement for ex(cid:173)
`pensive vacuum equipment.
`In the former, a paste containing the
`metal is printed onto the silicon wafer through a mask and subse(cid:173)
`quently fired to remove "binders" in the paste and to lower the metal
`resistivity. Silver pastes were the first to be used commercially al(cid:173)
`though nickel, aluminum, and copper pastes may be lower-cost alterna(cid:173)
`tives. In the plating approach, a pattern is etched through an insulating
`layer on the cell surface and the desired metal layer is plated through
`this. More than one type of metal layer generally is plated sequen(cid:173)
`tially, since few metals by themselves possess the properties of good
`adherence to silicon, corrosion resistance, low resistivity, and low
`cost. A final step in this approach may be "solder dipping" to cover
`the plated metal by a layer of solder for corrosion protection and
`lower series resistance. Figure 7 .9 compares the physical appearance of
`cells with solder-dipped and screen-printed top-layer metallization.
`Spraying appears to be the most cost-effective method for
`applying the antireflection coating, although with textured surfaces
`this layer may not be required. Automated machinery has been de(cid:173)
`veloped for connecting the cells together and for their encapsulation
`into solar modules (Ref. 7 .17).
`
`7.5 ANALYSIS OF CANDIDATE FACTORIES
`
`Several alternative approaches to producing silicon cells have been
`outlined in previous sections. To provide common ground for the
`comparison of economic aspects of these approaches, a costing tech(cid:173)
`nique known as SAMICS (Solar Array Manufacturing Industry Cost(cid:173)
`ing Standards) has been developed (Ref. 7.18). Using a computer
`program based on this technique, some of the best documented and
`validated costing has been done of the processing sequences involved
`in fabricating solar modules.
`Large-capacity factories have been designed based on different
`combinations of the technologies described in this chapter and the
`cost of the resulting solar modules compared using the SAMICS meth(cid:173)
`odology. The results have been that several combinations of these
`technologies appear capable of producing solar modules at costs which
`
`Figure 7 .9. Solar cells of 10 cm in diameter with sol(cid:173)
`der-dipped (upper) and screen-printed (lower) top-layer
`metallization.
`
`130
`
`

`

`132
`
`Impro"ed Silicon Cell Technology
`
`Chap. 7
`
`would make them competitive energy generators in some of the large(cid:173)
`scale applications described in Chapter 14. The EFG and dendritic
`web ribbon approaches as well as HEM (heat-exchanger method) with
`subsequent wafer slicing all appear viable silicon sheet technologies,
`with the advanced Czochralski approaches lagging somewhat behind
`(Ref. 7.8).
`As an example of an automated factory capable of producing
`low-cost silicon modules, the characteristics of one of the first to be
`analyzed by the SAMICS approach will be described (Ref. 7.19). The
`product resulting from this factory is a 1.2 X 1.2 m module made up
`of 192 cells fabricated on EFG ribbon silicon cut to a size oflO X 7 .5
`cm as shown in Fig. 7.10. The module efficiency is 11.4%.
`The processing sequence used to produce the module is shown
`in Fig. 7 .11. The Union Carbide process is used to refine metallur(cid:173)
`gical-grade silicon. Silicon sheet is prepared from this material by the
`EFG process and cut to size. The major stages in fabricating cells on
`this material are the application of a back surface field, texture etch(cid:173)
`ing, ion implantation of the junction followed by pulse annealing, and
`the screen printing of contacts. The cells are then encapsulated and
`tested.
`
`,
`
`,
`
`, 'I
`, r;
`
`4' Output 171 W
`
`,
`
`,
`
`4'
`
`,
`,
`
`,
`
`,
`
`,
`,
`,
`
`,
`,
`,
`,
`
`,
`,
`
`, ,
`, ,
`
`,
`
`,
`
`,
`
`,
`
`, ,
`
`,
`I
`
`Soda-
`
`Ethylene vinyl acetate
`
`EFG ribbon cells
`
`Figure 7 .10. Solar cell module produced by the candidate
`factory described in the text. (After Ref, 7.19.)
`
`Metallurgical
`silicon
`
`Refine
`
`Grow sheet
`
`Cut size
`
`Interconnect
`
`Front metal
`
`AR coat
`
`Pack
`and
`ship
`
`Silicon prep.
`
`L___,-------J
`~
`Sheet fabr.
`Cell fabr.
`
`Module fabr.
`
`Figure 7.11. Processing sequence used to produce the
`module of Figure 7.10. (After Ref. 7.19.)
`
`B
`
`Silicon
`refinement
`40,800 ft 2
`
`Sheet, cell,
`and module
`fabrication 91,630 ft 2
`
`Production rate (W/yr)
`
`labor ·force {all shifts)
`
`250,000,000
`
`1, 152 direct
`529 indirect
`
`Factory area (h2 )
`Silicon refinement
`Sheet growth
`Cell fabrication
`Module fabrication
`Warehouse
`Misc. (aisles, shops, cafeteria, etc.)
`Capital equipment($)
`Silicon refinement
`Sheet !J'Owth
`Cell and module-fabrication
`
`40,800
`19,550
`31,200
`10,200
`9,779
`20,901
`
`19,400,000'"
`14,820,000
`8,219,000
`
`'"Union Carbide
`Energy payback time sheet, cell, and module 0.179 year
`
`Figure 7 .12. Calculated space, labor, and capital require•
`ments (1975 $US) to produce cells in a volume of 260
`MWp/yr. The calculated selling price of the module (F.O.B.
`factory) was $0.46 per Wp in the same monetary units.
`(After Ref. 7.19.)
`
`133
`
`

`

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`85
`
`130 pairs of 5-ribbon machines with melt replenisher between
`10 pairs with maintenance bench per column
`One operator per pair
`
`(a)
`
`' "~ - - 230
`
`0 Spray aluminum
`mJ Plasma etch
`El Ion implant
`II Pulse anneal
`CJ Print metal
`§ Ovens
`~ Spray AA
`■ Solder
`■ Encapsulate
`11D Frame
`□ Test
`
`(b)
`
`(a) Physical layout of the nbbon crystal pul(cid:173)
`Figure 7 .13.
`lers for the candidate factory. Each puller produces five
`ribbons simultaneously using the EFG approach ( dimensions
`are in feet). ( b) Physical layout of cell processing, encapsu(cid:173)
`lation, and testing sections of the plant. (After Ref. 7.19.)
`
`210
`
`1
`
`60
`
`15
`
`1
`60 j
`15 ~1
`60 I
`
`134
`
`Exercises
`
`135
`
`To achieve the low costs mentioned, production volume has
`to be an estimated 250 MW0 /yr. The labor requirements and area re(cid:173)
`quirements ·for different steps in the module fabrication are shown in
`Fig. 7.12. The operating time of the modules to pay back the proces(cid:173)
`sing energy invested in them for this processing sequence is a very low
`65 days.
`To give an idea of the size and physical layout of different
`sections of the candidate 250 MW0 /yr factory, Fig. 7 .13(a) shows a
`possible layout for the sheet-preparation section of the factory. Fig(cid:173)
`ure 7 .13(b) shows the sections dealing with cell fabrication, encapsu(cid:173)
`lation, and testing.
`
`7.6 SUMMARY
`
`Several advanced technologies have been developed for producing
`low-cost silicon solar cell modules. These eliminate the deficiencies
`in the standard processing sequence described in Chapter 6.
`Direct growth of silicon ribbons eliminates wafer slicing, which
`is the weak link in any ingot technology. The main requirements on
`techniques for fabricating cells on silicon wafers are that they be ca(cid:173)
`pable of a high degree of automation and that they do not consume
`excessive materials. Several processing sequences satisfy these criteria.
`Economic analysis of candidate factories based on advanced processing
`sequences show that it should be possible to produce silicon solar cell
`modules at prices that would make them competiti