1818
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`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004
`
`Silicon Heterojunction Solar Cell: A New
`Buffer Layer Concept With Low-Temperature
`Epitaxial Silicon
`
`Emanuele Centurioni, Daniele Iencinella, Rita Rizzoli, and Flavio Zignani
`
`Abstract—Amorphous silicon/crystalline silicon heterojunction
`solar cells, deposited by the plasma-enhanced chemical vapor de-
`position (PECVD) technique, have been fabricated using different
`technologies to passivate defects at the heterointerface: without
`treatment, the insertion of a thin intrinsic amorphous layer or
`that of a thin intrinsic epitaxial layer. The open circuit voltage
`of heterojunction solar cells fabricated including an intrinsic
`amorphous buffer layer is strangely lower than in devices with
`no buffer layer. The structure of the amorphous buffer layer is
`investigated by high resolution transmission electron microscope
`observations. As an alternative to amorphous silicon, the insertion
`of a fully epitaxial silicon layer, deposited at low temperature with
`conventional PECVD technique in a hydrogen–silane gas mixture,
`was tested. Using the amorphous silicon/crystalline silicon (p
`a-Si/i epi-Si/n c-Si) heterojunction structure in solar cells, a 13.5%
`efficiency and a 605-mV open circuit voltage were achieved on
`flat Czochralski silicon substrates. These results demonstrate that
`epitaxial silicon can be successfully used to passivate interface
`defects, allowing for an open circuit voltage gain of more than
`50 mV compared to cells with no buffer layer. In this paper, the
`actual structure of the amorphous silicon buffer layer used in
`heterojunction solar cells is discussed. We make the hypothesis
`that this buffer layer, commonly considered amorphous, is actually
`epitaxial.
`
`Index Terms—Amorphous materials, epitaxial growth, photo-
`voltaic cells, semiconductor heterojunctions.
`
`I. INTRODUCTION
`
`T HE
`
`silicon
`silicon/crystalline
`AMORPHOUS
`(a-Si:H/c-Si) heterojunction (HJ) solar cell is one of the
`most interesting technological solutions for the photovoltaic
`market, basically due to the excellent performance and the
`simple low-temperature production process. A key factor of
`this technology is the insertion of a thin intrinsic amorphous
`silicon layer between the amorphous emitter and the crystalline
`base:
`the HJ with intrinsic thin layer (HIT) concept of
`the Sanyo group [1]. This buffer layer, thanks to excellent
`passivating properties, allows very high open circuit voltages
`and efficiencies. Based on this technology, Sanyo has recently
`produced panels with a very high efficiency of 17% [2].
`
`Manuscript received December 30, 2003; revised June 16, 2004. This work
`was supported by an FIRB project of the Italian MIUR. The review of this paper
`was arranged by Editor P. Panayotatos.
`E. Centurioni, D. Iencinella, and R. Rizzoli are with National Research
`Council–Institute of Microelectronics and Microsystems Sezione di Bologna,
`Bologna 40129, Italy (e-mail: iencinella@bo.imm.cnr.it).
`F. Zignani is with the Department of Applied Chemistry and Material Science,
`Bologna University, Bologna I-40136, Italy (e-mail: fzignani@bo.imm.cnr.it).
`Digital Object Identifier 10.1109/TED.2004.836801
`
`Both the n a-Si:H/p c-Si and p a-Si:H/n c-Si structures can
`be used. The main advantage of using a p-type silicon wafer as
`a substrate is its greater minority carrier diffusion length com-
`pared to an n-type silicon wafer, resulting in higher short circuit
`currents, while using n-type silicon wafers, the degradation of
`carrier lifetime caused by the metastable defects related to boron
`doping does not apply [3]. The best solution [4], [5] is still a
`subject of discussion. However, the highest efficiency has been
`demonstrated by Sanyo using the p/n structure.
`In a previous work [6], some epitaxial-like growth during the
`deposition of intrinsic a-Si:H layers on c-Si, using the plasma
`enhanced chemical vapor deposition (PECVD) technique and
`a silane-hydrogen mixture, was observed. Many groups use this
`gas mixture to deposit by PECVD the i buffer layer in their struc-
`tures (both p/n and n/p). However, to our knowledge, limited
`data are available in literature regarding the microstructure of
`the i layer grown on c-Si substrates. We think that the intrinsic
`buffer layer used in heterojunction solar cells, commonly con-
`sidered an amorphous layer, is actually an epitaxial layer.
`In the first part of this paper, the structural composition of
`an intrinsic a-Si:H layer deposited by PECVD on top of a c-Si
`substrate is investigated in detail, including the effect of the i
`layer on the solar cell performance. In the second part, the ex-
`perimental results on solar cell devices with a complete epitaxial
`Si (epi-Si) buffer layer are discussed. The structural character-
`ization of the buffer layers is carried out by cross section high
`resolution transmission electron microscopy (HR-TEM), to dis-
`cern between the amorphous and epitaxial phases. The role of
`different deposition parameters for the epitaxial layer on solar
`cell performance is amply analyzed.
`
`II. EXPERIMENTAL
`
`The samples were deposited by PECVD on Czochralski (CZ)
`(100) n-type 1-
`cm 500- m–thick, polished silicon wafers.
`The c-Si wafers were etched in 0.5% diluted hydrofluoric acid
`before the introduction in the PECVD vacuum system. Separate
`chambers for the deposition of intrinsic n-type and p-type layers
`were used. The deposition conditions are reported in Table I.
`The plasma frequency for all the samples was 13.56 MHz.
`Then
`cm solar cells were fabricated using the structure
`Ag/ITO/p a-Si:H/buffer layer/n c-Si/n
`c-Si/Al. The Ag front
`grid and the Al back contact were evaporated. The indium
`tin oxide (ITO) film was deposited by RF (13.56 MHz) mag-
`netron sputtering at 0.5 W/cm power density, in a 0.021 mbar
`
`0018-9383/04$20.00 © 2004 IEEE
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`
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`CENTURIONI et al.: SILICON HETEROJUNCTION SOLAR CELL: NEW BUFFER LAYER CONCEPT
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`1819
`
`TABLE I
`PECVD DEPOSITION CONDITIONS: PLASMA POWER DENSITY (P), PRESSURE (p), SUBSTRATE TEMPERATURE (T), AND GAS FLOWS
`
`ultrapure Ar atmosphere, at 250 C. The electrical character-
`istics of the p layer (deposited on Corning glass) were: dark
`S/cm, and activation energy
`conductivity
`c-Si layer was deposited by
`eV. The 50-nm n
`PECVD, at low temperature, on the rear surface of the device,
`to reduce the contact resistance and form a back surface field
`(BSF) for photogenerated carriers (for this purpose, the use of a
`dopant diffusion is not appropriate, as it would introduce a high
`temperature fabrication step). Different buffer layer solutions
`were investigated: no buffer layer at all, i a-Si:H buffer layer, i
`epi-Si buffer layer. The electrical characteristics of the i a-Si:H
`layer (deposited on Corning glass) were: dark conductivity
`S/cm, activation energy
`eV, and
`. The a-Si:H
`photo/dark conductivity ratio
`layer thicknesses were evaluated by simulating the experimental
`ultraviolet-visible reflectance spectra. The simulation makes
`use of the Bruggemann effective medium approximation and a
`multilayer model based on Fresnel formulation [7]. The solar
`cellcurrent density–voltage (J–V) characteristics under illumi-
`nation were measured at 100 mW/cm AM1.5G irradiance.
`The HR-TEM observations were performed in cross section
`geometry.
`
`defect density, and the emitter is easily charge-depleted, 2) the
`transparent conductive oxide (TCO) on the top of the device
`has a low work function and the band bending at the TCO/a-Si
`interface strongly contributes to the emitter depletion, resulting
`in a large decrease of the built-in potential even with a good
`quality emitter layer [11]. The dominant factor has not been
`established yet and is currently under investigation.
`As reported in the literature, the deposition of a thin intrinsic
`amorphous silicon (i a-Si:H) layer on the c-Si substrate, in order
`to passivate its surface, is considered one of the key factors of the
`HJ solar cell technology to attain very high efficiencies. On that
`basis, the i a-Si:H layer growth on top of n-type c-Si wafers has
`been studied, using the deposition conditions reported in Table I,
`which result in good quality a-Si:H on glass. A large number of
`samples were deposited with different deposition times and the
`corresponding optically evaluated thicknesses (the procedure is
`described in Section II) are shown in Fig. 2.
`The measured i-layer thicknesses increase linearly only with
`the deposition time longer than 30 s. As the fitting line does
`not intersect the axis origin, a slower growth at the early stages
`or even an initial incubation time can be inferred. The intersec-
`tion of the fitting line with the x axis in Fig. 2 (roughly at 17 s)
`is assumed as the incubation time. HR-TEM cross section im-
`ages of an i a-Si:H/c-Si sample, at different magnifications, are
`Heterojunction solar cells with different p a-Si:H emitter
`shown in Fig. 3. In Fig. 3(a), three main regions are identified:
`thicknesses (7, 14, and 30 nm) and with no intrinsic buffer
`the c-Si structure on the top, the amorphous glue at the bottom,
`layer at the a-Si:H/c-Si interface were deposited. The exper-
`and the deposited layer, previously assumed completely amor-
`imental J–V curves under illumination are shown in Fig. 1.
`phous, in the middle. The resulting thickness of the a-Si:H layer
`decreases as the emitter
`The short-circuit current density
`is approximately 11 nm, in agreement with that expected from
`thickness increases. This was foreseen because the amorphous
`the results in Fig. 2. However, the interface between the c-Si
`emitter layer acts mainly as a “dead layer” [8] in which almost
`substrate and the a-Si:H layer is not clear-cut. Some crystalline
`all the absorbed light does not generate photocurrent. A depen-
`grains with a sawtooth structure extend from the crystalline into
`on emitter thickness is
`dence of the open circuit voltage
`the amorphous phase. This sawtooth grain structure is shown
`decreases from about 590 mV for a
`also evidenced. The
`in detail in Fig. 3(b), a magnification of the region surrounded
`30-nm-thick emitter down to 550 mV for a 7-nm-thick emitter.
`by a white box in Fig. 3(a). The same crystallographic orienta-
`Sawada et al. [9], in contrast to our results, do not report any
`tion of the c-Si substrate is preserved in the grains: continuous
`trend can be explained by a partial or
`dependence. The
`crystalline Si planes crossing the interface formed during the
`complete charge depletion of the p-doped emitter layer, with
`PECVD process are shown in the HR-TEM image, suggesting
`a consequent decrease of the device built-in potential [10]. By
`an epitaxial-like growth. The following growth kinetics can be
`thinning the emitter, the depletion region extends to the whole
`inferred by the nanostructure of the layer (Fig. 3) and by the
`suffers from the built-in potential decrease.
`emitter, and the
`deduction of an incubation time (Fig. 2): at the beginning, the
`Such behavior can be caused by two factors: 1) the electronic
`layer starts growing epitaxially on c-Si and is indistinguishable
`quality of our p-doped a-Si layer is too low, due to a large
`from the c-Si phase employing optical measurements [12]. For
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`
`III. RESULTS AND DISCUSSION
`
`

`

`1820
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`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004
`
`illumination of p a-Si/n c-Si
`Fig. 1. Experimental J–V curves under
`heterojunction solar cells having various emitter thicknesses and no buffer
`layer.
`
`Intrinsic amorphous silicon layer thickness as a function of deposition
`Fig. 2.
`time. The substrate is crystalline silicon, thickness is optically evaluated (see
`Section II ).
`
`Fig. 3. Cross section HR-TEM images, at different magnifications, of an
`intrinsic amorphous silicon layer deposited on top of a crystalline silicon
`wafer. For this sample the expected thickness according to the calibration curve
`of Fig. 2 was 11 nm. In Fig. 3(a) the white box indicates an epitaxial grain
`embedded in the amorphous layer, which is shown at a higher magnification
`in Fig. 3(b).
`
`this reason, its thickness is optically undetectable. After a spe-
`cific time (the incubation time) the deposition rate increases, the
`growth becomes more disordered and continues with an amor-
`phous phase, whose thickness can be optically evaluated.
`Some p (30-nm) a-Si:H/i a-Si:H/n c-Si devices were de-
`posited with different i a-Si:H buffer layer thicknesses, on the
`basis of the calibration shown in Fig. 2. The experimental J–V
`curves under illumination are shown in Fig. 4. The device with
`no buffer layer reveals the higher
`, while the insertion of an
`intrinsic buffer layer, deposited using the plasma conditions to
`.
`obtain a good quality a-Si:H on glass, is detrimental to the
`Such result is unexpected taking into account the very different
`findings reported by T. Tanaka et al. [1], which show that
`the insertion of an i a-Si:H layer, about 5 nm thick, improves
`the device performance. However, it must be pointed out that
`Tanaka et al. used hydrogen diluted gas mixtures to deposit
`the a-Si:H buffer layer. Basing on our results that demonstrate
`an epitaxial growth and the presence of an incubation time
`even for undiluted plasma conditions, and recalling that the
`incubation time is expected to increase if hydrogen dilution
`is applied [13], we believe that fully epitaxial silicon layers,
`rather than amorphous layers, are actually grown in the plasma
`conditions used in [1]. It is worth noting that on Corning glass
`(very often used to test and tailor the deposition conditions) the
`same deposition parameters would give rise to a completely
`amorphous layer, because the substrate itself is amorphous and
`no crystal seed at the beginning drives the growth.
`According to these considerations, we decided to investigate
`the possibility of using fully intrinsic epitaxial silicon as a buffer
`layer (see also [6] and [14]). The epitaxial growth was further fa-
`vored by introducing a high H dilution in the gas mixture, close
`to the chemical equilibrium condition, i.e. when the etching rate
`is equal to the deposition rate [13].
`The p a-Si:H/i epi-Si/n c-Si devices with different deposition
`an epitaxial Si layer on crystalline Si cannot be evaluated by
`times of the intrinsic epitaxial silicon layer, using a 7-nm-thick
`means of optical techniques but, as discussed previously, is ob-
`p layer, were deposited. The deposition conditions for the i layer
`are: 200 C, 0.6 sccm SiH , 94 sccm H (other parameters can
`tainable by HR-TEM analysis. Without any intrinsic buffer layer
`is about 550 mV, then it increases with the depo-
`as a function of
`be found in Table I). The experimental
`(0 min) the
`sition time, remaining constant after 3 min, with a gain of about
`the deposition time of the i epi-Si layer is shown in Fig. 5. In
`behavior, with the increasing of
`30 mV. We remark that the
`this case, the deposition time is used, because the thickness of
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`
`Fig. 4. Experimental J–V curves under illumination of p a-Si/i a-Si/n c-Si
`heterojunction solar cells with various intrinsic amorphous layer thicknesses.
`The p emitter layer thickness is 30 nm.
`
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`

`CENTURIONI et al.: SILICON HETEROJUNCTION SOLAR CELL: NEW BUFFER LAYER CONCEPT
`
`1821
`
`Fig. 5. Experimental V of p a-Si/i epi-Si/n c-Si heterojunction solar cells as
`a function of i epi-Si layer deposition time. The p emitter layer thickness is 7 nm;
`the i layer deposition temperature and silane concentration are T = 200 C and
`[SiH ]=([SiH ] + [H ]) = 0:6%, respectively.
`
`the buffer layer thickness (i.e., the deposition time), is the same
`as that reported in [1]. The other cell parameters do not show
`any evident dependence on the deposition time, stable values
`mA/cm and FF
`are measured. The
`of
`improvement can be explained by a reduction of defect states
`on the surface of the c-Si substrate, with a resulting reduction
`in carrier recombination in this zone. Since the deposited layer
`is epitaxial, no significant change in the energy band structure,
`compared to the underlying c-Si, is expected. In this case the re-
`combination current of electrons diffusing from the base to the
`emitter cannot be reduced by a conduction band offset (contrary
`to the case of the i a-Si buffer layer). We believe that, depositing
`in conditions close to the chemical equilibrium (the deposition
`rate is almost zero), a rearrangement of the c-Si surface resulting
`in a reduction of surface defect density is more likely to occur
`than a passivation of such defects.
`The effect of the deposition temperature of the i layer on
`the solar cell parameters was also investigated. Taking into ac-
`count the results shown in Fig. 5, a set of devices with a 3-min
`i epi-layer (0.6 sccm SiH , 94 sccm H ) was fabricated (the
`p a-Si:H emitter thickness was 7 nm). The experimental
`versus deposition temperature of the intrinsic layer is shown in
`increases when the temperature is decreased,
`Fig. 6. The
`then it remains almost constant between 150 C and 100 C,
`with a gain of about 25 mV from 250 C to 150 C. Once again
`and FF do not show any dependence on the deposition tem-
`perature. Using the i layer deposited at 150 C for 3 min, a
`of more than 600 mV is obtained, with a gain of about 50
`mV compared to the case with no intrinsic layer. This value is
`comparable with the results reported in literature for p a-Si:H/i
`a-Si:H/n c-Si hetero-structures using an amorphous buffer layer,
`an n-type CZ crystalline silicon substrate and no texturization of
`the c-Si substrate [8].
`It is not clear why a reduction in the deposition temperature
`. However, the same result is
`of the i epi-layer improves the
`found in the case of microcrystalline p-i-n solar cells, where a
`obtained indicates that a pure hydrogen plasma
`The high
`low temperature deposition of the intrinsic layer is preferred in
`is able to remove the kind of defects giving carrier recombi-
`. For p-i-n c-Si devices, Das et al. [15]
`order to get high
`nation, as expected by an etching action. On the other hand,
`suggest that the higher temperature facilitates the incorporation
`the presence of an S-shape on the J–V characteristics indicates
`in the film of oxygen that can form defect states, acting as car-
`that some charge defects, not acting as recombination centers,
`rier recombination centers. Similar behavior of oxygen incorpo-
`are also generated. This result confirms the damaging effect of
`ration in the epitaxial buffer layer can be guessed at, due to the
`a hydrogen plasma treatment before the p layer deposition, as
`presence of a large number of defects in the crystalline structure
`reported by Ulyashin et al. [16].
`of epitaxial silicon.
`Very low silane concentration results both in a good
`Another deposition parameter has a crucial effect on the
`and a good FF. As mentioned before, the deposition condition
`i-layer passivation properties on the c-Si surface, i.e., the silane
`at very low silane concentration (close to the chemical equi-
`SiH
`H . A
`concentration in the gas mixture, SiH
`librium) is expected to give the best result. Since etching and
`set of devices with a 7-nm-thick p a-Si:H layer and a 3 min
`deposition act at the same rate, there is no net etching and con-
`i epi-layer was fabricated, varying the silane concentration in
`sequently no formation of charged defects (no S-shape, good
`the gas mixture during the deposition of the i epi-layer. The
`FF). Moreover, the very low deposition rate permits a surface
`temperature was chosen as 150 C, which was shown to be
`structure rearrangement resulting in a net reduction of recom-
`and FF as a function of
`optimal in Fig. 6. Experimental
`). Increasing the silane concentration
`bination centers (high
`silane concentration are shown in Fig. 7. A pure hydrogen
`decrease. For a 2.5% silane concentration the
`both FF and
`plasma treatment (no silane) allows the achievement of a high
`values for different cells on the
`spread of the measured
`, up to about 600 mV, but has a detrimental effect on the
`same wafer indicates the presence of surface inhomogeneities.
`FF. In fact the cell current under illumination starts falling off
`Moving away from the chemical equilibrium conditions, the
`, resulting in an S-shaped
`in voltages much lower than the
`J–V characteristic (not shown here) and a very low fill factor.
`growth of an amorphous phase is favored and can occur in
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`
`Fig. 6. Experimental V of p a-Si/i epi-Si/n c-Si heterojunction solar cells
`vs. deposition temperature of the intrinsic epitaxial layer. The p emitter layer
`thickness is 7 nm; the i layer deposition time and silane concentration are t =
`3 min and [SiH ]=([SiH ] + [H ]) = 0:6%, respectively.
`
`

`

`1822
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004
`
`Fig. 7. Experimental V and FF of p a-Si/i epi-Si/n c-Si heterojunction solar
`cells versus silane concentration during the i epi-Si deposition. The p emitter
`layer thickness is 7 nm; the i layer deposition time and temperature are t =
`3 min and T = 150 C, respectively.
`
`some wafer regions, preventing the formation of a fully epi-
`value is as
`taxial layer. For a 5% silane concentration the
`low as 470 mV, which is approximately the value measured on
`cells with a 5-nm i a-Si layer deposited without H dilution.
`can be correlated with the growth of an
`The drop in
`amorphous phase mixed with some epitaxial grains, with a
`sawtooth amorphous/crystalline interface (see Fig. 3), due to
`the higher silane concentration. This morphology gives rise to
`recombination paths along the intrinsic layer which negatively
`. The results in Fig. 7 show that the 0.6% silane
`affect the
`concentration, used in the previous experiments, was already
`a good choice.
`is limited by the emitter layer
`To check whether the
`quality or by the TCO/emitter interface properties rather than
`by the recombination in the base bulk or at the emitter/base
`interface, a p a-Si:H/i epi-Si/n c-Si device with a thicker emitter
`layer was deposited. The purpose was to investigate whether the
`dependence on the emitter thickness, observed in devices
`without the buffer layer (see Fig. 1), is still present. The device
`with the i epi-Si layer and 30-nm-thick emitter has shown a
`increase of about 10 mV, compared to the device having
`a 7-nm-thick emitter. This indicates that a further increase of
`, by an appropriate optimization of the p layer and TCO
`the
`properties, is possible. A valid alternative to improve the emitter
`quality is the use of a better microcrystalline emitter instead of
`the amorphous one. A p-doped microcrystalline silicon ( c-Si)
`emitter gives rise to a high built-in potential. Moreover, due
`to its better electronic quality (higher doping level and carrier
`diffusion length) with respect to amorphous silicon, it does
`not suffer from eventual charge depletion at the junction with
`TCO front contact [17]. In a previous work [12], heterojunction
`devices with a p c-Si emitter and an i a-Si:H buffer layer were
`fabricated. A remarkable result of 640-mV open-circuit voltage
`was achieved, due to the higher built-in potential of the device.
`c-Si on an epitaxial buffer layer
`However, the deposition of
`can be very difficult, resulting in unwanted epitaxial growth
`of the emitter too. An attempt to get over this technological
`difficulty, using a double layer emitter (p a-Si/p c-Si), is under
`investigation.
`The highest efficiencies of p a-Si/i epi-Si/n c-Si cells were
`obtained using a 7-nm-thick p layer. The external quantum ef-
`ficiency QE and the J–V curve under illumination of one of the
`best devices with i epi-Si layer, with 13.5% efficiency, 0.79 FF,
`and 605 mV
`, are shown in Fig. 8. This re-
`28.2 mA/cm
`sult is comparable with the state of the art for p/n heterojunction
`solar cells on flat CZ silicon wafers fabricated with a completely
`low temperature process (no dopant diffusion on the back of the
`cell, temperature lower than 250 C) [8].
`A HR-TEM cross section image of the same device (J–V)
`and QE in Fig. 8) can be seen in Fig. 9. In the image, three
`main regions can be recognized: the c-Si structure on the
`top, the ITO layer at the bottom (darker region) and the p
`of a few monoatomic layers in which the crystalline matrix is
`a-Si:H layer in the middle. The thickness of the p a-Si:H layer,
`still visible. This region can be associated with the intrinsic
`evaluated from the HR-TEM image, is about 7 nm and confirms
`epitaxial layer. The very fine thickness of the i epi-Si is in
`the optically measured thickness. The interface between the
`agreement with a deposition rate close to zero, i.e. deposition
`p a-Si:H and c-Si, in contrast with Fig. 3, is more clear-cut.
`conditions close to chemical equilibrium.
`Moreover, at the interface, the figure shows a brighter zone
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`
`Fig. 8. External quantum efficiency QE and J–V curve under illumination of
`one of the best devices having an i epi-Si buffer layer. The p emitter thickness
`is 7 nm.
`
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`CENTURIONI et al.: SILICON HETEROJUNCTION SOLAR CELL: NEW BUFFER LAYER CONCEPT
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`on amorphous silicon/crystalline silicon heterojunction solar cell perfor-
`mance,” IEEE Electron Device Lett., vol. 24, pp. 177–179, Mar. 2003.
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`Summonte, and A. Migliori, “Silicon heterojunction solar cells with p
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`A. Shah, “Very low temperature epitaxial growth of hpi type silicon for
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`materials and solar cells grown by pulsed PECVD technique,” in Proc.
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`etching and hydrogen plasma treatment: application to heterojunction
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`formance of a-Si/c-Si and c-Si/c-Si heterojunction solar cells: simula-
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`
`Fig. 9. Cross section HR-TEM image of the same device shown in Fig. 8.
`
`IV. CONCLUSION
`
`The HR-TEM cross section observations of our a-Si:H/c-Si
`heterojunction solar cells show that
`the typical deposition
`conditions used to deposit an i a-Si:H buffer layer on top of
`c-Si can actually lead to the formation of a partial or even
`complete epitaxial layer. We suggest that, epitaxial silicon, rather
`than amorphous silicon, is often unknowingly deposited as a
`buffer layer in heterojunction solar cells, because the epitaxial
`growth is favored in hydrogen diluted plasmas (commonly
`used in intrinsic buffer layer deposition). To our knowledge,
`no HR-TEM observation of the i buffer layers deposited on
`c-Si has ever been shown in literature, whereas the HR-TEM is
`one of the best techniques that can distinguish the amorphous
`phase from the epitaxial phase in these structures. Using a
`very thin intrinsic epitaxial buffer layer deposited by PECVD,
`a gain of more than 50 mV in open circuit voltage, compared
`to the cell with no buffer layer, is demonstrated. This gain
`is equivalent to the best results reported in literature, further
`confirming the hypothesis that the intrinsic (usually considered
`“amorphous”) buffer layer used in heterojunction solar cells
`is actually an epitaxial layer.
`The epitaxial silicon layer has been deposited at low tem-
`perature (the best cell performance is with the 150 C epi-Si
`layer), resulting in a completely low temperature process for the
`fabrication of the solar cell. A reproducible 13.5% efficiency is
`achieved.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank Dr. A. Migliori, CNR-IMM
`Sezione di Bologna Institute, for HR-TEM observations.
`
`Emanuele Centurioni was born in Florence, Italy,
`in 1969. He received the B.Sc. degree (Laurea de-
`gree) in physics, and the Ph.D. degree in material en-
`gineering from the University of Bologna, Bologna,
`Italy, in 1995 and 2000, respectively.
`During this period he was with the IMM-CNR
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`on glass.
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