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`UNITED STATES PATENT AND TRADEMARK OFFICE
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` _________________
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`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`_________________
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`LENOVO (UNITED STATES) INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II LLC
`Patent Owner
`
`_________________
`
`Case No. IPR2024-01226
`Patent No. 7,646,835 B1
`___________________
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,646,835 B1
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
`
`
`
`TABLE OF CONTENTS
`LISTING OF EXHIBITS ........................................................................................ vii
`CHALLENGED CLAIMS ....................................................................................... ix
`I.
`INTRODUCTION ........................................................................................... 1
`II. MANDATORY NOTICES ............................................................................. 1
`A.
`Real Party-in-Interest ............................................................................ 1
`B.
`Related Matters ...................................................................................... 1
`C.
`Counsel and Service Information .......................................................... 2
`III. PAYMENT OF FEES ..................................................................................... 2
`IV. GROUNDS FOR STANDING ........................................................................ 2
`V.
`PRECISE RELIEF REQUESTED AND GROUNDS .................................... 3
`A.
`Identification of Challenge .................................................................... 3
`1. Ground 1: ......................................................................................... 3
`2. Ground 2: ......................................................................................... 3
`3. Ground 3: ......................................................................................... 3
`VI. LEVEL OF ORDINARY SKILL .................................................................... 4
`VII. SUMMARY OF THE ’835 Patent .................................................................. 4
`A.
`’835 Patent ............................................................................................. 4
`B.
`Priority Date .......................................................................................... 8
`C.
`The ’835 Patent’s Relevant File History ............................................... 9
`VIII. SUMMARY OF THE PRIOR ART .............................................................. 10
`A.
`Johnson ................................................................................................ 10
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`Jeddeloh ............................................................................................... 13
`B.
`C. Keeth .................................................................................................... 14
`IX. CLAIM CONSTRUCTION .......................................................................... 15
`X.
`THE CHALLENGED CLAIMS ARE UNPATENTABLE .......................... 17
`A. Ground 1: Claims 1-23 are obvious over Johnson in view of Jeddeloh
`
`17
`1. Claim 1 .......................................................................................... 17
`2. Claim 2 .......................................................................................... 38
`3. Claim 3 .......................................................................................... 38
`4. Claim 4 .......................................................................................... 42
`5. Claim 5 .......................................................................................... 44
`6. Claim 6 .......................................................................................... 46
`7. Claim 7 .......................................................................................... 49
`8. Claim 8 .......................................................................................... 57
`9. Claim 9 .......................................................................................... 57
`10. Claim 10 ...................................................................................... 57
`11. Claim 11 ...................................................................................... 57
`12. Claim 12 ...................................................................................... 57
`13. Claim 13 ...................................................................................... 58
`14. Claim 14 ...................................................................................... 64
`15. Claim 15 ...................................................................................... 66
`16. Claim 16 ...................................................................................... 67
`17. Claim 17 ...................................................................................... 68
`ii
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`18. Claim 18 ...................................................................................... 68
`19. Claim 19 ...................................................................................... 68
`20. Claim 20 ...................................................................................... 69
`21. Claim 21 ...................................................................................... 71
`22. Claim 22 ...................................................................................... 71
`23. Claim 23 ...................................................................................... 71
`B. Ground 2: Claims 1-3, 7-8, and 12 are obvious over Johnson in view
`of Keeth.......................................................................................................... 73
`1. Claim 1 .......................................................................................... 73
`2. Claim 2 .......................................................................................... 81
`3. Claim 3 .......................................................................................... 81
`7. Claim 7 .......................................................................................... 83
`8. Claim 8 .......................................................................................... 84
`9. Claim 12 ........................................................................................ 84
`C. Ground 3: Claims 4-6, 9-11, and 13-19 are Obvious Over Johnson in
`View of Keeth and Jeddeloh .......................................................................... 85
`XI. ARGUMENTS FOR DISCRETIONARY DENIAL SHOULD BE
`REJECTED. ............................................................................................................. 86
`A.
`Section 325(d) Is Inapplicable Because the Asserted Art Was Never
`Evaluated During Examination. .................................................................... 86
`B. Any Secondary Considerations Cannot Overcome the Strong
`Evidence of Obviousness. .............................................................................. 88
`C.
`Institution is Proper Under Section 314(a) and Fintiv. ....................... 88
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`U.S. Patent 7,646,835 B1
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`XII. PRESERVATION OF RIGHTS .................................................................... 89
`XIII. CONCLUSION .............................................................................................. 89
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`iv
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`Cases 
`
`TABLE OF AUTHORITIES
`
`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`Advanced Bionics, LLC v. Med-El Elektromedizinische Gerate GmbH, IPR2019-
`
`01469, Paper 6 (P.T.A.B. Feb. 13, 2020) ...................................................... 86, 87
`
`Ariosa Diagnostics v. Verinata Health, Inc., 805 F.3d 1359 (Fed. Cir. 2015) .......... 3
`
`Becton, Dickinson, & Co. v. B. Braun Melsungen AG, IPR2017-01586, Paper 8
`
`(P.T.A.B. Dec. 15, 2017) ...................................................................................... 86
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007) ........................................ passim
`
`Loper Bright Enters. v. Raimondo, No. 22-451 (U.S. June 28, 2024) .................... 89
`
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) ......................................... 16
`
`Toyota Motor Corp. v. Cellport Sys., Inc., IPR2015-00633, Paper 11 (Aug. 14,
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`2015) ..................................................................................................................... 16
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`Tristar Products, Inc. v. Choon’s Design, LLC, IPR2015-01883, Paper 6 (P.T.A.B.
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`Mar. 9, 2016) ........................................................................................................ 88
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`Uber Techs. Inc. v. X One, Inc., 957 F. 3d 1334 (Fed. Cir. 2020) .............. 43, 65, 67
`
`Wyers v. Master Lock Co., 616 F.3d 1231 (Fed. Cir. 2010) .................................... 88
`
`Statutes 
`
`35 U.S.C. § 103 .......................................................................................................... 3
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`35 U.S.C. § 314 ........................................................................................................ 88
`
`35 U.S.C. § 325 ........................................................................................................ 86
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`Rules 
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`37 C.F.R. § 42.100 ................................................................................................... 16
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`37 C.F.R. § 42.104 ..................................................................................................... 2
`
`Other Authorities 
`
`Director Vidal, Memorandum, “Interim Procedure for Discretionary Denials in
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`AIA Post-Grant Proceedings with Parallel District Court Litigation,” (June 21,
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`2022) ..................................................................................................................... 89
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`LISTING OF EXHIBITS
`
`Description
`U.S. Patent No. 7,646,835 B1
`
`Declaration of R. Jacob Baker, P.E., Ph.D.
`
`Prosecution History of U.S. Patent No. 7,646,835 B1
`
`U.S. Patent No. 6,434,081 B1 to Johnson et al.
`(“Johnson”) issued on August 13, 2002 U.S.
`
`U.S. Patent No. 6,629,222 B1 to Jeddeloh (“Jeddeloh”)
`issued on September 30, 2003
`
`U.S. Patent No. 6,115,318 A to Keeth (“Keeth”) issued on
`September 5, 2000
`
`Claim Construction Order, Intellectual Ventures I LLC et
`al. v. Lenovo Group Limited, 6:23-cv-307 (WDTX)
`
`Synchronous DRAM Architectures, Organizations, and
`Alternative Technologies by Bruce L. Jacob, published in
`December of 2002 (“Jacob”)
`
`RAM Guide Part I: DRAM and SDRAM Basics by Jon
`Stokes, published in July of 2000 (“Stokes”)
`
`Design and PCB Layout Considerations for Dynamic
`Memories Interfaced to the Z80 CPU by Tim Olmstead,
`published in October of 1996 (“Olmstead”)
`
`A Performance Comparison of Contemporary DRAM
`Architectures by Vinodh Cuppu et al., published in May of
`1999 (“Cuppu”)
`
`How to Use DDR SDRAM by Elpida Memory, published
`in April of 2002 (“Elpida”)
`
`vii
`
`Exhibit
`Exhibit 1001
`
`Exhibit 1002
`
`Exhibit 1003
`
`Exhibit 1004
`
`Exhibit 1005
`
`Exhibit 1006
`
`Exhibit 1007
`
`Exhibit 1008
`
`Exhibit 1009
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`Exhibit 1010
`
`Exhibit 1011
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`Exhibit 1012
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`Hyundai Electronics Actively Supplying DDR SDRAM
`Modules to Major PC Makers by SK hynix, published in
`March of 2001
`
`SLDRAM: High Performance, Open-Standard Memory by
`Peter Gillingham et al., published in December of 1997
`(“SLDRAM”)
`
`3.1. How Memory Works with the Processor by Technick,
`published in March of 1998
`
`Memory Access Scheduling by Scott Rixner et al.,
`published in March of 2000
`
`Computer-System Operation, published in July of 1999
`(“Computer-System”)
`
`Course-to-fine Estimation of Visual Motion by Eero P.
`Simoncelli, published in September of 1993
`
`Modern Dictionary of Electronics Seventh Edition by
`Rudolf F. Graf, published in February of 1999
`(“Dictionary of Electronics”)
`
`Merriam-Webster’s Collegiate Dictionary Tenth Edition,
`published in 2000 (“Merriam-Webster’s Dictionary”)
`
`Double Data Rate (DDR) SDRAM Specification by
`JEDEC Solid State Technology Association, published in
`June of 2000
`
`Exhibit 1013
`
`Exhibit 1014
`
`Exhibit 1015
`
`Exhibit 1016
`
`Exhibit 1017
`
`Exhibit 1018
`
`Exhibit 1019
`
`Exhibit 1020
`
`Exhibit 1021
`
`Exhibit 1022
`
`Declaration of Duncan Bauserman
`
`
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`CHALLENGED CLAIMS
`
`Claim 1
`A method for automatically calibrating intra-cycle timing relationships
`between command signals, data signals, and sampling signals for an
`integrated circuit device, the method comprising:
`
`1.P
`
`1.1
`
`generating command signals to access an integrated circuit component
`
`1.2
`
`accessing data signals to convey data for the integrated circuit
`component;
`
`1.3
`
`accessing sampling signals to control sampling of the data signals; and
`
`1.4.a
`
`systematically altering a phase shift of the command signals, a phase
`shift of the data signals, and a phase shift of the sampling signals to
`determine a valid operation range of the integrated circuit device,
`1.4.b wherein the valid operation range includes an optimal operation point for
`the integrated circuit device.
`Claim 2
`The method of claim 1, wherein the integrated circuit device comprises a
`DRAM component.
`
`2
`
`Claim 3
`The method of claim 2, wherein said altering is performed by a memory
`controller coupled to the DRAM component.
`Claim 4
`The method of claim 2, wherein the DRAM component comprises a
`DDR DRAM component.
`
`Claim 5
`The method of claim 4, wherein the data signals comprise a plurality of
`data bus (DQ) signals for the DDR DRAM component.
`
`3
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`4
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`5
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`U.S. Patent 7,646,835 B1
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`Claim 6
`The method of claim 5, wherein the sampling signals comprise a
`plurality of sampling bus (DQS) signals for the DDR DRAM component.
`Claim 7
`A system for automatically calibrating intra-cycle timing relationships
`between command signals, data signals, and sampling signals for an
`integrated circuit device, the system comprising:
`
`a controller configured to generate command signals for accessing an
`integrated circuit component;
`
`6
`
`7.P
`
`7.1
`
`7.2.a a delay calibrator integrated within the controller and
`7.2.b configured to access data signals conveying data for the integrated circuit
`device and
`
`7.2.c
`
`to access sampling signals for controlling sampling of the data signals,
`
`7.3.a
`
`wherein the delay calibrator is further configured to systematically alter a
`phase shift of the command signals, a phase shift of the data signals, and
`a phase shift of the sampling signals to determine a valid operation range
`of the integrated circuit device; and
`7.3.b wherein the valid operation range includes an optimal operation point for
`the integrated circuit device.
`Claim 8
`The system of claim 7, wherein the integrated circuit device comprises a
`DRAM component.
`
`8
`
`Claim 9
`The system of claim 8, wherein the DRAM component comprises a DDR
`DRAM component.
`
`9
`
`Claim 10
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`10
`
`11
`
`12.P
`
`The system of claim 9, wherein the data signals comprise a plurality of
`DQ signals for the DDR DRAM component.
`Claim 11
`The system of claim 10, wherein the sampling signals comprise a
`plurality of DQS signals for the DDR DRAM component.
`Claim 12
`In a memory controller, a method for finding an operating mode for a
`DRAM component by altering intra-cycle timing relationships between
`command signals, data signals, and sampling signals for the DRAM
`component, the method comprising:
`
`12.1 generating command signals to access a DRAM component;
`
`12.2 accessing data signals to convey data for the DRAM component;
`
`12.3 accessing sampling signals to control sampling of the data signals; and
`
`12.4
`
`13.1
`
`13.2
`
`systematically altering a phase shift of the command signals, a phase
`shift of the data signals, and a phase shift of the sampling signals to
`determine a valid operating range of the DRAM component.
`Claim 13
`The method of claim 12, further comprising: performing a coarse
`calibration by altering the phase shift of the command signals, the phase
`shift of the data signals, and the phase shift of the sampling signals in
`accordance with a large step interval to determine if the valid operating
`range of the DRAM component exists; and
`
`if the valid operating range exists, then performing a fine calibration by
`altering the phase shift of the command signals, the phase shift of the
`data signals, and the phase shift of the sampling signals in accordance
`with a small step interval to identify an optimal operating mode of the
`DRAM component.
`
`Claim 14
`
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
`
`The method of claim 13, wherein said performing a coarse calibration
`comprises simultaneously varying each of the phase shift of the
`command signal, the phase shift of the data signal, and the phase shift of
`the sampling signal by a five percent step increase.
`Claim 15
`The method of claim 13, wherein said performing a fine calibration
`comprises varying each of the phase shift of the command signal, the
`phase shift of the data signal, and the phase shift of the sampling signal
`one at a time by a two percent step increase.
`Claim 16
`The method of claim 13, further comprising configuring the memory
`controller to operate the DRAM component in the optimal operating
`mode.
`
`Claim 17
`The method of claim 12, wherein the DRAM component comprises a
`DDR DRAM component.
`
`Claim 18
`The method of claim 17, wherein the data signals comprise a plurality of
`DQ signals for the DDR DRAM component.
`Claim 19
`The method of claim 18, wherein the sampling signals comprise a
`plurality of DQS signals for the DDR DRAM component.
`Claim 20
`A computer readable media having stored thereon, computer-executable
`instructions that, if executed by a processor, cause the processor to
`perform a method for finding an operating mode for a DDR DRAM
`component by altering intra-cycle timing relationships between
`command signals, data signals, and sampling signals for the DDR
`DRAM component, the method comprising:
`xii
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`14
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`15
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`16
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`17
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`18
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`19
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`20.P
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`20.1 generating command signals to access a DDR DRAM component;
`20.2 accessing DQ signals to convey DQ signals for the DDR DRAM
`component;
`
`20.3 accessing DQS signals to control sampling of the DQ signals; and
`
`20.4
`
`21.1
`
`21.2
`
`22
`
`23.P
`
`systematically altering a phase shift of the command signals, a phase
`shift of the DQ signals, and a phase shift of the DQS signals to determine
`a valid operating range of the DDR DRAM component.
`Claim 21
`The computer readable media of claim 20, wherein the method further
`comprises: performing a coarse calibration by altering the phase shift of
`the command signals, the phase shift of the data signals, and the phase
`shift of the sampling signals in accordance with a large step interval if
`the valid operating range of the DDR DRAM component exists; and
`
`if the valid operating range exists, then performing a fine calibration by
`altering the phase shift of the command signals, the phase shift of the
`data signals, and the phase shift of the sampling signals in accordance
`with a small step interval to identify an optimal operating mode of the
`DDR DRAM component.
`
`Claim 22
`The computer readable media of claim 21, wherein the method further
`comprises configuring the memory controller to operate the DRAM
`component in the optimal operating mode.
`Claim 23
`In a memory controller, a method for finding an operating mode for a
`DDR DRAM component coupled to a PCB (printed circuit board) by
`altering intra-cycle timing relationships between command signals, data
`signals, and sampling signals for the DDR DRAM component, the
`method comprising:
`
`23.1 generating command signals to access a DDR DRAM component;
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`U.S. Patent 7,646,835 B1
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`23.2 accessing data signals to convey data for the DDR DRAM component;
`
`23.3 accessing sampling signals to control sampling of the data signals; and
`
`23.4
`
`systematically altering a phase shift of the command signals, a phase
`shift of the data signals, and a phase shift of the sampling signals
`transmitted via a PCB to determine a valid operating range of the DDR
`DRAM component.
`
`
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`
`I.
`
`INTRODUCTION
`
`IPR2024-01226
`U.S. Patent 7,646,835 B1
`
`Lenovo (United States), Inc. (“Petitioner”) respectfully requests inter partes
`
`review (“IPR”) of claims 1-23 (“Challenged Claims”1) of U.S. Patent No. 7,646,835
`
`(“’835 Patent”).
`
`II. MANDATORY NOTICES
`
`A. Real Party-in-Interest
`Petitioner hereby names Lenovo (United States) Inc. as a real-party-in-interest
`
`and, solely because it is named as a defendant in the co-pending district court case
`
`listed below, further identifies Lenovo Group Ltd. as a real party-in-interest.
`
`B. Related Matters
`Intellectual Ventures I LLC et al. has asserted the ’835 Patent against Lenovo
`
`Group Ltd. in Intellectual Ventures I LLC et al. v. Lenovo Group Limited, 6:23-cv-
`
`307 (WDTX) (“co-pending litigation”).
`
`The ’835 Patent is also asserted in the following cases:
`
` Intellectual Ventures I LLC et al. v. OnePlus Technology
`
`(Shenzen) Co., Ltd., No. 6-23-cv-00290 (WDTX, filed April 20,
`
`2023);
`
`
`1 A subset of the Challenged Claims are being asserted (and at issue) in the co-
`
`pending litigation.
`
`
`
`
`1
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`

`
`
`IPR2024-01226
`U.S. Patent 7,646,835 B1
`
` Intellectual Ventures I LLC et al. v. Zebra Technologies
`
`Corporation, No. 6-23-cv-00292 (WDTX, filed April 20, 2023);
`
` Intellectual Ventures II LLC v. Lenovo Group Limited, No. 6-23-
`
`cv-00068 (WDTX, filed February 2, 2023, terminated on April
`
`26, 2023).
`
`C. Counsel and Service Information
`Lead counsel is Dinesh Melwani (Reg. No. 60,670). Back-up counsel are
`
`Ankit Aggarwal (Reg. No. 67,882) and William Uhr (Reg. No. 71,282). Service
`
`information is: Bookoff McAndrews, PLLC, 2000 Pennsylvania Avenue NW Suite
`
`4001, Washington, DC 20006; Tel.: 202.808.3497; Fax.: 202.450.5538; email:
`
`docketing@bomcip.com, dmelwani@bomcip.com, aaggarwal@bomcip.com, and
`
`wuhr@bomcip.com. Petitioner consents to electronic service.
`
`III. PAYMENT OF FEES
`
`The PTO is authorized to charge any fees due during this proceeding to
`
`Deposit Account No. 50-5906.
`
`IV. GROUNDS FOR STANDING
`
`Petitioner certifies that the ’835 Patent is available for review and Petitioner
`
`is not barred/estopped from requesting review on these grounds. 37 C.F.R.
`
`§42.104(a).
`
`
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`2
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`V.
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`PRECISE RELIEF REQUESTED AND GROUNDS
`
`A.
`Identification of Challenge2
`Petitioner requests the Challenged Claims to be found unpatentable based on
`
`the following grounds:
`
`1.
`Ground 1:
`Claims 1-23 are unpatentable under 35 U.S.C. §103 as obvious over U.S.
`
`Patent No. 6,434,081 (“Johnson”) in view of U.S. Patent No. 6,629,222
`
`(“Jeddeloh”).
`
`2.
`Ground 2:
`Claims 1, 2, 3, 7, 8, and 12 are unpatentable under 35 U.S.C. §103 as obvious
`
`over Johnson in view of U.S. Patent No. 6,115,318 (“Keeth”).
`
`3.
`Ground 3:
`Claims 4-6, 9-11, and 13-19 are unpatentable under 35 U.S.C. §103 as obvious
`
`over Johnson in view of Jeddeloh and in view of Keeth.
`
`
`2 For each Ground, Petitioner does not rely on any reference other than those listed
`
`here. Other references are discussed to show the state of the art at the time of the
`
`invention. See Ariosa Diagnostics v. Verinata Health, Inc., 805 F.3d 1359, 1365
`
`(Fed. Cir. 2015).
`
`
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`3
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`VI. LEVEL OF ORDINARY SKILL
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`As of November 17, 2003, a person having ordinary skill in the art
`
`(“POSITA”) would have had a bachelor’s degree in electrical engineering, computer
`
`engineering, or the equivalent, and two to three years of experience designing high-
`
`speed computer memory devices. More practical experience could also substitute for
`
`formal education, while a higher level of education could substitute for practical
`
`experience. Ex-1002, ¶¶31-35.
`
`VII. SUMMARY OF THE ’835 PATENT
`
`A.
`’835 Patent
`The ’835 Patent describes calibrating intra-cycle timing relationships for
`
`integrated circuit devices. Ex-1001, Abstract. To ensure that critical timing
`
`specifications remain within critical specification parameters, automatic calibration
`
`of intra-cycle timing relationships for sampling signals of an integrated circuit
`
`device are provided. Id., 1:34-37; Ex-1002, ¶55.
`
`As shown below, memory system 100 of the ’835 Patent includes a memory
`
`controller 101 with a delay calibrator 105. Ex-1001, 2:63-64. The memory controller
`
`101 is coupled to a plurality of DRAM components 110 via: a) a command/address
`
`bus 102; b) a data bus (“DQ”); and c) a sampling signal bus (“DQS”). Id., 2:64-3:2;
`
`Ex-1002, ¶¶56-57.
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`IPR2024-01226
`U.S. Patent 7,646,835 B1
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`
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`Ex-1001, 2; Ex-1002, ¶¶56-57.
`
`The ’835 Patent states that the memory system “implements a method for
`
`automatically calibrating intra-cycle timing relationships between command signals
`
`of the command/address bus 102, data signals of the DQ bus 103, and sampling
`
`signals of the DQS bus 104.” Ex-1001, 3:3-6. Also, “each of the DRAM components
`
`110 comprise the integrated circuit device for which the calibration adjustments are
`
`performed,” and the memory controller 101 performs the adjusting. Id., 3:6-9; Ex-
`
`1002, ¶¶57-58.
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`Figure 3, reproduced below, depicts relative timings of the command/address
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`signals, the DQ signals, and the DQS signals. Ex-1002, ¶59. Timing diagram 300
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`shows a DQ signal 301 and a DQS signal 302 during a read transaction. Ex-1001,
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`4:53-54. The rising and falling edges of DQS 302 are aligned with the rising and
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`falling edges of the DQ signal 301. Id., 4:56-58. To align sampling windows with
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`rise-and-hold times of the DQ signal 301, a 90° phase shift is performed to “place
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`the sampling windows 310 at the center of the rise-and-hold times of DQ 301 (e.g.,
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`shown as DQS delayed 303).” Id., 4:59-61. DQS 303 is delayed such that rising and
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`falling edges are centered to rise-and-hold times of DQ signal 301:
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`Id., 4; Ex-1002, ¶60.
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`The phase-shifted DQS signal 303 is generated by the delay calibrator 105
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`during an automatic calibration process. Ex-1002, ¶60. During calibration, a phase
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`relationship between signals is automatically adjusted to calibrate the operation of
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`the DRAM components 110. Id. The automatic calibration process purportedly
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`increases the reliability rate of computer systems and can be used to increase the
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`maximum obtainable performance of such computer systems. Ex-1001, 3:58-64; Ex-
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`1002, ¶¶61-62.
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`Optimal operation of DRAM components is allegedly achieved by calibrating
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`intra-cycle timing relationships between command/address signals, DQ signals, and
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`DQS signals. Ex-1001, 3:13-16. The calibration includes “generating command
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`signals and address signals for accessing the DRAM components (e.g., DRAM chips
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`of a memory module) [,] … accessing data signals (e.g., DQ signals) that convey
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`data for the DRAM components… [, and] accessing sampling signals (e.g., DQS
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`signals) for controlling the sampling of the data signals.” Id., 3:16-27. A phase
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`relationship between the command, data, and sampling signals is then automatically
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`adjusted. Id., 3:27-29; Ex-1002, ¶¶63-65.
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`The phase shift of a DQS signal can be adjusted over a minimum to a
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`maximum value (e.g., 0-100% shift). Ex-1001, 5:7-13. Embodiments “search for and
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`find the valid region of operation within the configuration space without requiring
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`knowledge, a-priori, where the valid region is.” Id., 4:10-13.
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`B.
`Priority Date
`The application underlying the ’835 Patent (U.S. Application No. 10/716,320)
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`(“’320 application”) was filed on November 17, 2003, and issued as the ’835 Patent
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`on January 12, 2010. Accordingly, the earliest possible effective filing date of the
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`’835 Patent is November 17, 2003.
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`C. The ’835 Patent’s Relevant File History
`The ’320 application was filed with twenty-two (22) claims. During
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`examination, the Examiner issued multiple Office Actions rejecting all pending
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`claims over U.S. Patent No. 6,553,472 (“Yang”) or over Yang in view of U.S. Patent
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`Publication No. 2004/0160833 (“Suzuki”), U.S. Patent No. 6,016,282 (“Keeth
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`’282”), and/or U.S. Patent No. 5,781,766 (“Davis”). Ex-1003, 108-122; 167-180;
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`216; 257-269; 293-303; Ex-1002, ¶¶66-75. In a June 11, 2007, response, the
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`Applicant argued that Yang does not disclose “automatic calibration” of cycle timing
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`relationships, but instead discloses “programming clock delays, command delays,
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`read command parameter delays, and write command parameter delays of a memory
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`controller.” Ex-1003, 286-287 (emphasis in original).
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`In Office Actions dated September 6, 2007, January 25, 2008, and July 23,
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`2008, the Examiner applied the same references and U.S. 2003/0122696 (“Johnson”)
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`to reject the pending claims. Id., 167-180; 196-202; 259-260. In response to each
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`Office Action, Applicant argued that the claims distinguished the references because
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`“a process requiring user input” allegedly “is not automatically calibrating.” Id., 154-
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`155, 204, 248.
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`A December 12, 2008, Office Action rejected the pending claims based on the
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`same references in combination with U.S. Pub. No. 2002/0078316 (“Nakamura”).
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`Id., 109-122.
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`On March 12, 2009, Applicant amended all independent claims and argued
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`that the cited art did not teach “systematically altering respective phase shifts of the
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`command, data, and sampling signals to determine a valid operation range of the
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`integrated device,” as the amended claims then recited. Id., 89-103 (emphasis in
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`original); Ex-1002, ¶76.
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`The Office mailed a Notice of Allowance on May 14, 2009. Ex-1003, 65; Ex-
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`1002, ¶77.
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`Accordingly, during prosecution of
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`the ’320 application, Applicant
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`unsuccessfully argued that automatic calibration of cycle timing relationships is not
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`taught by “programming [] delays of a memory controller.” Ex-1003, 286-287. The
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`Applicant also unsuccessfully argued that “a process requiring user input” allegedly
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`“is not automatically calibrating.” Id., 154-155, 204, 248. The issued claims of the
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`’835 Patent were allowed as a result of amending the independent claims to recite
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`“systematically altering respective phase shifts of the command, data, and sampling
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`signals to determine a valid operation range of the integrated device,” or similar
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`limitations. Ex-1003, 65.
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`VIII. SUMMARY OF THE PRIOR ART
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`A.
`Johnson
`Johnson was filed on May 12, 2000, issued on August 13, 2002, and is prior
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`art under Sections 102(a), (b), and (e). Ex-1004, 1; Ex-1002, ¶78.
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`Johnson teaches a “calibration technique which is useful for calibrating the
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`timing of control and data signals in memory devices.” Ex-1004, 1:5-8; Ex-1002,
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`¶79. Johnson’s technique calibrates timing relationships between commands on a
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`CA0-9 bus, data on data paths DQ, and a command clock signal (CCLK), and a data
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`clock signal (DCLK) for a memory device. Ex-1004, 3:30-47; Ex-1002, ¶79.
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`Johnson discloses “a plurality of SLDRAM modules 11a...11n which are
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`accessed and controlled by a memory controller 13. Memory controller 13 provides
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`a command link to each of the SLDRAM modules 11a...11n which includes a clock
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`signal CCLK [] and a 10 bit command bus data path CA0-9. [A] bi-directional data
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`bus DQO-17 is provided between memory controller 13 and each of the SLDRAM
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`modules 11a...11n, as are bi-directional data clocks DCLK0 and DCLK1.” Ex-1004,
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`3:31-44.
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`Id., 4, Ex-1002, ¶80.
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`Johnson further teaches that “all incoming data can properly be aligned with
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`respect to the clock used to latch in the data by adjusting the data delays relative to
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`the clock (