IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`––––––––––
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`––––––––––
`ADVANCED MICRO DEVICES, INC. and PENSANDO SYSTEMS, INC.,
`Petitioners,
`v.
`CONCURRENT VENTURES, LLC and XTREAMEDGE, INC.,
`Patent Owners.
`––––––––––
`Case No. IPR2025-00478
`U.S. Patent 8,924,596
`––––––––––
`Declaration of Dr. Samuel Russ
`
`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000001
`IPR2025-00478 (Advanced Micro Devices, Inc., Pensando Systems, Inc. v. Concurrent Ventures, LLC, XtreamEdge, Inc.)
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`

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`TABLE OF CONTENTS
`
`I.
`
`II.
`
`V.
`
`Pages
`OVERVIEW OF THE TECHNOLOGY ......................................................... 6
`A. Multiprocessor Architectures ................................................................ 8
`B. Memory Mapping ................................................................................ 10
`C. Multi Threading and Semaphores ....................................................... 12
`THE ’596 PATENT ....................................................................................... 18
`A.
`Prosecution History ............................................................................. 19
`B.
`Priority Date ........................................................................................ 21
`C.
`District Court Allegations ................................................................... 22
`D.
`Challenged Claims .............................................................................. 23
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 24
`III.
`IV. CLAIM CONSTRUCTION .......................................................................... 25
`A.
`“input/output queue implemented in hardware” ................................. 26
`INVALIDITY ................................................................................................ 27
`A.
`Ground 1: Claims 1-2, 5-8, 11-14, and 17-18 are Rendered
`Obvious in View of Dongare and Gewirtz .......................................... 28
`1.
`Dongare (Ex-1005) ................................................................... 29
`2.
`Gewirtz (Ex-1006) .................................................................... 32
`3.
`Independent Claim 1 ................................................................. 36
`4.
`Dependent Claim 2 ................................................................... 79
`5.
`Dependent Claim 5 ................................................................... 80
`6.
`Dependent Claim 6 ................................................................... 82
`7.
`Independent Claim 7 ................................................................. 83
`8.
`Dependent Claim 8 ................................................................... 91
`9.
`Dependent Claim 11 ................................................................. 91
`10. Dependent Claim 12 ................................................................. 92
`11.
`Independent Claim 13 ............................................................... 92
`12. Dependent Claim 14 ................................................................. 99
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000002
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`B.
`
`C.
`
`D.
`
`13. Dependent Claim 17 ................................................................. 99
`14. Dependent Claim 18 ............................................................... 100
`Ground 2: Claims 3-4, 9-10, and 15-16 are Rendered Obvious
`in view of Dongare, Gewirtz, and Matsunami .................................. 100
`1.
`Matsunami (Ex-1007) ............................................................. 100
`2.
`Dependent Claims 3-4 ............................................................. 102
`3.
`Dependent Claims 9-10 ........................................................... 109
`4.
`Dependent Claims 15-16 ......................................................... 110
`Ground 3: Claims 1-2, 6-8, 12-14, and 18 are Rendered
`Obvious by Khawand and Rosenthal ................................................ 110
`1.
`Khawand (Ex-1008) ................................................................ 111
`2.
`Rosenthal (Ex-1009) ............................................................... 113
`3.
`Independent Claim 1 ............................................................... 115
`4.
`Dependent Claim 2 ................................................................. 147
`5.
`Dependent Claim 6 ................................................................. 148
`6.
`Independent Claim 7 ............................................................... 150
`7.
`Dependent Claim 8 ................................................................. 158
`8.
`Dependent Claim 12 ............................................................... 158
`9.
`Independent Claim 13 ............................................................. 159
`10. Dependent Claim 14 ............................................................... 165
`11. Dependent Claim 18 ............................................................... 165
`Ground 4: Claims 1-2, 6-8, 12-14, and 18 are Rendered
`Obvious by Khawand, Rosenthal, and Ohkawa ................................ 166
`1.
`Ohkawa (Ex-1010) .................................................................. 166
`2.
`Independent Claim 1 ............................................................... 168
`3.
`Dependent Claim 2 ................................................................. 179
`4.
`Dependent Claim 6 ................................................................. 179
`5.
`Independent Claim 7 ............................................................... 180
`6.
`Dependent Claim 8 ................................................................. 184
`7.
`Dependent Claim 12 ............................................................... 184
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`E.
`
`Independent Claim 13 ............................................................. 185
`8.
`Dependent Claim 14 ............................................................... 191
`9.
`10. Dependent Claim 18 ............................................................... 191
`Ground 5: Claims 3-4, 9-10, and 15-16 are Rendered Obvious
`in view of Khawand, Rosenthal, Ohkawa, and Matsunami .............. 191
`1.
`Dependent Claims 3-4 ............................................................. 192
`2.
`Dependent Claims 9-10 ........................................................... 197
`3.
`Dependent Claims 15-16 ......................................................... 197
`VI. BACKGROUND AND QUALIFICATIONS ............................................. 198
`A.
`Compensation .................................................................................... 200
`B. Materials and Other Information Considered ................................... 200
`VII. UNDERSTANDING OF THE LAW .......................................................... 200
`VIII. RESERVATION OF RIGHTS .................................................................... 201
`APPENDIX 1: CURRICULUM VITAE OF DR. SAMUEL RUSS ..................... 202
`APPENDIX 2: MATERIALS CONSIDERED IN THE PREPARATION OF
`THIS DECLARATION ............................................................................... 216
`APPENDIX 3: CHALLENGED CLAIMS ............................................................ 219
`APPENDIX 4: UNDERSTANDING OF THE LAW ...........................................225
`
`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000004
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`I, Samuel Russ declare as follows:
`1.
`My name is Samuel Russ. I am an Associate Professor of Electrical
`
`Engineering at the University of South Alabama. I have prepared this report as an
`
`expert witness retained by Advanced Micro Devices, Inc. and Pensando Systems,
`
`Inc. In this report I give my opinions as to whether certain claims of U.S. Patent
`
`No. 8,924,596 (“the ’596 patent”) are invalid. I provide technical bases for these
`
`opinions as appropriate.
`
`2.
`
`This report contains statements of my opinions formed to date and the
`
`bases and reasons for those opinions. I may offer additional opinions based on
`
`further review of materials in this case, including opinions and/or testimony of
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`other expert witnesses. I make this declaration based upon my own personal
`
`knowledge and, if called upon to testify, would testify competently to the matters
`
`contained herein.
`
`3.
`
`The ’596 patent seeks to avoid software synchronization (e.g., with
`
`semaphores and mutexes) when accessing command or input queues. But the
`
`alleged invention—a “reservation register” that stores the amount of space in the
`
`input queue—was trivial and already known in the art, for example as taught by
`
`Gewirtz (Ground 1) and Rosenthal (Ground 3). Grounds 1 and 3 simply combine
`
`these references with conventional computer architecture arrangements that
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000005
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`describe the various processing elements and queues recited in the Challenged
`
`Claims.
`
`I.
`
`OVERVIEW OF THE TECHNOLOGY
`4.
`One of the basic data structures used in computers is called a queue.
`
`A queue is a line, like a queue of people in line to see a movie. In the computing
`
`arts, a queue is a linear data structure in which the first element put into the queue
`
`is the first element that comes out. In other words, like a line of people at a movie,
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`the first one entering the line is also the first one to exit. Queues, in life and in
`
`computing, maintain the “first come, first served” policy or, stated differently, the
`
`first one in is the first one out. First-in-first-out is often abbreviated “FIFO.”
`
`5.
`
`If a queue is implemented in ordinary memory, it has a “write pointer”
`
`(a pointer to the place where elements enter the queue) and a “read pointer” (a
`
`pointer to the place where elements exit the queue).
`
`6.
`
`Queues are a powerful way to synchronize concurrently running
`
`processes or threads. For example, if one thread has access to the write pointer and
`
`another has access to the read pointer, there is not a thread safety issue because
`
`only one thread can update the write pointer (write data to the queue) and only one
`
`thread can update the read pointer (read data from the queue). This is why queues
`
`are often placed by design between concurrently running processes.
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000006
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`7.
`
`Because queues are so useful, chip manufacturers have created
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`dedicated chips called FIFOs. FIFOs have a write port, a read port, and flags that
`
`indicate how full the FIFO is and whether there is space available, and how much
`
`space is available. Examples include the Texas Instruments SN74V273 FIFO.
`
`The datasheet is dated 2001 and we used it recently in our (successful) satellite
`
`design at the University of South Alabama.
`
`8.
`
`Queue have finite size. Once a queue is full, no new data can be
`
`placed into it. That is why queue structures included mechanisms to indicate how
`
`much space was left. By being able to obtain this information, whoever was
`
`writing to the queue was able to avoid overflowing it with too much data.
`
`9.
`
`A common mechanism for reporting queue space was with registers,
`
`which have been one of the basic building blocks of computers for many decades.
`
`For example, Gewirtz described a reservation register that tracked the “available
`
`entries for reservation” in a queue. Ex-1006, 4:5-7. Rosenthal also described a
`
`flow control register that “stores an indication of the number of available spaces
`
`for commands” in its command queue. Ex-1009, 16:33-37. The prior art is replete
`
`with examples of registers that tracked the amount of space free in a queue. See
`
`also Ex-1011, 9:47-58 (describing a counter for a queue and setting a queue full
`
`flag when the counter reaches the queue’s size limit); Ex-1026, 9:12-18 (describing
`
`a counter that is checked against the queue size to determine if a request can be
`
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000007
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`issued to that queue); Ex-1027, 8:26-32 (describing using a counter to determine
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`the available space in a FIFO); Ex-1028, 8:32-43 (describing a counter that counts
`
`the number of available storage locations in a buffer).
`
`A. Multiprocessor Architectures
`10. By 2013, it was common for computers to have multiple processors
`
`inside them. For example, multiprocessor systems consisting of CPUs, dedicated
`
`hardware engines, DSPs, embedded processors, and other types of processors were
`
`widely known and used. Queues were often used to facilitate communications
`
`between these processors. See Ex-1005, Abstract (describing multi-engine
`
`processing system with queues); Ex-1006, 4:51-5:6 (describing software running
`
`on multiple processor cores using a reservation register to determine if it can write
`
`to a queue); Ex-1007, 6:10-12 (describing multiprocessor used in a network
`
`channel adapter); Ex-1008, Abstract (describing a multiprocessor system with
`
`queues that delegates tasks from processor to another); Ex-1009, 4:49-59
`
`(describing multiple bus masters and bus slaves connected to an I/O bus); Ex-1010,
`
`Abstract (describing coordinated processing using queues for groups of
`
`processors).
`
`11. Another example of a multiprocessor system with queue-based
`
`synchronization among three processors is found in a 2008 article by Ou.
`
`Ex-1016. Ou’s Fig. 3 is illustrative of the architecture:
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`Ex-1016, Fig. 3.
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`12. Ou’s Figure 3 illustrates a task manager that coordinates the MPU
`
`(processor) and DSP (digital signal processor) by use of command queues. As
`
`described:
`
`The proposed HPI consists of three interactive controllers (FSMs)
`including the MPU manager, the DSP manager, and the task manager
`as depicted in Fig. 3. Communication among those controllers is
`through command queues. The MPU manager takes care of commands
`such as data push/pull from the MPU or the DSP. The DSP manager
`will receive commands from the MPU or the DSP. Some commands
`such as “free memory page request/release” are handled by the DSP
`manager itself while others like “dequeue/enqueue” are bypassed to the
`task manager. The main function of the task manager is to monitor all
`task status and schedule any ready-to-run task to idle DSP thread for
`execution.
`
`Ex-1016, 000001-2.
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`13. The Ou article also describes an embodiment, in which a third “task
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`manager” processor manages enqueuing and dequeuing commands going to/from a
`
`DSP and interfacing with an MPU manager running on the main processor.
`
`Ex-1016, 000001-2. In general, well before the filing of the ’596 patent, it was
`
`well known in the art that there were several ways to arrange multiple processors
`
`to interact with and to manage queues, and Ou’s embodiment is one example.
`
`By 2013, a particular arrangement of tasks among processors would not be novel,
`
`as many possible arrangements would have been well known in the art. To restate,
`
`in Ou’s embodiment the addition of a separate task manager co-processor enabled
`
`the MPU and DSP both to operate more efficiently. The MPU is freed from
`
`having to create and assign tasks (processes) to the DSP and the DSP is able to be
`
`kept busier because the dedicated task manager can assign another task as soon as
`
`one finishes.
`
`B. Memory Mapping
`14. One common way to allow a processor to access internal control
`
`registers is by mapping the registers to addresses in memory space, where accesses
`
`to that address will be directed to the register. Consider, for example, the Atmel
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`8-bit microcontroller. This is a common, inexpensive microcontroller. Consider
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`this excerpt from its datasheet:
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000010
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`Ex-1025, 000008.
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`15. This shows that the “UCSR0C” register is accessed via address
`
`location 0xC2 (hexadecimal C2). A read from address 0xC2 reads the values
`
`found inside that register. This is why all modern processors (that I am aware of)
`
`use this technique—a CPU can easily read and write control registers simply by
`
`reading and writing to specific addresses.
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`16. Examining the table in the datasheet, it is clear that the defined
`
`memory range goes from memory address 0x00 to memory address 0xFF.
`
`Ex-1025, 000008-11. In other words, it would be a simple matter for a hardware
`
`designer to add more registers and map them into the processor’s memory space at
`
`an address higher than 0xFF without disrupting the operation of any other registers.
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`A processor’s memory map is determined by the address decoder that selects and
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`activates the specific memory location or device that corresponds to the given
`
`address. By using different address ranges for various memory components and
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`devices (like RAM, ROM, I/O ports, registers), the address decoder determines
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`which device to access based on the address being used.
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000011
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`C. Multi Threading and Semaphores
`17. Binary electronic computers are only approximately 75 years old.
`
`The first electronic computers, based on vacuum tubes, came along during World
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`War 2 and their better-known transistorized versions came out shortly after. Even
`
`in my childhood, computers were roughly the size of refrigerators.
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`18. Early computers contained a single central processing unit (CPU) that
`
`fetched and executed instructions. In that world, programs were relatively
`
`straightforward—one CPU ran one program. Even then problems arose.
`
`Computers performed input/output operations and, as storage technology evolved,
`
`access to input/output soon became necessary to store a non-trivial amount of
`
`information.
`
`19.
`
`In the emerging world where bulk data storage was much slower than
`
`the CPU, CPUs migrated from polling input/output (waiting for the I/O operation
`
`to complete before continuing) to interrupt driven to improve overall performance.
`
`In the interrupt-driven model, a CPU assigns an operation to an I/O unit and then
`
`resumes its main program. Later, when the I/O unit is finished, the CPU is notified
`
`via an interrupt. Importantly, an interrupt can occur at any time while the program
`
`is running. At this point, programming becomes significantly more complicated.
`
`20.
`
`I teach interrupts in my sophomore-level undergraduate
`
`microprocessor class. The important feature is that the main program can be
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000012
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`interrupted at any moment. The only way that the main program can run reliably is
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`if the interrupt software maintains the illusion, to the main program, that nothing is
`
`happening behind the program’s back. For example, if an interrupt could
`
`overwrite the variable “x” then the main program would live in a world where “x”
`
`could spontaneously change with no warning. It rapidly becomes clear that
`
`something fundamental has shifted.
`
`21.
`
`In the history of computing, this issue came to the surface rather
`
`quickly. For example, it was discussed in a seminal paper by Djiskstra in 1966 (as
`
`cited in a paper by Wirth in 1969). In other words, the problem of two pieces of
`
`software that can execute in any order was recognized as a problem almost 60
`
`years ago.
`
`22.
`
`In short, the main program and the interrupt service routine are
`
`separate threads (to be clear, the name “thread” did not come along until later, but
`
`the concept is clear). In the computing arts, a thread is a single schedulable piece
`
`of software. Each thread has its own set of instructions, access to its own set of
`
`data (variables), and its own program state. Importantly, one thread cannot alter
`
`the instructions, data, or state of another thread, or else the result will be chaotic
`
`and unpredictable execution.
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`23. This situation was explained in a 1969 paper by Niklaus Wirth.
`
`Ex-1012. Wirth’s paper explains the following:
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000013
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`Most modern data processing systems consist of several machines
`which can operate concurrently, and most programs make use of many
`of these concurrently operating units. This is particularly the case for
`input and output (I/O) activities. ...
`
`The difficulties arising with multiprogramming compared with
`uniprogramming (programming a single sequential algorithm) are such
`that every effort is made to save the programmer from having to specify
`concurrent operations.
`
`On the machine code level, however, these difficulties cannot be
`circumvented: the activities of every unit must be specified in detail.
`Unfortunately this level offers the least safety against programming
`mistakes, because there is no redundancy as provided by higher level
`languages, which can be used by compilers to check against errors. It
`is therefore particularly desirable that at the machine code level the
`programmer be able to work on the basis of clear and systematic
`concepts of concurrent activities--their initiation, termination, and
`synchronization.
`
`Ex-1012, 000001.
`
`24.
`
`In other words, programmers needed access to a simple set of
`
`concepts to enable concurrently running threads to be able to work together
`
`harmoniously on a single computer. The paper goes on to explain the concept of
`
`semaphores.
`
`Synchronization among concurrent processes is performed by means of
`variables common to those processes. Dijkstra has thoroughly
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000014
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`investigated the problems arising from access of common variables
`(and the reader is encouraged to study his treatise at this point [3, 7]).
`He postulates two basic operations which constitute an interlocking
`mechanism, named P and V. These operations act on variables which
`assume integral values (0, 1, 2, • • • ). Dijkstra appropriately calls these
`variables semaphores, and it is subsequently postulated that P and V be
`the only operations applicable to variables designated as semaphores.
`(The observation of this postulate will be crucial for the implementation
`discussed below.) The operation V(s) (3) increments the value of the
`semaphore S by 1. The operation P(S) (4) can only be performed when
`the value of S is positive, which is decremented by 1. From this it
`follows that P may effectuate a delay of program execution until
`another process performs a V operation on the semaphore S. Thereby
`a synchronization of the two processes is obtained.
`
`Ex-1012, 000002.
`
`25. To recap, by the mid-1960s, it was clear that concurrently running
`
`pieces of software need a mechanism to synchronize their actions. For example,
`
`one purpose of a semaphore is to make sure that only one thread has access to a
`
`resource at a time.
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`26. Consider what happens when two threads have write access to the
`
`same area of memory without coordination between them. When one thread writes
`
`to a variable in memory and reads back the variable, normal programming practice
`
`demands that the variable have the same value. The analogy I use in my class is
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`Advanced Micro Devices, Inc., Pensando Systems, Inc. - Ex. 1003, Page 000015
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`this: imagine a world where you drive to work and when you return home, it has
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`been replaced by an elephant sanctuary. Like threads, we expect the world to
`
`remain the same when we are not observing it.
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`27. The semaphores described by Dijkstra serve as a safeguard. A thread
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`can only obtain write access if it successfully performs a P operation with a
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`positive result.
`
`28. A subtle side effect of semaphores is that a single semaphore has to be
`
`updated atomically. That is, the process of reading and updating (and specifically
`
`the internal steps of the P operation) must be executed without any interruptions.
`
`In computing circles, this is sometimes called atomic test and set.
`
`29. Circling back to the P and V example in the Wirth paper, a common
`
`approach was to extend the P and V concept incrementally, e.g., to modify P and V
`
`such that the integer value of the semaphore represents the amount of empty space
`
`available for storage. If a thread requested “100” and the value of the integer
`
`was 110, the integer would be lowered to 10 and the 100 bytes would be made
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`available to the thread. If a thread requested “200” and the value of the integer
`
`was 110, the thread would block until more space was available. In other words,
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`semaphores are very useful tools for providing concurrent access to hardware
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`resources.
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`30.
`
`It is worth noting that semaphores were implemented in software or
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`hardware. In software, semaphores were maintained as long as the “P” process can
`
`occur without interrupts. In other words, the heart of the “P” process contains a
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`critical section, a piece of code that runs with interrupts disabled. In hardware,
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`many mechanisms existed to permit atomic (that is, uninterruptible or indivisible)
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`access. For example, U.S. Patent No. 5,276,886 to Dror describes a hardware
`
`semaphore. Ex-1013. A 2006 article describes the creation of a set of operating-
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`system-accessible hardware semaphores to permit more rapid and more efficient
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`access to hardware co-processors. Ex-1014. As explained in this article, hardware
`
`implementations were more efficient, and included the ability to arbitrate as
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`necessary and to perform atomic operations on shared resources, such as a read of
`
`a queue status register, or writing or reading to queue, and updating the queue
`
`status register accordingly based on read (increment) or write (decrement). See
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`generally Ex-1014.
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`31. Modern CPUs, such as the commonly used ARM CPU, have
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`instructions in their instruction set architecture specifically for accessing memory
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`locations with mutual exclusion, a foundational step for creating a semaphore. For
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`example, the LDREX (“load register exclusive”) and STREX (“store register
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`exclusive”) instructions perform these steps. Ex-1015, 000004. In other words,
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`ARM processors include instructions to maintain variables in memory that can be
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`“locked” and “unlocked” by running processes. This enables processes to maintain
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`semaphores or to track other information without concerns of another process
`
`overwriting it without permission.
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`32. To recap, the notion of communicating processes is quite old, as is the
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`notion of a simple set of constructs to manage their interaction. One common way
`
`to manage their interaction is with a semaphore, a construct that can exist in
`
`software or hardware.
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`33. To summarize, semaphores, hardware status registers, and/or memory
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`locations accessed atomically by multiple processors, queues, multiple independent
`
`processors / processes, and concurrent queue access were all extremely well known
`
`in the art by 2013.
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`II. THE ’596 PATENT
`34. The ’596 patent does not purport to invent FIFO buffers or queues; it
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`admits these existed in the prior art. Ex-1001, 1:22-25. The ’596 patent also
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`admits that software techniques used for synchronization such as semaphores and
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`mutexes existed in the prior art. Ex-1001, 1:25-27.
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`35. According to the ’596 patent, “[i]t can become a challenge to ensure
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`the module command queues (FIFOs) are not overfilled, thus synchronization is
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`required amongst the multiplicity of processing elements.” Ex-1001, 1:22-32. “In
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`the prior art, such synchronization is performed using software techniques, such as
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`semaphores and mutexes to a shared available space count variable in memory.”
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`Ex-1001, 1:25-27. “However, this takes additional processing time, making this
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`process non-optimal.” Ex-1001, 1:27-29.
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`36. To address these supposed shortcomings of software semaphores, the
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`’596 patent purports to invent a “shared counter resource (e.g. a register) in the
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`hardware representing how much free space there is in the command queue,
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`accessible to one or more processing elements.” Ex-1001, 3:30-34.
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`37. However, as explained above, the prior art already included
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`multiprocessor architectures with queues, along with registers indicating the
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`amount of free space in those queues. Supra §I.
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`A.
`38.
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`Prosecution History
`I understand that the ’596 patent is the start of a family of patents,
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`including patents in the United States and China, and an application filed in
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`Europe.
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`39. On August 19, 2014, the ’596 patent received a first action allowance.
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`Ex-1002, 000060-74. Prior to the allowance, an examiner-initiated interview
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`occurred, in which the applicant agreed to the Examiner’s claim amendments as
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`reflected in the claims of the issued patent. Ex-1002, 000075.
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`40.
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`In the Examiner’s reasons for allowance, the Examiner stated the
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`reason as:
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`the inclusion of the specific details of a reservation register that is
`accessed by the second processing element and the feature of the second
`processing element notifying the first processing element to issue a
`command to the input queue if the reservation register value indicates
`that there is available space in the input queue as are now included in
`independent claim 1
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`…
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`the inclusion of the specific details of a reservation register that is
`accessed by the second processing element and the feature of the second
`processing element receiving a command from the first processing
`element and the second processing element issuing said command to
`the input queue if the reservation register value indicates that there is
`available space in the input queue, as are now included in independent
`claims 7 and 13.
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`Ex-1002, 000072-73.
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`41.
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`I understand that there was no substantive discussion of any prior art
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`references, including the cited prior art references, during the prosecution of the
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`’596 patent.
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`42. Before the ’596 patent issued in the United States, a European
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`counterpart application, EP14867963 (the “EU Counterpart”) was filed. Ex-1004,
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`000080-83. During prosecution of the EU Counterpart, on June 7, 2016, an
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`International Search Report and Written Opinion on Patentability were issued.
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`Ex-1004, 000084-88. On June 23, 2016, the application Entered into the European
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`phase of prosecution. Ex-1004, 000089-93.
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`43. On May 19, 2017, a Supplementary European Search Report was
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`issued that identified U.S. Patent No. 8,051,227 to Gewirtz and U.S. Patent
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`Application Publication No. 2002/069245 to Kim. Ex-1004, 000111-113.
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`44. On June 13, 2017, an EU Search Opinion was issued rejecting all
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`claims on the basis of the Gewirtz and Kim. Ex-1004, 000114-123. The EU
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`Search Opinion specifically noted that “[i]t is common general knowledge of the
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`skilled person [] that an output queue [] is an implementation choice for buffering
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`request results from a storage device.” Ex-1004, 000119.
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`45. On April 23, 2018, the Applicant responded to the EU Search
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`Opinion, by amending the claims to address the issues identified in the EU Search
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`Opinion and argued against the rejections based on Gewirtz and Kim. Ex-1004,
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`000128-144.
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`46. On July 21, 2021, the EU Counterpart was considered withdrawn for
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`non-payment of the 7-year renewal fee. Ex-1004, 000159.
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`Priority Date
`B.
`47. The ’596 patent was filed on December 6, 2013, and did not claim
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`priority to any earlier filed application. I have not conducted any analysis as to
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`whether the ’596 patent is entitled to any claim of earlier priority. For the purposes
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`of this declaration, I have applied a December 6, 2013, priority date for my
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`opinions.
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`C. District Court Allegations
`In the District Cou