United States Patent (19)
`Leyendecker
`
`USOO5867065A
`Patent Number:
`11
`(45) Date of Patent:
`
`5,867,065
`Feb. 2, 1999
`
`54) FREQUENCY SELECTIVE PREDISTORTION
`IN A LINEAR TRANSMITTER
`
`75 Inventor: Robert Richard Leyendecker, Blaine,
`Wash.
`
`73 Assignee: Glenayre Electronics, Inc., Charlotte,
`N.C.
`
`21 Appl. No.: 852,390
`22 Filed:
`May 7, 1997
`(51) Int. Cl. .................................................. HO3F 1/26
`52 U.S. Cl. ............................................. 330/149; 455/126
`58 Field of Search ................................ 330/2, 129, 136,
`330/149; 455/126
`
`56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,193,224 3/1993 McNicol et al. ........................ 455/126
`5,732,333 3/1998 Cox et al. .......
`... 455/126
`5,748,678 5/1998 Valentine et al. ................... 330/149 X
`FOREIGN PATENT DOCUMENTS
`62-139425 6/1987 Japan ..................................... 455/126
`
`Primary Examiner Steven Mottola
`Attorney, Agent, or Firm-Christensen O'Connor Johnson
`& Kindness PLLC
`
`57
`
`ABSTRACT
`
`A System for linearly transmitting an amplified output signal
`using predistortion is disclosed. The System uses a Straight
`inverse modeling Scheme to more easily and accurately
`determine the inverse of the distortion caused by a power
`amplifier of a RF transmitter. The direct inverse modeling
`Scheme of the present invention indexes the LUT using the
`modulated input signals instead of the potentially noisier
`output signals, which helps to increase the accuracy of the
`predistortion. The predistorter System Stores complex coef
`ficients in the LUT, which are then used as the tap weights
`of a digital filter implementing the predistorter. Finally, the
`trainer uses a modified version of the power amplifier output
`Signal. The modified power amplifier output signal has the
`in-band distortion removed from the power amplifier output
`Signal.
`
`21 Claims, 11 Drawing Sheets
`
`
`
`MODULATED
`INPUT
`
`TTTTTTTTTTTTTTTTTTTTTTT
`
`UPCONVERTER/
`MODULATOR
`
`1024
`
`f026
`
`LOOK-UP
`TABLE
`
`DOWNCONVERTER/
`DEMODULATOR
`
`PETITIONERS EXHIBIT 1006
`Page 1 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 1 of 11
`
`5,867,065
`
`101
`
`103
`
`MODULATION
`
`SIGNAL 4.
`TRAINER
`107
`
`f05
`
`roo 22. 7
`2
`(PRIOR ART)
`
`MODULATION
`SIGNAL
`
`
`
`
`
`
`
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`
`PREDISTORTER
`---------------------------------
`203
`COMPLEX
`WEIGHTING
`
`(OR MACNITUDE)
`CALCULATOR
`
`H-TO PA
`
`(PRIOR ART)
`
`- P OUTPUT:30
`Map PA INPUT
`TO MODEL
`PA TRANSFER CHARACTERISTIC
`
`STORE IN
`FIRST LUT
`
`
`
`
`
`calculate INVERSES-808
`OF PA TRANSFER
`CHARACTERISTIC
`
`22.5
`
`STORE INVERSE IN
`SECOND PD LUT
`
`305
`
`(PRIOR ART)
`
`PETITIONERS EXHIBIT 1006
`Page 2 of 25
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`

`

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`U.S. Patent
`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 2 of 11
`
`5,867,065
`5,867,065
`
`YOLVINGORITYOLVRIQIC
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`
`PETITIONERS EXHIBIT 1006
`Page 3 of 25
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`PETITIONERS EXHIBIT 1006
`Page 3 of 25
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`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 3 of 11
`
`5,867,065
`
`500 &
`
`
`
`MODULATION
`SIGNAL
`(COMPLEX)
`
`407
`
`MEMORY EFFECT
`COMPENSATOR
`
`105
`
`
`
`
`
`
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`TRAINER
`
`DIRECT INVERSE
`MODELER
`
`f03
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`IN
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`OUT
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`IN
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`OUT
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`f03
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`
`52. 3.e4
`
`DIRECT INVERSE MODEL
`
`52. 13?
`
`PETITIONERS EXHIBIT 1006
`Page 4 of 25
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`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 4 of 11
`
`5,867,065
`
`MODULATION
`SIGNAL SAMPLE
`
`60
`f
`PREDISTORTION
`FILTER
`
`PA
`INPUT SIGNAL
`
`PA
`OUTPUT SICNAL
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`f03
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`FILTER
`COEFFICIENTS
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`UPDATES
`y 607
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`ADDRESS
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`C609
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`COMPLEX CAIN BRANCHK
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`OUTPUT
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`ADDRESS
`CENERATOR
`
`
`
`707
`
`LUT
`(COMPLEY PARAMETERS)
`
`603
`
`PETITIONERS EXHIBIT 1006
`Page 5 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 5 of 11
`
`5,867,065
`
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`PETITIONERS EXHIBIT 1006
`Page 6 of 25
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`PETITIONERS EXHIBIT 1006
`Page 6 of 25
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`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 6 of 11
`
`5,867,065
`
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`PETITIONERS EXHIBIT 1006
`Page 7 of 25
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`PETITIONERS EXHIBIT 1006
`Page 7 of 25
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`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 7 of 11
`
`5,867,065
`
`707
`
`COMPLEY ODUATION SAMPLE
`f 10f
`SAMPLE POWER
`(ORMACNITUDE)
`CALCUATOR
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`(COMPLEX)
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`SAMPLES
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`SAMPLES
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`INVERSE
`MODELER
`
`22. 72
`2.
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`431
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`FILTER
`COEFFICIENT
`UPDATES
`
`MODULATION
`SCNA, SAMPLES
`(COMPLEX)
`
`PA INPUT SICNAL
`SAMPLES
`
`PA OUTPUTSICNA,
`SAMPLES
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`
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`INVERSE
`MODELER
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`WRITE
`ADDRESS
`
`FILTER
`COEFFICIENT
`UPDATES
`
`PETITIONERS EXHIBIT 1006
`Page 8 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 8 of 11
`
`5,867,065
`
`MODULATION
`SCNA, SAMPLES
`(COMPLEX)
`
`PA INPUT SICNA,
`SAIPLES
`
`
`
`PA OUTPUT SIGNAL
`SAMPLES
`
`WRITE
`ADDRESS
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`SOWER
`DIRECT
`INVERSE
`MODELER
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`2.
`
`PETITIONERS EXHIBIT 1006
`Page 9 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 9 of 11
`
`5,867,065
`
`MODULATION
`SIGNES ifies PIN
`
`PAOUT
`
`CALCULATE PARAMETERS CORRESPONDING
`T0 L00K UP TABLE ADDRESSES
`EXHIBITED BY THE DATA IN THE SAMPLE BLOCK C1321
`
`
`
`ADDRESSES
`
`PARAMETERS
`
`QUALIFY THE SOLVED PARAMETERS
`AND REJECT UNCERTAIN ONES
`
`FILL IN THE UNTRAINED
`PARAMETERS IN THE TABLE
`
`FILTER THE NEW PARAMETERS
`RELATIVE TO THE PAST PARAMETERS
`
`STORE AWERACED
`PARAMETERS IN LUT
`
`52. 75ay
`
`1323
`
`f325
`
`1327
`
`f329
`
`PETITIONERS EXHIBIT 1006
`Page 10 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 10 of 11
`
`5,867,065
`
`MODULATION
`SIGNES ifies
`
`
`
`IN
`
`PAOUT
`
`QUALIFY DATA AND CALCULATE PARAMETERS
`CORRESPONDING TO L00K UP TABLE ADDRESSES
`EXHIBITED BY THE DATA IN THE SAMPLE BLOCK C-1334
`
`ADDRESSES
`
`PARAMETERS
`
`FILL IN THE UNTRAINED
`PARAMETERS IN THE TABLE
`
`1325
`
`FILTER THE NEW PARAMETERS
`RELATIVE TO THE PAST PARAMETERS
`
`f327
`
`STORE AWERACED
`PARAMETERS IN LUT
`
`1329
`
`1400 &
`
`
`
`PETITIONERS EXHIBIT 1006
`Page 11 of 25
`
`

`

`U.S. Patent
`
`Feb. 2, 1999
`
`Sheet 11 of 11
`
`5,867,065
`
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`PETITIONERS EXHIBIT 1006
`Page 12 of 25
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`PETITIONERS EXHIBIT 1006
`Page 12 of 25
`
`

`

`5,867,065
`
`1
`FREQUENCY SELECTIVE PREDISTORTION
`IN A LINEAR TRANSMITTER
`
`RELATED APPLICATIONS
`This application is related to a co-pending application
`entitled “Method and Apparatus for Linear Transmission. By
`Straight Inverse Modeling” to Leyendecker et al., Ser. No.
`08/850.940, filed on May 5, 1997, assigned to the same
`assignee herein, and expressly incorporated in its entirety by
`reference herein.
`
`FIELD OF THE INVENTION
`The present invention relates to linear transmitters and,
`more particularly, to linear transmitters using predistortion.
`
`15
`
`2
`tion Schemes predistort the input Signal as a function of the
`power or magnitude of the Signal to be amplified. For
`example, U.S. Pat. No. 4,291,277 issued to Davis et al. and
`U.S. Pat. No. 5,049,832 issued to Cavers disclose Such a
`scheme. Thus, in this scheme, the predistorter 101 includes
`a power calculator 201 for calculating the instantaneous
`power or magnitude of the received modulation signal. The
`calculated instantaneous power or magnitude is then used to
`access a look-up table (LUT) 203 that stores a corresponding
`complex value for this particular instantaneous power or
`magnitude. This complex value approximates the local
`inverse of the transfer characteristic of the power amplifier
`for this particular instantaneous power or magnitude of the
`modulation signal. The LUT 203 can be periodically
`updated by the trainer 107 (FIG. 1) so that the complex
`values reflect any changes in the transfer characteristic of the
`power amplifier 103 (FIG. 1). The LUT 203 provides this
`complex value to a multiplier 205, which multiplies the
`modulation Signal with this complex value to predistort the
`modulation Signal. Thus, when the predistorted modulation
`Signal is Subsequently amplified by the power amplifier, the
`predistortion cancels to Some extent the distortion caused by
`the power amplifier.
`Although these conventional predistortion Schemes rep
`resent an improvement over earlier Schemes to reduce power
`amplifier distortion, the inventors of the present invention
`have observed that modeling the power amplifier transfer
`characteristic using only the instantaneous power or mag
`nitude does not completely accurately predict the distortion
`caused by the power amplifier. Consequently, predistortion
`Schemes based on Such models cannot completely correct
`the distortion caused by the power amplifier.
`FIG. 3 is a flow chart illustrative of a conventional process
`of calculating the complex values that are Stored in the LUT
`203 (FIG. 2). In a step 301, the trainer 107 (FIG. 1)
`determines the instantaneous magnitude and phase of the
`input signal to the power amplifier 103 (FIG. 1) and the
`instantaneous magnitude and phase of the amplified (and
`distorted) output signal. The trainer 107 typically stores
`these values in a LUT (not shown) within the trainer and,
`thus, can directly model the transfer characteristics of the
`power amplifier 103. In step 302, these characteristics are
`stored in a first lookup table (LUT). This first trainer LUT is
`indexed using the actual amplifier output power or magni
`tude. Then in a next step 303, the trainer 107 calculates the
`mathematical “inverse” of the transfer characteristic of the
`power amplifier. This step is generally computationally
`intensive, thereby undesirably increasing the complexity of
`the hardware and software of the trainer 107 and consuming
`processing time and power. In addition, because the trainer
`LUT is indexed by actual amplifier output power or
`magnitude, addressing errors may occur because the ampli
`fier output signal is potentially noisy. Then in a step 305, the
`trainer stores the calculated inverse in the second LUT 203
`of the predistorter 101.
`In View of the above shortcomings of conventional pre
`distortion Schemes, there is a need for a predistortion System
`that will compensate for power amplifier distortion more
`accurately than the conventional predistortion Systems that
`are based on instantaneous envelope power or magnitude.
`There is also a need for a leSS complex and more accurate
`Scheme to provide the inverse of the power amplifier transfer
`characteristic.
`SUMMARY OF THE INVENTION
`In accordance with the present invention, a System for
`linearly transmitting an amplified output Signal using pre
`
`25
`
`35
`
`40
`
`BACKGROUND OF THE INVENTION
`It is well-known that the power amplification Stages of
`typical radio frequency (RF) broadcast transmitters behave
`in a nonlinear fashion when operated near peak capacity.
`One simple solution to this problem is to “back off the
`power amplifier and only operate the power amplifier below
`Saturation in its linear region. However, backing off the
`power amplifier tends to reduce the power conversion effi
`ciency of the power amplifier. Additionally, for a given
`required transmitter output power, the power amplifier used
`must be larger (and more expensive) than a power amplifier
`that can be operated at peak capacity.
`Furthermore, although backing off would allow the power
`output of the power amplifier to behave more linearly,
`backing off would not alleviate the phase distortion of the
`power amplifier. For modulation Schemes that only depend
`upon modulation of amplitude (Such as AM), phase distor
`tion is of relatively little concern. However, for other types
`of modulation Schemes that rely upon both amplitude and
`phase modulation, phase distortion is an important concern.
`An alternative Solution, commonly referred to as
`predistortion, compensates for the distortion caused by the
`power amplifier by "predistorting the Signal to be amplified
`with the “inverse” of the transfer characteristic of the power
`amplifier. FIG. 1 is a simplified block diagram of an exem
`plary conventional predistortion Subsystem 100 for use in a
`transmitter. A predistorter 101 is coupled to receive a modu
`lation signal to be amplified by a power amplifier 103 and
`45
`broadcast through an antenna 105. The predistorter 101
`operates on the received modulation Signal to predistort the
`modulation signal with the calculated inverse of the transfer
`characteristic of the power amplifier 103. Thus, ideally, the
`“predistortion' and the power amplifier distortion cancel
`each other out to achieve a linear amplification of the output
`signal. In this example, the predistortion subsystem 100
`includes a trainer 107 to monitor the power amplifier input
`and output Signals to determine the distortion caused by the
`power amplifier 103, which may change over time. The
`trainer 107 then provides signals to update the predistorter
`101 so that predistorter 101 tracks any changes in the
`transfer characteristic of the power amplifier 103.
`FIG. 2 is a simplified block diagram of the conventional
`predistorter 101 (FIG. 1). Typical conventional predistortion
`Schemes attempt to model the performance of the power
`amplifier and calculate the “inverse” of the amplifier transfer
`characteristic. All of the predistortion Schemes known to the
`inventors of the present invention attempt to model the
`power amplifier performance as a function of the instanta
`neous power or magnitude envelope of the input signal to the
`power amplifier. Accordingly, these conventional predistor
`
`50
`
`55
`
`60
`
`65
`
`PETITIONERS EXHIBIT 1006
`Page 13 of 25
`
`

`

`3
`distortion is provided. In one embodiment adapted for use
`with digital input data, the System uses a Straight inverse
`modeling Scheme to more easily and accurately determine
`the inverse of the distortion caused by a power amplifier of
`a RF transmitter. In this embodiment, the “inverse' of the
`power amplifier is directly modeled by considering the
`power amplifier as a signal processing block with the input
`and output ports reversed. More Specifically, the output
`Signal of the power amplifier is considered the input Signal
`of the “inverse” power amplifier model and,
`correspondingly, the modulated input signal of the power
`amplifier is considered the output signal of the “inverse'
`power amplifier model. As a result, the computationally
`intensive inversion required by the conventional Schemes is
`avoided, which Serves to free up resources and reduce
`processing time and power consumption. Further, unlike the
`conventional inverse modeling Schemes, the direct inverse
`modeling Scheme of the present invention indexes the LUT
`using the modulated input signals instead of the potentially
`noisier output signals, which helps to increase the accuracy
`of the predistortion. In addition, in one embodiment, the
`predistorter System Stores complex coefficients in the LUT,
`which are then used as the tap weights of a digital filter
`implementing the predistorter.
`In accordance with other aspects of the present invention,
`the trainer uses a modified version of the power amplifier
`output signal. The modified power amplifier output Signal
`has the in-band distortion removed from the power amplifier
`output signal.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The foregoing aspects and many of the attendant advan
`tages of this invention will become more readily appreciated
`as the Same becomes better understood by reference to the
`following detailed description, when taken in conjunction
`with the accompanying drawings, wherein:
`FIG. 1 is a block diagram of a conventional predistortion
`System;
`FIG. 2 is a block diagram of a conventional predistorter
`as depicted in FIG. 1;
`FIG. 3 is a flow diagram of a conventional process to
`calculate the complex values of the predistorter depicted in
`FIG. 2;
`FIG. 4 is a block diagram of a transmitter using a
`predistortion System according to one embodiment of the
`present invention;
`FIG. 5 is a block diagram of a predistortion system
`according to one embodiment of the present invention;
`FIG. 5A and FIG. 5B are block diagrams illustrating
`direct inverse modeling according to one embodiment of the
`present invention;
`FIG. 6 is a more detailed block diagram of the predistor
`tion system depicted in FIG. 5;
`FIG. 7 is a block diagram of a predistortion filter accord
`ing to one embodiment of the present invention;
`FIG. 8 is block diagram of a predistortion filter according
`to a Second embodiment of the present invention;
`FIG. 9 is a block diagram of an envelope filter according
`to one embodiment of the present invention;
`FIG. 9A is a block diagram of an envelope filter according
`to a Second embodiment of the present invention;
`FIG. 10 is a block diagram of an envelope filter according
`to a third embodiment of the present invention;
`FIG. 10A is a block diagram of an envelope filter accord
`ing to a fourth embodiment of the present invention;
`
`4
`FIG. 11 is a functional block diagram of a look-up table
`address generator according to one embodiment of the
`present invention;
`FIGS. 12, 12A and 12B are functional block diagrams of
`a trainer according to different embodiments of the present
`invention;
`FIG. 13 is a functional block diagram of the solver
`depicted in the trainer of FIG. 12, according to one embodi
`ment of the present invention;
`FIGS. 13A and 13B are flow diagrams illustrating the
`operation of the Solver according to two embodiments of the
`present invention; and
`FIG. 14 is a block diagram of digital signal processing
`circuit for implementing a predistorter and trainer, according
`to one embodiment of the present invention; and
`FIG. 15 is a block diagram of an alternative embodiment
`of the present invention.
`
`DETAILED DESCRIPTION
`FIG. 4 is a functional block diagram of a linear transmitter
`400 using a predistortion System according to one embodi
`ment of the present invention. This embodiment of the
`transmitter is Substantially similar to the transmitter
`described in U.S. Pat. No. 5,732,333 to Cox et al., which is
`commonly assigned to the assignee of the present invention
`and incorporated herein by reference. In a preferred
`embodiment, the linear transmitter 400 is adapted for use as
`a paging transmitter in a paging System, although it can be
`used in any radio frequency (RF) application.
`The transmitter 400, in the forward signal processing
`path, includes a modulator 403, a predistorter 407, a digital
`quadrature modulator 411, a digital-to-analog converter 412,
`an analog upconverter 413, the power amplifier 103 and the
`transmitting antenna 105. A feedback loop of the transmitter
`400 includes a directional coupler 419 (between the power
`amplifier 103 and the antenna 105), an analog downcon
`verter 423, an analog-to-digital converter 424, a digital
`quadrature demodulator 425, and a trainer 431. The trainer
`431 is coupled to receive the output Signals of the digital
`modulator 403 and interact with the predistorter 407. In
`other embodiments, additional power amplifiers may be
`connected in parallel with the power amplifier 103 to
`increase the gain of the transmitter 400.
`Digital data that is to be broadcast by the transmitter 400
`is provided to the modulator 403, as represented by an arrow
`432. The digital data may be provided by any source. In the
`preferred embodiment, the digital data received by the
`modulator 403 is provided from a transmitter controller (not
`shown) of the paging System. The transmitter controller
`receives data over a link channel from a paging terminal and
`formulates the data for transmission. The details of the
`construction of a transmitter controller, and indeed an entire
`paging system, can be found in U.S. Pat. No. 5,481,258 to
`Fawcett et al., U.S. Pat. No. 5,365,569 to Witsaman et al. and
`U.S. Pat. No. 5,416,808 to Witsaman et al., commonly
`assigned to the assignee of the present invention and incor
`porated herein by reference.
`In a preferred embodiment, the data is a Series of digital
`Symbols, with each Symbol representing a predetermined
`number of bits. The number of bits per symbol is dependent
`upon the particular modulation Scheme being transmitted by
`the transmitter 400. Modulation formats in typical conven
`tional paging data Systems include, for example, two or four
`tone frequency shift keying (FSK) modulation, continuous
`phase FSK (CPFSK), 43K75B8E formal modulation (a type
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`of amplitude modulation developed by Motorola) and
`quadrature amplitude modulation (QAM). QAM formats
`include, for example, an eight level QAM Scheme that
`would have a three-bit symbol. Similarly, a sixteen level
`QAM scheme would have four bits per symbol. It will be
`appreciated that for a three-bit Symbol, there are eight
`possible symbols. Likewise, for a four-bit symbol, there are
`Sixteen possible Symbols.
`The modulator 403 correlates each particular symbol with
`predetermined in-phase and quadrature output Signals. Thus,
`for each unique symbol, a different combination of in-phase
`and quadrature component Signals for the base band Signal
`is output by the modulator. In a preferred embodiment, the
`modulator 403 includes a Texas Instruments TMS320C44
`digital signal processor (DSP) microprocessor that is pro
`grammed to perform the in-phase and quadrature modula
`tion on the symbols.
`Additionally, as each Symbol is processed, the modulator
`403 does not “instantaneously” transition from one symbol
`to another. Such an instantaneous change in in-phase and
`quadrature output Signals would result in high frequency
`harmonics in the System. Instead, by means of digital
`filtering, a Smooth transition between Symbols (and there
`fore in-phase and quadrature output signals) is achieved.
`One embodiment of this technique which is applicable to an
`FSK system is disclosed in more detail in U.S. Pat. No.
`5,418,818 to Marchetto et al., assigned to the same assignee
`as the present invention and incorporated herein by refer
`CCC.
`Next, the in-phase and quadrature component signals
`output by the modulator 403 are input into the predistorter
`407. The predistorter 407 is operative to modify the in-phase
`and quadrature component Signals output from the modula
`tor 403 so as to compensate for any distortion that takes
`place in the power amplifier 103. In accordance with the
`present invention, the predistorter uses a predistortion
`Scheme that is dependent not only on the instantaneous
`power or magnitude envelope of the Sample, but also on the
`power or magnitude envelope of the previous Samples. By
`taking into account the power or magnitude envelope of
`previous Samples, the effect of the trajectory leading to the
`current Sample's power or magnitude envelope is also
`compensated for in the predistortion of the current Sample,
`improving the linearity of the output signal from the power
`amplifier 103. This predistortion scheme is described further
`below in conjunction with FIGS. 5-13A.
`The output signals of the predistorter 407 are then pro
`vided to the digital quadrature modulator 411. The digital
`quadrature modulator 411 converts the in-phase and quadra
`ture component signals into a single real digital Signal. The
`real digital Signal from the digital quadrature modulator 411
`is received by a D-A converter 412 that converts the real
`digital Signal to an analog signal, producing an intermediate
`frequency output Signal. For example, the intermediate
`frequency is approximately 5.6 MHZ in a representative
`embodiment. Because a Single D-A converter is used, the
`distortion caused by the relative delay and amplitude dif
`ferences introduced in those conventional Systems that use
`Separate D-A for in-phase and quadrature Signals is Substan
`tially eliminated in the transmitter 400.
`The intermediate frequency output Signal from the D-A
`converter 412 is provided to the analog upconverter 413,
`which converts the intermediate frequency Signal to a broad
`cast frequency Signal having a frequency within a frequency
`band of the paging System. For example, the broadcast
`frequency is approximately 940 MHz in a representative
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`embodiment. The analog upconverter 413 can be any Suit
`able conventional upconverter Such as, for example, a mixer
`receiving a local oscillator Signal.
`The power amplifier 103 receives the broadcast frequency
`Signal from the analog upconverter 413, amplifies the Signal,
`and provides the amplified signal to the transmitting antenna
`105 for transmission. In this embodiment, the power ampli
`fier 103 is substantially similar to the power amplifier
`disclosed in U.S. Pat. No. 5,694,085 to Walker, assigned to
`the same assignee as the present invention and incorporated
`herein by reference. Of course, any Suitable power amplifier
`can be used in other embodiments.
`In order to aid in the accurate predistortion of the Signal,
`the feedback loop monitors the amplified Signal from the
`power amplifier 103. The coupler 419 is a conventional
`directional coupler positioned relatively close to the antenna
`105 and is operative to direct a relatively small portion of the
`output signal from the power amplifier 103 to the analog
`downconverter 423.
`The analog downconverter 423 operates in an opposite
`manner to the analog upconverter 413. In particular, the
`analog downconverter 423 lowers the frequency of the
`receive signal outputted by power amplifier 103 to an
`intermediate frequency. In a preferred embodiment, this
`intermediate frequency is Substantially the same as the
`intermediate frequency used in the forward Signal proceSS
`ing path. Within the analog downconverter 423, there is a
`Series of filtering, amplification, and mixing with local
`oscillator Signals processes to generate the intermediate
`frequency Signal, as described in the aforementioned U.S.
`Pat. No. 5,732,333.
`Next, the intermediate frequency signal is converted from
`an analog intermediate frequency Signal into a digital Signal.
`This is accomplished by using a conventional A-D converter
`424 such as, for example, an Analog Devices AD9026,
`which Samples the intermediate frequency signal and
`outputs, a digital Signal representing the Sampled interme
`diate frequency Signal. The digital quadrature demodulator
`425 performs a digital quadrature demodulation of the
`digital Signals and outputs the in-phase component Signal
`and the quadrature component Signal.
`The trainer 431 receives the output signals of the digital
`quadrature demodulator 425. The trainer 431 also periodi
`cally receives the output signals from the modulator 403 and
`the predistorter 407, as described below in conjunction with
`FIG. 6. Thus, ideally, the trainer 431 receives the equivalent
`of the exact modulated Signal that was intended to be sent
`(the output signals of the modulator 403) and the signal that
`was actually transmitted (the output signals of the digital
`quadrature demodulator 425). This scheme enables the pre
`distorter 407 to associate the distorted output sample to its
`corresponding input Sample So that the predistorter 407 can
`more accurately compensate for the distortion caused by the
`power amplifier 103. Typically, the trainer provides one or
`more “trainer' Signals to the predistorter to update the
`predistorter's response to the in-phase and quadrature Sig
`nals input to the predistorter as the power amplifiers
`response changes due to temperature, age, etc.
`In addition, the trainer monitors the actual data or voice
`Signals being transmitted to implement the predistortion
`Scheme, as opposed to special sequences (i.e., not normal
`data or voice signals) as required by Some conventional
`Systems. Thus, normal data or voice transmissions need not
`be interrupted to transmit Special data Sequences to update
`the predistorter as in these conventional Systems.
`In a further refinement, the transmitter 400 may include
`digital interpolators 405 and 409, and a digital decimator
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`429. The digital interpolator 405 is connected between the
`modulator 403 and the predistorter 407, the digital interpo
`lator 409 is connected between the predistorter 407 and the
`digital quadrature modulator 411, and the digital decimator
`429 is connected between the digital quadrature demodula
`tor 425 and the trainer 431. This circuitry provides further
`upconversion in the forward Signal processing path and
`corresponding downconversion in the feedback path.
`In addition, the transmitter 400 includes a synthesizer 435
`connected to the analog upconverter 413 and the analog
`downconverter 423, a phase locked loop (PLL) 437 con
`nected to the digital quadrature modulator 411. An ovenized
`reference oscillator 433 is connected to both the synthesizer
`435 and the PLL 437. This timing circuitry ensures that the
`modulation, upconversion, downconversion and demodula
`tion are accurately Synchronized.
`In this embodiment, the output signals of the modulator
`403 are the in-phase and quadrature component signals
`sampled at 80,000 samples per second (80 ksps). The
`in-phase and quadrature component Signals output by the
`modulator 403 are received by the digital interpolator 405.
`The digital interpolator 405 operates to increase the effective
`Sampling rate of the received signals by means of digital
`interpolation. In a preferred embodiment, the digital inter
`polator 405 outputs the in-phase and quadrature component
`Signals at a rate of approximately 800 kSps and is imple
`mented with a DSP module having a TMS320C44 DSP
`microprocessor and associated memory, as described below
`in conjunction with FIG. 14.
`The signals output by the interpolator 405 are received by
`the predistorter 407. The predistorter 407, as previously
`described, predistorts the received in-phase and quadrature
`component signals to compensate for the distortion of the
`power amplifier 103. The predistorted 800 ksps component
`signals from the predistorter 407 are received by the digital
`interpolator 409. The digital interpolator 409 operates in a
`fashion similar to the interpolator 405 to increase the effec
`tive Sampling rate. Specifically, both the in-phase and
`quadrature component Signals are first upconverted in a first
`step by a factor of two. Thus, after this first conversion, the
`effective sampling rate of the component Signals is approxi
`mately 1.6 Msps. The Signals are then upconverted by
`another factor of two, resulting in an effective rate of
`approximately 3.2 Msps. Next, these two 3.2 Msps signals
`are passed to a further interpolator which upconverts them
`by a factor of seven to approximately 22.4 Msps. Thus, the
`output Signals of the digital interpolator 409 are in-phase and
`quadrature component signals that have been Sampled at
`22.4 Msps. The interpolation Stages include digital filtering
`of the base band Signals. The implementation of the digital
`interpolator 409 is described in more detail in the aforemen
`tioned U.S. Pat. No. 5,732.333.
`The digital quadrature modulator 411 receives the output
`signals of the digital interpolator 409 and modulates them as
`previously described using a digital quadrature modulation
`Scheme. In this embodiment, the digital quadrature modu
`lator 411 uses a digital equivalent of a conventional double
`balanced modulation scheme in conjunction with a 5.6