Digital Predistortion of Power Amplifiers
`
`for Wireless Applications
`
`A Thesis
`Presented to
`The Academic Faculty
`
`by
`
`Lei Ding
`
`In Partial Fulfillment
`of the Requirements for the Degree
`Doctor of Philosophy
`
`School of Electrical and Computer Engineering
`Georgia Institute of Technology
`March 2004
`
`PETITIONERS EXHIBIT 1009
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`Digital Predistortion of Power Amplifiers
`
`for Wireless Applications
`
`Approved by:
`
`Dr. G. Tong Zhou, Advisor
`
`Dr. Ye (Geoffrey) Li
`
`Dr. J. Stevenson Kenney
`
`Dr. Jianmin Qu
`
`Dr. W. Marshall Leach
`
`Date Approved: April 1, 2004
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`For my family.
`For my family.
`
`iii
`iii
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`ACKNOWLEDGEMENTS
`
`It is time to draw a period to my PhD endeavor. I feel extremely lucky to meet so many
`
`talented people during these years. I am grateful for their friendship, help, encouragement,
`
`and support.
`
`First, I would like to thank my advisor, Dr. G. Tong Zhou, for providing this opportunity
`
`for me to study at Georgia Tech. Her constant encouragement and valuable advices are
`
`essential for the completion of this thesis. I will be always inspired by the high standards
`
`she sets for herself and her sharp focus and deep devotion to whatever she works on.
`
`I would like to thank my thesis committee members: Drs. J. Stevenson Kenney, W.
`
`Marshall Leach, Ye (Geoffrey) Li, and Jianmin Qu for taking time to serve on my committee
`
`and for their questions and suggestions. My special thanks also go to Drs. Monson Hayes
`
`and Douglas B. Williams for the excellent classes they offered, which benefit me a lot for
`
`my research work and job search.
`
`I also benefit a lot from my two summer internships at Bell Labs, Lucent Technologies.
`
`I would like to thank Drs. Zhengxiang Ma and Dennis R. Morgan for making this possible.
`
`I enjoyed every aspect of my internship experience: talented colleagues, excellent research
`
`opportunities, cool weather, nice work environment, and the list goes on. My special thanks
`
`also go to Dr. Yiteng Huang for his friendship and help during my stay in New Jersey.
`
`I would like to thank my group members: Yongsub, Krishna, Muhammad, Raviv, Gail,
`
`Ning, Hua, Chunpeng, Yuan, Thao, Vincent, and Bob for all the technical discussions and
`
`help along the way. I also enjoyed interactions with the nice Chinese student community
`
`here at CSIP.
`
`A lot of credit goes to my parents. Their unconditional support has always helped me
`
`in all my endeavors. I would also like to thank my sister for her support and feeding me
`
`with great dishes from time to time. Last but not least, I would like to thank my wife,
`
`wenjin, for her love, encouragement, and support.
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`TABLE OF CONTENTS
`
`Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`iii
`
`iv
`
`List of Tables
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
`
`List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`ix
`
`Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
`
`Chapter 1
`
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1.2 Objectives
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Chapter 2
`
`Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`2.1 Modeling Memoryless Power Amplifiers . . . . . . . . . . . . . . . . .
`
`2.2 Predistortion of Memoryless Power Amplifier . . . . . . . . . . . . . .
`
`2.2.1 Data Predistortion for Memoryless Power Amplifiers
`
`. . . . .
`
`2.2.2
`
`Signal Predistortion for Memoryless Power Amplifiers . . . . .
`
`2.3 Modeling Power Amplifiers with Memory Effects . . . . . . . . . . . .
`
`2.4 Predistortion of Power Amplifiers with Memory Effects . . . . . . . .
`
`1
`
`1
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`3
`
`3
`
`5
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`5
`
`7
`
`7
`
`8
`
`10
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`14
`
`Chapter 3
`
`Digital Predistorter Design . . . . . . . . . . . . . . . . . . . . .
`
`17
`
`3.1 Hammerstein Predistorter Design . . . . . . . . . . . . . . . . . . . .
`
`3.1.1 Hammerstein Predistorter Training . . . . . . . . . . . . . . .
`
`3.1.2 Hammerstein Predistorter Simulation . . . . . . . . . . . . . .
`
`3.2 Memory Polynomial Predistorter Design . . . . . . . . . . . . . . . .
`
`3.2.1 Memory Polynomial Predistorter Training . . . . . . . . . . .
`
`3.2.2 Memory Polynomial Predistorter Simulation . . . . . . . . . .
`
`3.2.3 Memory Polynomial Predistorter Discussion . . . . . . . . . .
`
`3.3 A New Combined Predistorter Design . . . . . . . . . . . . . . . . . .
`
`3.3.1 Combined Predistorter Model
`
`. . . . . . . . . . . . . . . . . .
`
`3.3.2 Combined Predistorter Training . . . . . . . . . . . . . . . . .
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`3.3.3 Effects of Noise and Initial Estimates . . . . . . . . . . . . . .
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`17
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`17
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`22
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`25
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`25
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`26
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`33
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`35
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`36
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`37
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`40
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`3.3.4 Combined Predistorter Performance . . . . . . . . . . . . . . .
`
`45
`
`Chapter 4
`
`Effects of Even-order Nonlinear Terms . . . . . . . . . . . . . .
`
`47
`
`4.1 Passband and Baseband Nonlinearities
`
`. . . . . . . . . . . . . . . . .
`
`4.1.1 Memoryless Case
`
`. . . . . . . . . . . . . . . . . . . . . . . . .
`
`4.1.2 Quasi-memoryless Case . . . . . . . . . . . . . . . . . . . . . .
`
`4.2 Even-Order Terms in the Baseband Power Amplifier Model . . . . . .
`
`4.3 Even-Order Terms in the Baseband Predistorter Model
`
`. . . . . . . .
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`4.4 Extensions to Power Amplifiers and Predistorters with Memory . . .
`
`47
`
`47
`
`48
`
`50
`
`53
`
`58
`
`Chapter 5
`
`Analog Imperfection Compensation . . . . . . . . . . . . . . . .
`
`61
`
`5.1 Two-Stage Upconversion Transmitter . . . . . . . . . . . . . . . . . .
`
`5.1.1
`
`System Setup . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`5.1.2 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . .
`
`5.1.3 Equalizer Design . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`5.1.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . .
`
`5.2 Direct Upconversion Transmitter . . . . . . . . . . . . . . . . . . . . .
`
`5.2.1 Channel Models . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`5.2.2 Channel Estimation . . . . . . . . . . . . . . . . . . . . . . . .
`
`5.2.3 Compensator Construction . . . . . . . . . . . . . . . . . . . .
`
`5.2.4
`
`Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`61
`
`61
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`62
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`65
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`67
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`71
`
`72
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`76
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`79
`
`84
`
`Chapter 6
`
`Real-time Implementations . . . . . . . . . . . . . . . . . . . . .
`
`87
`
`6.1 Memory Polynomial Model . . . . . . . . . . . . . . . . . . . . . . . .
`
`6.2
`
`Indirect Learning Architecture . . . . . . . . . . . . . . . . . . . . . .
`
`6.3 Predistorter Construction . . . . . . . . . . . . . . . . . . . . . . . . .
`
`6.4 DSP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`6.4.1
`
`Implementation Details . . . . . . . . . . . . . . . . . . . . . .
`
`6.4.2 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . .
`
`6.5 Testbed Measurements
`
`. . . . . . . . . . . . . . . . . . . . . . . . . .
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`87
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`88
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`88
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`91
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`91
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`92
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`92
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`Chapter 7
`
`Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`98
`
`7.1 Contributions
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`7.2 Suggestions for Future Research . . . . . . . . . . . . . . . . . . . . .
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`98
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`99
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`References. 2...0. ee 100
`References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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`LIST OF TABLES
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`52
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`55
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`58
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`84
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`94
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`Table 1
`
`Table 2
`
`Table 3
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`NMSE for F (|z(t)|)
`NMSE for G(|x(t)|)
`NMSE when the power amplifier is modeled by memory polynomial. . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Table 4
`
`Ideal Model Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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`Table 5
`
`Real-time performance of the predistorter training algorithm. . . . . . . .
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`LIST OF FIGURES
`
`Figure 1 Digital Predistortion System Diagram . . . . . . . . . . . . . . . . . . . .
`
`Figure 2 The AM/AM and AM/PM responses of a Class AB power amplifier. . . .
`
`Figure 3 Block diagram of a data predistortion system with the pulse shaping filter
`implemented after the power amplifier.
`. . . . . . . . . . . . . . . . . . .
`
`Figure 4 Block diagram of a data predistortion system with the pulse shaping filter
`placed in the baseband after the predistorter. . . . . . . . . . . . . . . . .
`
`Figure 5 Block diagram of a signal predistortion system. . . . . . . . . . . . . . . .
`
`Figure 6 The Wiener Model.
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 7 The Hammerstein Model.
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 8 The Wiener-Hammerstein model. . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 9 The indirect learning architecture for the predistorter. . . . . . . . . . . .
`
`Figure 10 The indirect learning architecture for the Hammerstein predistorter. . . .
`
`Figure 11 Comparison of the PSDs for the pole/zero Wiener power amplifier and the
`pole/zero Hammerstein predistorter.
`(a) Output without predistortion;
`(b) Output with memoryless predistortion; (c) Output with Hammerstein
`predistortion, NG and LS/SVD algorithms (similar performance).
`. . . .
`
`Figure 12 Comparison of the PSDs for FIR Wiener power amplifier and 15-tap FIR
`Hammerstein predistorter. (a) Output without predistortion; (b) Output
`with memoryless predistortion; (c) Output with Hammerstein predistor-
`tion (NG); (d) Output with Hammerstein predistortion (LS/SVD).
`. . .
`
`Figure 13 Comparison of the PSDs for full Volterra power amplifier and 15-tap FIR
`Hammerstein predistorter. (a) Output without predistortion; (b) Output
`with memoryless predistortion; (c) Output with Hammerstein predistor-
`tion (NG); (d) Output with Hammerstein predistortion (LS/SVD); (e)
`Input signal.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 14 The indirect learning architecture for the memory polynomial predistorter.
`
`Figure 15 Wiener-Hammerstein model diagram.
`
`. . . . . . . . . . . . . . . . . . . .
`
`Figure 16 Effectiveness of predistortion in suppressing spectral regrowth when the
`power amplifier is modeled by a Wiener-Hammerstein system. (a) Output
`without predistortion; (b) Output with memoryless predistortion; (c) Out-
`put with memory polynomial predistortion (Q = 2, K = 5) (d) Original
`input. (c) and (d) almost coincide. . . . . . . . . . . . . . . . . . . . . . .
`
`2
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`6
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`7
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`8
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`9
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`12
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`12
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`12
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`15
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`18
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`23
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`24
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`24
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`26
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`Figure 17 Effectiveness of predistortion in suppressing spectral regrowth, when the
`power amplifier itself is modeled by a memory polynomial. (a) Output
`without predistortion; (b) Output with memoryless predistortion; (c) Out-
`put with memory polynomial predistortion (Q = 2, K = 5, odd order); (d)
`Output with memory polynomial predistortion (Q = 2, K = 5, even and
`odd orders); (e) Original input. . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 18 Effectiveness of predistortion in suppressing spectral regrowth, when the
`power amplifier is modeled by a perturbed Wiener (hence Volterra) system.
`(a) Output without predistortion; (b) Output with memoryless predistor-
`tion; (c) Output with memory polynomial predistortion (Q = 2, K = 5);
`(d) Output with memory polynomial predistortion (Q = 10, K = 5); (e)
`Original input.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 19 Parallel Wiener model diagram. Hi(·) is an LTI block, and Fi(·) is a
`memoryless nonlinear block.
`. . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 20 Effectiveness of predistortion in suppressing spectral regrowth, when the
`power amplifier is modeled by a parallel Wiener system. (a) Output with-
`out predistortion; (b) Output with memoryless predistortion; (c) Output
`with memory polynomial predistortion (Q = 2, K = 5); (d) Output with
`memory polynomial predistortion (Q = 5, K = 5); (e) Original input.
`. .
`
`29
`
`29
`
`32
`
`32
`
`Figure 21 Parallel Hammerstein model diagram. Fi(·) is a memoryless nonlinear
`. . . . . . . . . . . . . . . . . . . . . . .
`block, and Hi(·) is an LTI block.
`Figure 22 The indirect learning architecture of the new combined predistorter model. 37
`
`34
`
`Figure 23 Block diagram of the predistorter model simulation.
`
`. . . . . . . . . . . .
`
`41
`
`Figure 24 Trajectories of (a) mean squared error, (b) cl coefficients, (c) amplitudes
`of akp coefficients, and (d) amplitudes of bq coefficients vs. number of
`iterations in the noiseless setting. . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 25 Trajectories of (a) mean squared error, (b) cl coefficients, (c) amplitudes
`of akp coefficients, and (d) amplitudes of bq coefficients vs. number of
`iterations in the noisy setting.
`. . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 26 Comparison of the power spectrum of the noiseless predistorter model out-
`put z0(n) with the power spectra of noiseless residue e0(n) in noiseless and
`noisy settings.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 27 Comparison of the power spectrum of the noiseless predistorter model out-
`put z0(n) with the power spectra of noiseless residue e0(n) for different
`initialization c’s in the noisy setting. . . . . . . . . . . . . . . . . . . . . .
`
`Figure 28 Overall system performance of the least-squares/Newton algorithm on the
`predistortion testbed, showing the power spectra of the output signal (a)
`without predistortion, (b) with predistorter (m = [7 4 0 0]), (c) with
`predistorter (m = [7 4 7 3]), and (d) with predistorter (m = [7 4 7 35]).
`
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`Figure 29 Fitting F (|z(t)|) using polynomials of different orders. (a) and (b) show
`the real and imaginary parts of the measured F (|z(t)|) and its polynomial
`approximations ˆF (|z(t)|). (c) and (d) show the real and imaginary parts of
`the fitting error ˆF (|z(t)|)− F (|z(t)|). In all figures, LUT refers to the mea-
`sured power amplifier data, and the polynomial order sets K1 = {1, 3, 5},
`. . . . . . . . . . . . . . . .
`K2 = {1, 3, 5, 7, 9}, K3 = {1, 2, 3, 4, 5}.
`Figure 30 The predistorter precedes the power amplifier, and the objective is to have
`y(t) ≈ Cx(t), where C is a constant. . . . . . . . . . . . . . . . . . . . . .
`Figure 31 The errors ˆG(|x(t)|) − G(|x(t)|) for three sets of polynomial orders L1 =
`{1, 3, 5, 7}, L2 = {1, 3, 5, 7, 9, 11, 13}, and L3 = {1, 2, 3, 4, 5, 6, 7}.
`The real part of the error is shown in Figure (a), and the imaginary part of
`the error is shown in Figure (b). L2 and L3 resulted in comparable amount
`of error and both outperform L1. . . . . . . . . . . . . . . . . . . . . . . .
`Figure 32 Predistortion linearization performance in terms of spectral regrowth sup-
`pression. power amplifier output power spectral density (PSD) is shown for
`the following cases: (a) there is no predistorter; (b) predistorter (119) with
`L1 = {1, 3, 5, 7} is used; (c) predistorter (119) with L2 = {1, 3, 5, 7, 9, 11, 13}
`or predistorter (119) with L3 = {1, 2, 3, 4, 5, 6, 7} is used (the two lines
`coincide). (d) PSD of the original input. . . . . . . . . . . . . . . . . . . .
`57
`
`52
`
`53
`
`56
`
`Figure 33 Predistortion linearization performance in terms of spectral regrowth sup-
`pression. Power amplifier output power spectral density (PSD) is shown
`for the following cases: (a) there is no predistorter; (b) predistorter (123)
`with L1 = {1, 3, 5, 7} and Q = 4 is used; (c) predistorter (123) with
`L2 = {1, 3, 5, 7, 9, 11, 13} and Q = 4 is used; (d) predistorter (123)
`with L3 = {1, 2, 3, 4, 5, 6, 7} and Q = 4 is used. (e) PSD of the original
`input.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 34 Two-stage upconversion transmitter. . . . . . . . . . . . . . . . . . . . . .
`
`Figure 35 Block diagram of the baseband predistortion system with equalization.
`The dashed lines refer to the feedback path for equalizer training.
`. . . .
`
`Figure 36 Comparison between noncausal system response H(ejω) (solid line) and
`causal system response Hc(ejω) (dotted-line). Note that the mean slopes
`of the phase responses have been removed. The phase responses of H(ejω)
`and Hc(ejω) coincide.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 37 Block diagram of the test bed.
`
`. . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 38 Example of a training signal from predistorted waveform with the equalizer
`turned off.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 39 Magnitude and phase responses of the estimated channel (solid line), the
`equalizer (dotted line), and the overall cascade of the channel and the
`equalizer (dashed line). The estimated channel has 51 taps. The equalizer
`has 14 taps and is designed with ωp= 0.7π, w = 10−3.
`. . . . . . . . . .
`
`60
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`62
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`Figure 40 Comparison of power spectral densities (PSDs). (a) Training signal; (b)
`Power Amplifier output with predistortion but no equalizer; (c) PA output
`with predistortion and equalizer; (d) PA output with the same predistorter
`as in (c) but no equalizer.
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 41 Block diagram of the baseband predistortion system. The dashed lines
`refer to the feedback loop for I/Q compensator training. . . . . . . . . . .
`
`Figure 42 Detailed block diagram of the path from the DAC input x(n) to the base-
`band feedback data samples y(n).
`. . . . . . . . . . . . . . . . . . . . . .
`
`Figure 43 Block diagrams of three channel models: (a) real I/Q model; (b) complex
`I/Q model; (c) direct/image model.
`. . . . . . . . . . . . . . . . . . . . .
`
`Figure 44 Cascade of the I/Q compensator and the channel.
`
`. . . . . . . . . . . . .
`
`Figure 45 Comparison of the direct upconverter outputs without I/Q compensation
`and with different I/Q compensators. (a) Without I/Q compensation; (b)
`With a 1-tap I/Q compensator; (c) With a 9/9 I/Q compensator con-
`structed using the two-step approach; (d) With a 9-tap I/Q compensator
`constructed using the one-step approach; (e) Original input. Here, (c), (d),
`and (e) coincide.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 46 Comparison of the power amplifier output with different I/Q compensators
`and predistorters. (a) Without predistortion but with a 9-tap I/Q com-
`pensation from the one-step approach; (b) With predistortion and a 1-tap
`I/Q compensator; (c) With predistortion and a 9/9 I/Q compensator from
`the two-step approach; (d) With predistortion and a 9-tap I/Q compen-
`sator from the one-step approach; (e) Original input. Here, (c), (d), and
`(e) almost coincide.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 47 The indirect learning architecture for the predistorter. . . . . . . . . . . .
`
`Figure 48 Condition number of the correlation matrix with different Q values and dif-
`ferent input signals: (a) three-carrier WCDMA with K = 5 conventional
`polynomials; (b) three-carrier WCDMA with K = 5 orthogonal polynomi-
`als; (c) a complex random signal (amplitude uniformly distributed in [0,1])
`with K = 5 conventional polynomials; (d) a complex random signal (am-
`plitude uniformly distributed in [0,1]) with K = 5 orthogonal polynomials.
`
`Figure 49 Flow chart of the algorithm.
`
`. . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 50 Block diagram of the testbed. . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 51 Measured power amplifier output PSD: (a) without predistortion; (b) with
`K = 5 memoryless predistorter trained by 5,000 data samples; (c) with
`K = 5 memoryless predistorter trained by 20,000 data samples. (b) and
`(c) coincide.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Figure 52 Measured power amplifier output PSD: (a) without predistortion; (b) with
`K = 5, Q = 4 memory polynomial predistorter trained by 5,000 data
`samples; (c) with K = 5, Q = 4 memory polynomial predistorter trained
`by 20,000 data samples.
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`70
`
`73
`
`73
`
`74
`
`79
`
`85
`
`86
`
`88
`
`91
`
`93
`
`94
`
`96
`
`97
`
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`

`SUMMARY
`
`Power amplifiers are essential components in communication systems and are inher-
`
`ently nonlinear. The nonlinearity creates spectral growth (broadening) beyond the signal
`
`bandwidth, which interferes with adjacent channels. It also causes distortions within the
`
`signal bandwidth, which decreases the bit error rate at the receiver. Newer transmission
`
`formats, such as wideband code division multiple access (WCDMA) or orthogonal frequency
`
`division multiplexing (OFDM), are especially vulnerable to the nonlinear distortions due to
`
`their high peak-to-average power ratios (PAPRs). If we simply back-off the input signal to
`
`achieve the linearity required for the power amplifier, the power amplifier efficiency will be
`
`very low for high PAPR signals.
`
`Another choice is to linearize a nonlinear power amplifier so that overall we have a
`
`linear and reasonably efficient device. Digital predistortion is one of the most cost effective
`
`ways among all linearization techniques. However, most of the existing designs treat the
`
`power amplifier as a memoryless device. For wideband or high power applications, the
`
`power amplifier exhibits memory effects, for which memoryless predistorters can achieve
`
`only limited linearization performance.
`
`In this dissertation, we propose novel predistorters and their parameter extraction al-
`
`gorithms. We investigate a Hammerstein predistorter, a memory polynomial predistorter,
`
`and a new combined model based predistorter. The Hammerstein predistorter is designed
`
`specifically for power amplifiers that can be modeled as a Wiener system. The memory
`
`polynomial predistorter can correct both the nonlinear distortions and the linear frequency
`
`response that may exist in the power amplifier. It is a robust predistorter, which has demon-
`
`strated good performance on several nonlinear system models. Real-time implementation
`
`aspects of the memory polynomial predistorter are also investigated in the dissertation.
`
`The new combined model includes the memory polynomial model and the Murray Hill
`
`model, thus extending the predistorter’s ability to compensate for strong memory effects in
`
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`

`

`the power amplifier. Performance of the new model is demonstrated through experimental
`
`measurements.
`
`The predistorter models considered in this dissertation include both even- and odd-
`
`order nonlinear terms.
`
`In the literature, most of the power amplifier and predistorter
`
`models consider only the odd-order terms. Here, we show that it is beneficial to include
`
`even-order nonlinear terms in both the baseband power amplifier and predistorter models.
`
`By including these even-order nonlinear terms, we have a richer basis set, which offers
`
`appreciable improvement.
`
`The ideal performance of digital predistortion certainly relies on robust predistorters
`
`that can completely compensate for the nonlinearities of the power amplifier. In reality,
`
`however, the performance can also be affected by the analog imperfections in the transmit-
`
`ter, which are introduced by the analog components; mostly analog filters and quadrature
`
`modulators. There are two common configurations for the upconversion chain in the trans-
`
`mitter: two-stage upconversion and direct upconversion. For a two-stage upconversion
`
`transmitter, we design a band-limited equalizer to compensate for the frequency response
`
`of the surface acoustic wave (SAW) filter which is usually employed in the IF stage. For a
`
`direct upconversion transmitter, we develop a model to describe the frequency-dependent
`
`gain/phase imbalance and dc offset. We then develop two methods to construct compen-
`
`sators for the imbalance and dc offset. These compensation techniques help to correct for
`
`the analog imperfections, which in turn improve the overall predistortion performance.
`
`xiv
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`

`

`CHAPTER 1
`
`INTRODUCTION
`
`1.1 Motivation
`
`Power amplifiers are indispensable components in a communication system and are inher-
`
`ently nonlinear. The nonlinearity generates spectral regrowth, which leads to adjacent
`
`channel interference and violations of the out-of-band emission requirements mandated by
`
`regulatory bodies. It also causes in-band distortion, which degrades the bit error rate (BER)
`
`performance.
`
`To reduce the nonlinearity, the power amplifier can be backed off to operate within
`
`the linear portion of its operating curve. However, newer transmission formats, such as
`
`wideband code division multiple access (WCDMA) and orthogonal frequency division mul-
`
`tiplexing (OFDM), have high peak to average power ratios, i.e., large fluctuations in their
`
`signal envelopes. This means that the power amplifier needs to be backed off far from its
`
`saturation point, which results in very low efficiencies, typically less than 10% [50]; i.e.,
`
`more than 90% of the dc power is lost and turns into heat. Considering the large num-
`
`ber of wireless base stations deployed worldwide, improved power amplifier efficiency can
`
`substantially reduce the electricity and cooling costs incurred to the service providers. To
`
`improve the power amplifier efficiency without compromising its linearity, power amplifier
`
`linearization is essential.
`
`Among all linearization techniques, digital predistortion is one of the most cost effective
`
`(see Fig. 1). It adds a digital predistorter in the baseband to create an expanding nonlinear-
`
`ity that is complementary to the compressing characteristic of the power amplifier. Ideally,
`
`the cascade of the predistorter and the power amplifier becomes linear and the original
`
`input is amplified by a constant gain. With the predistorter, the power amplifier can be
`
`utilized up to its saturation point while still maintaining a good linearity, thereby signif-
`
`icantly increasing its efficiency. In reality, the power amplifier characteristics may change
`
`1
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`PETITIONERS EXHIBIT 1009
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`

`

`x(n)
`
`Predistortion
`
`z(n)
`
`D/A
`
`Up
`Converter
`
`PA
`
`Predistorter
`Construction
`
`y(n)/G
`
`A/D
`
`Down
`Converter
`
`Figure 1: Digital Predistortion System Diagram
`
`over time because of temperature drift, component aging, etc. Therefore, the predistorter
`
`should also have the ability to adapt to these changes.
`
`Digital predistortion implementations in the current literature mostly focus on the power
`
`amplifier that has a memoryless nonlinearity; i.e., the current output depends only on the
`
`current input through a nonlinear mechanism. This instantaneous nonlinearity is usually
`
`characterized by the AM/AM and AM/PM responses of the power amplifier, where the
`
`output signal amplitude and phase deviation of the power amplifier output are given as
`
`functions of the amplitude of its current input. There has been intensive research on pre-
`
`distortion techniques for memoryless power amplifiers during the past decade [28].
`
`As the signal bandwidth gets wider, such as in WCDMA, power amplifiers begin to
`
`exhibit memory effects. This is especially true for those high power amplifiers used in
`
`wireless base stations. The causes of the memory effects can be attributed to thermal
`
`constants of the active devices or components in the biasing network that have frequency-
`
`dependent behaviors [47]. As a result, the current output of the power amplifier depends
`
`not only on the current input, but also on past input values. In other words, the power
`
`amplifier becomes a nonlinear system with memory. For such a power amplifier, memoryless
`
`predistortion can achieve only very limited linearization performance [29], [17]. Therefore,
`
`digital predistorters also need to have memory structures. This dissertation investigates
`
`robust predistorter models that are capable of linearizing power amplifiers with memory
`
`effects. It also investigates system implementation issues related to these wideband digital
`
`predistortion systems.
`
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`

`

`1.2 Objectives
`
`The objective of this dissertation is to develop digital predistortion systems for linearization
`
`of power amplifiers with memory effects. Our research efforts focus on three areas:
`
`• Predistorter models with memory structures;
`
`• Digital compensation techniques of analog imperfections in the transmitters;
`
`• Wideband digital predistortion testbed.
`
`Volterra series is a general nonlinear model with memory. However, the large number of
`
`coefficients in the Volterra series makes it unattractive for practical applications. Instead,
`
`several special cases of the Volterra series are considered in this dissertation, which include
`
`the Hammerstein model [25], the memory polynomial model [30], the Murray Hill model
`
`[32], and possible combinations of these models.
`
`The ideal performance of digital predistortion certainly relies on robust predistorters
`
`that can completely compensate for the nonlinearities in the power amplifier. In reality,
`
`however, the performance can also be affected by the analog imperfections in the trans-
`
`mitter, which are introduced by the analog components, such as mixers, analog filters, and
`
`quadrature modulators. The second focus of this dissertation is to investigate modeling and
`
`compensation techniques for these imperfections.
`
`In this dissertation, a wideband digital predistortion testbed is also developed to evaluate
`
`the performance of digital predistortion systems on real power amplifiers.
`
`1.3 Outline
`
`The dissertation is organized as follows:
`
`Chapter 2 reviews the literature in the field of modeling and predistortion of power
`
`amplifiers. A memoryless power amplifier can be characterized by its AM/AM and AM/PM
`
`responses. To linearize such a power amplifier, a memoryless predistorter is sufficient. For a
`
`power amplifier with memory effects, various models are available to capture the behavior of
`
`the power amplifier, which include the Volterra series, the Wiener model, the Hammerstein
`
`3
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`PETITIONERS EXHIBIT 1009
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`

`

`model, and the Wiener-Hammerstein model. The indirect learning architecture is then
`
`presented to construct the predistorter for a power amplifier with memory effects.
`
`In Chapter 3, we present novel predistorters and their parameter extraction algorithms.
`
`A Hammerstein predistorter, a memory polynomial predistorter, and a new combined model
`
`based predistorter are considered. The parameters of these predistorters are extracted using
`
`the indirect learning architecture, eliminating the need for model assumption and parameter
`
`extraction of the power amplifier. Performance of these predistorters are demonstrated
`
`through computer simulations and/or experimental measurements.
`
`Most existing literature considers only odd-order nonlinear terms when modeling power
`
`amplifiers and designing predistorters in the baseband. We show in Chapter 4 that it is
`
`beneficial to include even-order nonlinear terms in the baseband PA as well as predistorter
`
`models. By including these even-order nonlinear terms, we have a richer basis set, which
`
`offers appreciable improvement.
`
`In Chapter 5, we study the analog imperfections in the transmitter and design com-
`
`pensation techniques. For a two-stage upconversion transmitter, we design a band-limited
`
`equalizer to compensate for the frequency response of the SAW filter, which is usually
`
`employed in the IF stage. For a direct upconversion transmitter, we develop a model to
`
`describe the frequency-dependent gain/phase imbalance and dc offset. We then develop two
`
`methods to construct compensators for the imbalance and dc offset. These compensation
`
`techniques help to correct for the analog imperfections, which in turn improve the overall
`
`predistortion performance.
`
`In a practical implementation, predistorter training is performed on a digital signal
`
`processor, such as the Texas Instruments TMS320C6711.
`
`In Chapter 6, we investigate
`
`real-time implementation aspects of the memory polynomial predistorter. We implement
`
`the predistorter training algorithm on a Texas Instruments TMS320C6711 processor and
`
`evaluate the performance of the trained predistorter on our wideband digital predistortion
`
`testbed.
`
`Finally, Chapter 7 concludes the dissertation and provides future research directions.
`
`4
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`PETITIONERS EXHIBIT 1009
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`

`

`CHAPTER 2
`
`BACKGROUND
`
`In this chap