CERL REPORT X- 20
`
`APRIL,1971
`
`REVISED MAY,I972
`
`THE PLATO IV ARCHITECTURE
`
`JACK STI FLE
`
`Computer - based Educat ion Resea rch Laboratory
`
`University of Illinois
`
`Urbana
`
`Illinois
`
`Page 1 of 24
`
`Instacart, Ex. 1032
`
`
`
`APRIL,1971
`
`REVISED MAY,I972
`
`THE PLATO IV ARCHITECTURE
`
`JACK STI FLE
`
`Computer - based Educat ion Resea rch Laboratory
`
`University of Illinois
`
`Urbana
`
`Illinois
`
`Page 1 of 24
`
`Instacart, Ex. 1032
`
`
`
`
`
`Page 2 of 24
`
`
`
`This york yas supported by the National Science Foundation under
`
`Contract NSF GJ 81 and NS~ GJ 947 .
`
`PLATO has been supported by the Advanced Research Projects Agency
`
`through the Office of Naval Research under Contract Nonr 3985( 08) , in
`
`part by the Joint Services Electronics Program (U . S . Army , U. S . Navy ,
`
`and U.S . Air Force) , i n part by the Publ i c Health Service , Division
`
`of Nursing of the U. S. Department of Health , Education and Welfare under
`
`Contract NPG- 188- 01 , and in part by the U. S. Office of Education under
`
`Contract OE- 6- 10-l84 .
`
`Reproduction in wh ole or in part is permitted for any purpose of t he
`
`United States Government .
`
`Distribution of this report is unlimited .
`
`-,
`
`l
`
`I ,
`
`, I
`
`I
`U
`L
`L
`l
`L
`I \
`
`Page 3 of 24
`
`
`
`I I I .
`Il
`II
`II
`, I
`
`: I
`I I
`I I
`
`I I
`
`I I I.
`II
`II
`I I
`
`II
`I I I J
`II
`II
`I I
`II
`'II
`
`Page 4 of 24
`
`Page 4 of 24
`
`
`
`ii
`
`A project of the size of PLATO IV necessarily re~uires the talents
`
`of many people only a few of whom are mentioned here .
`
`Paul Tucker and Mike Johnson assisted in the design of the Network
`
`Interface Unit .
`
`Len Hedges, Fred Holy, Jim Knoke, and Rich Slavens all contributed
`
`to the actual fabrication of the system hardware.
`
`Thanks also to Susan Rankaitis and Ann Carroll for their help in the
`
`assembly and typing of this report and to Jim Parry for the helpful
`
`comments .
`
`Page 5 of 24
`
`
`
`1
`
`: r
`
`\
`I I
`
`I I
`
`Page 6 of 24
`
`Page 6 of 24
`
`
`
`5
`
`l
`
`1
`
`1
`
`FIGURE2TERMINAL
`
`Page7 of 24
`
`Page 7 of 24
`
`
`
`6
`
`9. Additional input- output channels for the control of
`auxiliary equipment .
`
`10. An optional random-access audio response unit.
`
`A detailed description of the terminal can be found in reference 3 .
`
`Central Computer
`
`Operation of tQe entire PLATO IV system is under control of a CDC
`
`6400 computer system. This computer, see Figure 3, is a large seale
`
`general purpose computer containing one very fast central processing
`
`unit (CPU) and 10 independent peripheral processing units (PPU) which com-
`
`municate with the CPU via the central memory. Augmenting the central
`
`memory is the extended core storage (ECS) system which can provide storage
`
`of up to two million additional , .. ords . Additional mass storage is
`
`provided by three disk pack drives , 32 million characters each, and one
`
`75 million character disk. Twelve input-output channels are available,
`
`two of which operate the PLATO IV Network Interface Unit with others
`
`controlling the various peripheral equipment as shown in Figure 3 .
`
`Network Interface Unit--Output Controller
`
`The Output Controller is basically a parallel to serial converter .
`
`This equipment accepts data from the computer and prepares it for
`
`transmission over the PLATO network .
`
`A functional block diagram of the output controller is shown in
`
`Figure 4. The controller consists of two 1024 by 20 bit memories, a
`
`word assembly register, a write control, a read control, a four bit
`
`3J . Stifle , "A Plasma Display Terminal, " CERL Report X-15, March, 1970 .
`
`II
`
`I I
`
`Page 8 of 24
`
`
`
`,--
`
`,--
`
`,--
`
`r--
`
`c::::- ~ r--
`
`~
`
`L
`
`~
`
`J
`
`__ ------.J
`
`.J
`
`~
`
`I
`
`I ..
`
`6641
`
`.. ADAPTER
`..
`'"
`
`~ ~
`
`3 DISK PACK DRIVES
`(32 MEG. CHAR. EACH)
`-.., .....
`.....
`...., ..
`,
`
`~
`{:
`
`{.
`
`~
`
`CONSOLE
`
`0 0
`
`A",
`
`PLATO
`IV
`N I U
`
`....
`,
`~
`
`~
`
`...
`...
`
`..
`... DISTRIBLJrED
`..
`...
`DATA
`PATH
`...
`...
`
`• 10
`
`r - - I
`
`---. 9 I.
`•
`,...
`
`.. 6
`
`~
`--.
`•
`...
`..
`~
`:.
`..
`..
`..
`---.
`
`L..
`en I"'"
`-.J
`W
`..
`... 8 ..
`z ....... ~
`z
`« ...
`.. 7 ..
`I
`() I"'"
`•
`,...
`.
`...
`..
`I-
`:::l
`a..
`I- L.. "'5 1.
`3 I"'"
`..
`~ ..
`~ .. "'4"
`:::l
`a..
`~ .. 3 ...
`.. ~
`Z
`,...
`,. .
`.... ·2
`
`...
`
`I"'"
`
`..
`
`!""
`
`~ ,
`~ r
`rt EXTENDED
`CORE
`STORAGE
`(E C S)
`
`.~
`CENTRAL
`MEMORY
`(CM)
`
`I.
`....
`
`, , .,
`~ '" . ,..
`
`~'"
`
`CENTRAL
`
`..
`... PROCESSING
`
`UNIT
`(CPU)
`
`-..j
`
`MAGNETIC
`TAPE
`UNITS
`
`t..
`
`...
`
`..
`..
`
`CII
`
`LINE
`PRINTER
`
`~
`
`.--I
`, Ir
`75 MEG. CHAR
`DISK
`
`.... I ...
`I"'"
`..
`,...
`10 PERIPHERAL
`PROCESSORS
`(PPU)
`
`FIGURE 3.
`
`6400 COMPUTER SYSTEM
`
`Page 9 of 24
`
`
`
`8
`
`From C mp u ter
`
`\,ri t e
`Con trol
`
`Memory 2
`1024 \,ords
`20 Bits
`
`'
`
`"
`./
`",
`, , /
`
`I
`
`I -I
`
`I
`)-1
`I
`I
`I
`I
`I _
`~~
`Read
`Con tro1
`
`,
`•
`
`Buffer Register
`
`Shif t Regis ter
`
`I
`
`DTX
`
`To CATV Eq uipment
`
`J,
`Memory 1
`1024 Hords
`20 Bi ts
`
`I
`
`I
`
`II
`
`I I
`
`II
`
`FIGURE 4 OUTPUT CONTROLLER - BLOCK DIAGRAM
`
`Page 10 of 24
`
`
`
`l
`I ,
`
`,
`
`J
`J
`
`9
`
`memory uffer r egister , a f our bit shift r egist er, and a digital data
`
`transmit ter (DTX). The contents of either of the memories in the contl'o) -
`
`ler are loaded or read in 1/60 second. One memory is loaded by the
`
`computer during the 1/60 second that t he other memory is beilli( r ead i nto
`
`t he DTX .
`
`Each group of three 1 2 bit words from the computer is assembled oy
`
`the Output Controller into one 30 bit word as shown in Figure 5 .
`
`\>lord 1
`
`\>lord 2
`
`Word 3
`
`00
`
`II 10 09
`•
`•
`Data
`o •
`1 :
`: Bits 10-19
`•
`,
`
`19
`
`nn
`Ll 10 09
`;
`Dat a
`~
`•
`•
`•
`0 . 0 1 Bits 01 -09 ~
`
`TERllINAL DATA
`
`.f" 01 00
`P
`
`LlIO 09
`Ol E : ADDRESS
`-!
`:
`
`29 ..
`
`TERMINAL
`ADDRESS
`
`00
`
`20
`
`FIGURE 5 OUTPU'l' DATA FORl,IAT
`
`Bit 00
`
`Bits 01- 19
`
`Bits 20- 29
`
`Parity Bit. This bit is filled by
`the controller with a parity bit
`(odd parity) for the da ta portion
`of the word .
`
`Terminal Data
`
`Addr ess of terminal for whi ch data
`is , intended .
`
`Bits 10- 11 of the three 12 bit words are control bits used by t he controJ(cid:173)
`ler as foll ows :
`
`Bit 11, word 1
`
`Bit 10 , word 3
`
`This bit i ndi cates the fi r st word of
`a 3 word sequence.
`
`This bit, when equal to II] II j.ndicatt;.t;
`that this word is t he addr ess :;f th ~
`l ast terminal t o r eceive duta durin~
`the pre"cn ~ 1/60 of a sec ond.
`
`Page 11 of 24
`
`
`
`10
`
`~lri te (load) operations consist of storing the terminal data portions
`
`of the data words in a memory using the terminal addresses as memory
`
`addresses . Thus , for example , the data for terminal 355 would be stored
`
`in memory location 355 . Parity bit assignment on the data is made just
`
`prior to the t i me the data is stored in memory .
`
`A read operation consists of :
`
`1 . Read one bit from each of four consecutive memory addresses .
`
`2. Load t he four bits into the memory buffer register .
`
`3 . Write logical zeros in memory in place of the data .
`
`4 . Load the shift register from the buffer register.
`
`5. Shift dat a from register to DTX .
`
`6.
`
`Incr ement memory address .
`
`7 . After 1008 addresses are read, decrement the bit count .
`
`Read operations continue until all 20 bits of all (1008) locations
`
`have been read and transmitted . After having been read the contents of
`
`each memory location is all "O "' s. An all "O" ' s data W"ord is interpreted
`
`by the PLATO IV terminals as a no- operation (Nap) code . The computer is
`
`I
`
`therefore required to send data only to those terminals requiring neW"
`
`i"nformation ; t he controller ;r111 automatically transmit Nap codes to all
`
`other terminals . A more detailed descrjption of the Output Controller
`
`can be found in reference 4.
`
`4
`Paul Tucker, "A Large Scale Computer Terminal Output Controller , " CERL
`Report X- 27 , June, 1971.
`
`I(
`
`I '
`
`Page 12 of 24
`
`
`
`l
`
`I
`I
`
`l
`n
`
`,
`
`u
`u
`u
`
`Network Interface Unit -
`
`Input Controller
`
`11
`
`All incoming lines from the PLATO IV terminals are routed to the
`
`input controller . The i nput controller scans these li nes f or data and
`
`control s the flow of the data into the peripheral processor.
`
`The f ormat of th e incoming data is shown in Figure 6.
`
`16 15
`
`11 10
`
`01 00
`
`Terminal
`Address
`
`DATA
`
`FIGURE 6
`
`I NPUT DATA FORMAT
`
`Bit 00
`
`Bi ts 01-1 0
`
`Bits 11-1 5
`
`Bit 16
`
`Parity Bit
`
`Data
`
`Address of terminal sending data
`
`~1 essage start bit , always "I ".
`
`A funct ional block diagram of t he Input Controll er is shown in
`
`Figur e 7 . The data on each l ine arrives at the c ontr oller at a rate of
`
`1260 bits /second and i n the form of a fr equency modulated (FM) signal.
`
`The demodulators r ecover the data from the fm signal and stor es it
`
`temporarily in a holding regis ter unt il it is read by th e c ontroller .
`
`The controller is basically a 32 channel (1 6 bits/channel) multi -
`
`plexor . The s c anner scans t he holding register s in the demodulat ors; if
`
`a register contains data the scanner halts , transfers t he data to the
`
`peripheral processor a nd then resumes the scan . The scanner and
`
`comput er operate at a rate sufficient to ensure t hat no data is l ost on
`
`any incoming line . The Input Contr oller attaches a 5 b it channel (SITE)
`
`address to the data word and checks the parity before sending the data
`
`Page 13 of 24
`
`
`
`12
`
`Telephone Lines
`to
`Classroom Sites
`
`Site 01 Site 00
`
`Site 32
`
`- - - - - - - - - - 32 Total -------~
`
`Demodulato r s
`and Serial to
`Parallel Circuits
`
`01
`00
`
`32 Position Scanner
`
`16 Bits
`
`31
`
`r ---
`
`--
`
`--
`
`--
`
`Channel
`Add r ess
`
`6 5 bits
`,
`
`To Computer
`
`FIGURE 7
`
`INPUT CONTROLLER - BLOCK DIAGRAM
`
`I I
`
`I 1
`
`i I
`
`I
`I
`
`,
`
`I [
`
`Page 14 of 24
`
`
`
`13
`
`on to the computer . The complete input data word , Figure 8 i s
`
`disassembled into two 12 bit words for transmission t o the computer.
`
`20
`
`SITE
`ADDRESS
`
`16 15
`
`I TERMINAL
`
`ADDRESS
`
`11 10
`
`DATA
`
`01 00
`
`IE I
`
`0 04
`
`00
`
`SITE
`ADDRESS
`
`TERMINAL
`ADDRESS
`
`r~ rO
`
`WORD 1
`
`DATA
`
`',DRD 2
`
`Figure 8
`
`Input Data l,ord Format
`
`Bi t 00
`
`Bits 01-10
`
`Bits 11- 15
`
`Bits 16-20
`
`If this bit is a 1 , the
`Error Bit .
`data word contains an error.
`
`Terminal Data .
`
`Terminal Address .
`
`SITE Address .
`
`Input Controller Programming
`
`The PPU controls the operation of t he Input Controller with the
`
`external function (EXF) codes . These codes can be used to activate or
`
`deactivate any of the data lines arriving f r om the PLATO network. Status
`
`ReQuest codes are also available for sensing the state of any of the
`
`data lines. The format of the EXF codes is shown in Figure 9.
`,
`Table 1 li sts the f unction and Status Codes for the Output Controller.
`
`Each code is de sc r ibed below:
`
`11 10 09 08 07 06 05 04 03 02 01 00
`-.
`0 : 0 : 0
`!
`I
`
`FIGURE 9 EXF FORMAT
`
`-,
`
`n
`[ 1
`
`II
`lJ
`L
`L
`L
`L
`L
`
`Page 15 of 24
`
`
`
`Bits 00- 04
`
`Bit 05
`
`Bits 06- 08
`
`Bits 09-11
`
`14
`
`Specify a scanner channel address.
`
`Specifies an activate (Bit 5=1)
`or deactivate (Bit 5=0) function .
`
`Specify function as follows:
`
`000 - All channel function
`
`·001 - Single channel function
`
`111 - Status Request Code
`
`These bits specify the equipment
`number assigned to the Input Controller.
`They are always O.
`
`Function Code
`000 000 a 00000
`000 000 1 00000
`000 001 a XXXJCX.
`000 001 1 XXXXX
`000 111 a JCXXXX
`000 111 1 JCXXXX
`a
`1
`
`x
`x
`
`x
`x
`
`PLATO IV Input Controller EXF Codes
`
`Deactivate
`Activate
`
`Deactivate
`Activate
`
`Sense
`Channel. XXJCXX
`
`Negative
`Positive
`
`TABLE 1
`
`All Channels
`All Channels
`
`Channel XXXJCX
`Channel XXXJCX
`
`Inactive
`Active
`
`Response to
`Sense Codes
`
`x
`x
`
`Deactivate all lines (0000)
`
`This code deactivates all channels .
`
`Activate all lines (0040)
`
`This code activates all channels .
`
`Deactivate Channel (0100 - 0137)
`
`These codes deactivate the channel specified by the lower five bits
`
`of the EXF code .
`
`I I
`
`I I ,
`
`I I
`I I
`
`\ ,
`I I ,
`
`II
`
`Page 16 of 24
`
`
`
`Activate Channel (0140 - 0177)
`
`15
`
`These codes activate the channel specified by the lower five bits
`
`of the EXF code .
`
`Status Request Codes (0700 - 0777)
`
`These codes may be used to sense the status of the Output Controller .
`
`A one word input must follow the Status Request to read in the status word.
`
`The status word has the format shown in Figure 10 .
`
`11
`
`00
`
`xxx
`
`xxx
`
`xxx
`
`XXS
`
`FIGURE 10 STATUS WORD FORMAT
`
`Bit 00
`
`Bits 01-11
`
`Sit e Controller
`
`Sense Response. Bit 0 = ' 0 ' for a
`negative or a "1 " for a positive
`response to the condition sensed for .
`
`Not used .
`
`The PLATO Site Controller is a communications interface unit designed
`
`to process two- way digital communication between 32 PLATO IV student
`
`terminals and a remotely located computer .
`
`Data received from the computer by the Site Controller arrives in
`
`the form of a standard FCC television signal in which that portion of the
`
`signal which normally contains video (picture) information contains instead
`
`digital data . This data must be recovered from the television signal and
`
`distributed to the terminals serviced by the Site Controller . That
`
`portion of the Site Controller which performs this receiving and
`
`distributing function is referred to as a Digital Television Receiver (DTR) .
`
`,
`I
`
`11
`
`I. )
`
`1
`
`~l
`
`I~
`
`L
`U
`
`I
`~
`
`Page 17 of 24
`
`
`
`16
`
`I \
`
`Vi deo Cable
`From computer center 'r-------,
`
`To other sites
`
`r - - - - - - ----------------------,
`V
`I
`I
`I
`I
`I
`
`Digital Television
`Receiver and Distributor
`( DTR)
`
`L _______________ 1
`
`D ------- Upto 32 ______ _
`
`Terminals
`
`D
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`r- _____________ ---1
`I
`I
`Concentrator
`I L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J
`Voice Grade line
`
`Site Controller
`
`To computer center
`
`GR-640
`
`FIGURE 11 SITE CONTROLLER
`
`I ,
`
`I
`
`I
`
`Page 18 of 24
`
`
`
`l'T
`
`Data generated by the terminals is transmitted to the Site Controller
`
`and from there the" data is transmitted in a time division multiplex mode
`
`on a voice gr ade telephone circui t to the computer center. The data
`
`from up to 32 terminals is transmitted on a single voice grade circuit .
`
`That portion of the Site Controller which performs this function is
`
`referred to as a Concentrator .
`
`A block diagram of the Site Controller is shown in Figure 11 .
`
`Concentrator
`
`Data received by the Concentrator from each of the terminals is in
`
`the form of 12 bit words with the format shown in Figure 12 . These words
`
`11 10
`
`DATA
`
`01 00
`
`p
`
`FIGURE 12 TERMINAL TRANS~nTTED DATA FOW>lAT
`
`arrive serially , bit 11 first and bit 00 last , at a rate of 1260 bits per
`
`second . Bit 11 , the first bit in every word, is always a logical one .
`
`Bit 00 is a parity bit which forces the number of ones in a word to
`
`always b e odd .
`
`These data words are transmitted as a frequency shift keyed (FSK)
`
`signal as shown in Figure 1-3. Tp is 1/1260 second and represents one
`
`o
`
`o
`
`i
`
`·
`
`o
`
`FIGURE 13 FSK SIGNAL
`
`l
`l
`l
`l
`1
`
`1
`
`J
`
`.. ,
`
`..J
`
`L
`L
`
`Page 19 of 24
`
`
`
`18
`
`bit interval. A logical one is represented by one cycle of a 1260 hz
`
`signal and a logical zero as two cycles of a 2520 hz signal .
`
`The Concentrator must (1) receive these data words, (2) attach B 5
`
`bit address to the word identifying the terminal transmitting the word ,
`
`(3) ~djust the parity bit taking into account the address , and (") transmit
`
`the expanded word to the NIU at the computer center. The format cf the
`
`data words transmitted from the Concentrator is shown in Figure 14 . These
`
`17 bit words are transmitted serially , bit 16 first and bit 00 last . at
`
`a rate of 1260 bits per second . Bit 16, the first bit transmitted in
`
`16 15
`
`11 10
`
`11 I TERMINAL
`
`ADDRESS
`
`DATA
`
`01 00
`
`I P I
`
`FIGURE 14 CONCENTRATOR WORD FORMAT
`
`every word is always a logical one . Bit 00 is a parity bit which forces
`
`the number of ones in a word to always be odd. The data words are
`
`transmitted as a frequency shift keyed (FSK) signal as shown in Figure 13.
`
`DTR
`
`Information (data) destined for the PLATO terminals is transmitted
`
`in a time-division multiplexed mode as a NTSC (National Television
`Standards Committee) television signal . 5 The DTR must recover the data
`
`from the television signal , generate the terminal addresses for the data,
`
`and distribute the data to those terminals serviced by the Site Controller.
`
`When the terminals are in close proximity, i . e . same building, as the
`
`5Stifle, Bitzer , Johnson, "Digital Data Transmission Via CATV," pps. 5-7 .
`
`I,
`
`I I
`I ,
`
`Page 20 of 24
`
`
`
`19
`
`Site Controller , the data is distributed via twisted pair wires . For
`
`remotely loc ated terminals, the data is transmitted via voice grade
`
`telephone lines .
`
`,
`
`l
`
`l
`l
`I '
`II
`
`Page 21 of 24
`
`
`
`I 1
`I
`
`I 1 . I
`II
`II
`
`I I
`
`I .
`I I
`
`I .
`
`I
`I
`I I
`
`'
`
`I
`
`I I ,
`
`I I
`I
`
`.
`
`,
`
`I I
`
`II
`I :
`II
`
`Page 22 of 24
`
`Page 22 of 24
`
`
`
`~
`l
`l
`L
`L
`[
`[
`l
`
`Page 23 of 24
`
`
`
`I
`
`Page 24 of 24
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
