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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`––––––––––
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`––––––––––
`Marvell Semiconductor, Inc.,
`Petitioner,
`v.
`Credo Technology Group Ltd.,
`Patent Owner.
`
`––––––––––
`
`IPR2025-01220
`U.S. Patent No. 11,032,111
`––––––––––
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 11,032,111
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`TABLE OF CONTENTS
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`I. Overview of the Technology ........................................................................... 6
`A. Equalization ........................................................................................... 7
`B. Channel Loss & Transmission Performance ....................................... 10
`II. The ’111 patent .............................................................................................. 12
`A. Prosecution History ............................................................................. 12
`B. Priority Date ........................................................................................ 12
`III. Field and Level of Ordinary Skill .................................................................. 13
`IV. Claim Construction ........................................................................................ 14
`V. Invalidity Grounds ......................................................................................... 15
`A. Ground 1 .............................................................................................. 15
`1. Berke (Ex-1004) ........................................................................ 16
`2. Cornelius (Ex-1005) .................................................................. 16
`3. Claim 1 ...................................................................................... 17
`4. Claim 3 ...................................................................................... 29
`5. Claim 4 ...................................................................................... 30
`6. Claim 6 ...................................................................................... 31
`7. Claim 7 ...................................................................................... 31
`8. Claim 8 ...................................................................................... 32
`9. Claim 10 .................................................................................... 39
`10. Claim 11 .................................................................................... 39
`11. Claim 13 .................................................................................... 40
`12. Claim 14 .................................................................................... 40
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`13. Claim 15 .................................................................................... 41
`14. Claims 16, 17, 19 ...................................................................... 42
`B. Ground 2 .............................................................................................. 42
`1. Ran (Ex-1006) ........................................................................... 42
`2. Claims 1, 3, 4, 6, and 7 ............................................................. 43
`3. Claim 8 ...................................................................................... 43
`4. Claim 10 .................................................................................... 48
`5. Claim 11 .................................................................................... 48
`6. Claims 13-15 ............................................................................. 49
`7. Claims 16, 17, 19 ...................................................................... 49
`C. Grounds 3 and 4 .................................................................................. 50
`1. Stauffer (Ex-1008) .................................................................... 50
`2. Claim 2 ...................................................................................... 51
`3. Claim 5 ...................................................................................... 53
`4. Claims 9, 12, 18 ........................................................................ 55
`D. Ground 5 .............................................................................................. 55
`1. Mejia (Ex-1009) ........................................................................ 56
`2. Claim 1 ...................................................................................... 56
`3. Claim 2 ...................................................................................... 69
`4. Claim 3 ...................................................................................... 71
`5. Claim 4 ...................................................................................... 72
`6. Claim 5 ...................................................................................... 73
`7. Claim 6 ...................................................................................... 74
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`8. Claim 7 ...................................................................................... 74
`9. Claim 8 ...................................................................................... 75
`10. Claims 9-10 ............................................................................... 78
`11. Claim 11 .................................................................................... 78
`12. Claims 12-13 ............................................................................. 80
`13. Claim 14 .................................................................................... 80
`14. Claim 15 .................................................................................... 80
`15. Claim 16 .................................................................................... 81
`16. Claims 17-19 ............................................................................. 81
`VI. Standing ......................................................................................................... 81
`VII. MANDATORY NOTICES AND FEES ....................................................... 81
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`EXHIBIT LIST
`Exhibit No. Description
`1001 U.S. Patent No. 11,032,111 to Sun et al. (the ’111 patent)
`1002 Certified Prosecution History for the ’111 patent (“Prosecution
`History”)
`1003 Declaration of Michael S. Chen
`1004 U.S. Patent App. Pub. No. 2019/0288881 to Berke et al.
`(“Berke”)
`1005 U.S. Patent No. 8,516,238 to Cornelius, et al. (“Cornelius”)
`1006 U.S. Patent No. 10,715,357 to Ran (“Ran”)
`1007 U.S. Prov. App. Serial No. 62/722,517 (“Ran Provisional”)
`1008 Excerpts from Stauffer, High Speed Serdes Devices and
`Applications (“Stauffer”)
`1009 U.S. Patent App. Pub. No. 2014/0237301 to Mejia et al.
`(“Mejia”)
`1010 PCI Express Base Specification Revision 3.0 (Nov. 10, 2010)
`1011 Serial ATA Revision Specification 3.1 (July 18, 2011)
`1012 Excerpts of IEEE 802.3-2015 Standard
`1013 Declaration of June Munford re: Stauffer
`1014 Library of Congress Certification for Stauffer
`1015 Internet Archive Declaration of Mina Ching re: Stauffer
`1016 Declaration of Liliana Nunez re: Stauffer
`1017 U.S. Patent App. Pub. No. 2013/0223506 to Kolze
`1018 U.S. Patent App. Pub. No. 2010/0232493 to Thirumoorthy
`1019 U.S. Patent App. Pub. No. 2013/0201316 to Binder et al.
`1020 U.S. Patent No. 5,648,972 to Gharakhanian
`1021 U.S. Prov. App. Serial No. 63467_62723701 (’111 Patent
`Provisional)
`1022 Excerpts from Gasca, et al., CMOS Continuous-Time Adaptive
`Equalizers for High-Speed Serial Links
`1023 U.S. Patent No. 7,233,617 to Gorecki
`1024 U.S. Patent App. Pub. No. 2003/0035497 to Gorecki et al.
`1025 TE Connectivity, SFP+ High Speed Copper Cable Assemblies
`1026 Cisco, Cisco 40GBASE QSFP Modules Data Sheet
`1027 Wang & Bovik, Mean Squared Error: Love It or Leave It?
`1028 U.S. Patent No. 8,665,941 to Eliaz
`1029 U.S. Patent No. 8,600,039 to Chen et al.
`1030 U.S. Patent No. 5,392,315 to Laud
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`Serial communications have long used a technique called equalization,
`which used filters to improve the quality of signals transmitted over a channel.
`These filters included coefficients that were adjusted to match the specific
`characteristics of the channel. When conditions changed—e.g., from temperature
`shifts—training processes updated the initial coefficients. These fundamental
`techniques were taught in textbooks and college courses. Moreover, to
`accommodate different environments, systems often stored multiple sets of initial
`coefficients to choose from as a starting point for operation.
`Against this backdrop, the ’111 patent identified an increasing need for
`equalization as data rates increased. As a solution, the patent proposes the use of
`link training, with a set of initial coefficients. This, however, was a trivial concept
`that was already known in the art.
`I. OVERVIEW OF THE TECHNOLOGY
`High-speed serial communications became widespread in the 1990s as an
`alternative to parallel communications, which used multiple signal lines in parallel.
`As transmission speeds increased, parallel systems faced synchronization/routing
`challenges. Serial communication addressed these limitations by using a single
`channel, simplifying synchronization, and reducing pin count. Ex-1003, ¶4.
`By the early 2000s, computer bus and networking protocols had largely
`shifted to serial connections. Serial ATA (“SATA”) replaced parallel ATA; serial
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`PCIe replaced parallel PCI; and Universal Serial Bus (“USB”) replaced legacy
`parallel interfaces. Ethernet had long utilized serial connections. This process—
`where parallel data within a chip was converted into a serial bitstream
`(serialization), sent over a serial link, and then converted back into parallel
`(deserialization)—was called “SerDes.” Ex-1003, ¶5.
`Ethernet has been a widely used networking standard since the 1990s. By the
`2010s, Ethernet had become the primary high-speed serial communication standard
`for enterprise and data center networks, scaling from 1 Gigabit Ethernet (GbE) to
`widespread 10 GbE adoption. Serial cables are examples that implement the
`ubiquitous Ethernet standard. Ex-1008, 000058-000061. Ex-1003, ¶6.
`A. Equalization
`As connection protocols shifted to serial links, established serial
`communication techniques like equalization were adopted. Well before 2018,
`equalization was a standard topic in undergraduate courses on serial
`communications and routinely covered in relevant textbooks. Ex-1008, 000020-
`000024; Ex-1022, §1.1.1; Ex-1003, ¶7.
`Equalization performed at the transmitter was called “preequalization.” Pre-
`equalization adjusts the signal prior to the signal being sent over the channel to
`compensate for anticipated signal loss. Equalization was also performed at the
`receiver to adjust for channel losses after the signal crossed the channel. This
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`combination of pre-equalization at the transmitter and equalization at the receiver
`enabled robust, high-speed transmission across noisy channels. Ex-1008, 000020-
`000024; Ex-1003, ¶8.
`Because channels attenuate different frequencies unevenly, pre-equalization
`selectively boosted signal frequencies expected to experience greater loss. This
`ensured the received signal more closely matched the original signal after crossing
`the channel. Pre-equalization is illustrated below: the red boxes show the original
`waveform with and without pre-equalization. Ex-1008, FIGS. 1.9-1.10 at 000021:1
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`1 All emphasis and annotations added unless stated otherwise.
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`Ex-1003, ¶9.
`Pre-equalization was often implemented at the transmitter using a finite
`impulse response (“FIR”) filter. An FIR filter performs a weighted sum by
`multiplying adjacent data “taps” with coefficients. For pre-equalization, these
`coefficients are selected to amplify frequencies that the channel diminishes. As a
`result, the effects of the filter and channel cancel each other out, leaving the signal
`closer to its original form. A specific implementation is a Feed-Forward Equalizer
`(“FFE”). Ex-1008, 000020-000021, 000050; Ex-1022, 000025-000027.
`Equalization could also be added at the receiver end of the channel to further
`compensate for the channel loss. Ex-1003, ¶¶10-11.
`Because channel conditions changed, for example due to temperature
`variation, many serial communications systems used “training” to update
`equalization coefficients to the current channel characteristics. Training was a
`basic concept taught in textbooks and undergraduate courses on serial
`communications. Ex-1008, 000067-000069; Ex-1004, ¶3; Ex-1006, Abstract, 3:29-
`50, 15:45-50; Ex-1009, ¶32; Ex-1003, ¶12.
`Coefficient training usually started by configuring the channel with initial
`equalization coefficient values. Since the effectiveness of the training process
`depended on the quality of the initial coefficient values, it was common practice
`for serial communications systems to store multiple sets of “preset” or
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`“whitelisted” equalization coefficient values for use as the starting point or initial
`values for coefficient training. Ex-1004, ¶¶30-32; Ex-1006, 10:6-14, Fig. 3B.
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`Different baseline coefficients sets reflected different channel characteristics,
`allowing selection of the most suitable set as a starting point for training based on
`its performance for a particular channel. Ex-1004, ¶¶30-33, Ex-1009, ¶¶31-32, ¶36;
`Ex-1003, ¶12.
`B. Channel Loss & Transmission Performance
`Bit Error Rate (“BER”) and opening of an eye diagram were common
`criteria for evaluating performance of high-speed serial communications systems.
`Ex-1008, 000014-000015, 000020-000021; Ex-1003, ¶¶13-15.
`BER quantifies how often errors occur due to noise, interference, or
`distortion in the transmission channel. A lower BER indicates a more reliable
`communication link, and vice versa. Ex-1008, 000014-000015; Ex-1003, ¶16.Eye
`diagrams visually display overlapping traces of a digital waveform to allow quality
`assessment based on noise, jitter, and signal distortion:
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`Ex-1004, FIG. 2, ¶22. It was a well-known metric taught in undergraduate courses
`to measure “eye opening” for assessing the overall link quality in high-speed serial
`communications, including the impact of equalization. Ex-1008, 000014-000015;
`Ex-1003, ¶17.
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`II. THE ’111 PATENT
`The ’111 patent notes a problem of increased channel attenuation and
`dispersion in serial communications caused by the demand of “ever-higher data
`rates.” Ex-1001, 1:28-34. To address the problem, the ’111 patent purports to
`select initial pre-equalizer coefficients, stored in registers, and then use link
`training to refine them. Ex-1001, 1:39-58; Ex-1003, ¶18.
`A. Prosecution History
`The application for the ’111 patent was allowed after two Office Actions,
`where the Examiner rejected some claims as being obvious and identified other
`claims as allowable. Ex-1002, 000331-000345, 000389-000396. The Applicant
`overcame the Office Actions by incorporating allowable subject matter, including
`“each of the multiple registers corresponding to a different channel model,”
`without disputing the Examiner’s obviousness rejections. Ex-1002, 000370-
`000375, 000413-18. Neither the Examiner nor the Applicant explained why the
`allowable subject matter was non-obvious in view of the prior art. Ex-1003, ¶¶19-
`20.
`B. Priority Date
`The specification of the ’111 patent includes disclosure that is not in its
`provisional application, including that related to “channel model,” “chip-to-module
`(C2M) communications link,” or “pluggable module.” The ’111 patent is not
`entitled to the priority date of its provisional application because each of its
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`independent claim is not adequately supported by the written description of the
`provisional application. Ex-1003, ¶23. Nonetheless, this Petition analyzes
`invalidity as of August 28, 2018, and the analysis does not change for obviousness
`as of August 27, 2019. Ex-1003, ¶¶22-24.
`III. FIELD AND LEVEL OF ORDINARY SKILL
`The field of the patent is serial communications. See, e.g., Ex-1001,
`Abstract, 1:19-35. The patent is directed to methods for sending data in serial form
`over a channel. Id., Abstract, 1:49-54, cls.11, 16. The specification states that the
`’111 patent’s communications method is implemented on a transceiver “as
`application-specific integrated circuitry for very high-rate serial data transmission
`and reception.” Id., 5:10-16, Abstract, 1:39-41, 5:24-34, 10:4-11, 6:34-37, FIGS. 4-
`5, 10:39-40. Independent claims 8, 11, and 16 all recite “serial” communications,
`and claim 1 recites “SerDes,” which includes serialization for serial
`communications. Supra §I.A; Ex-1003, ¶26.
`A person of ordinary skill in the field of art (“POSITA”) would have been a
`person with a bachelor’s degree in electrical or computer engineering with at least
`three years of experience in serial communications. A person with more education
`but less practical experience may also meet this standard. Ex-1003, ¶28.
`In the relevant timeframe, a POSITA with the above-described level of skill
`would have been able to:
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`• Understand common high-speed serial components, including
`equalization, pre-equalization, and FIR filters;
`• Evaluate channel loss, compensation, and channel performance using
`indicators such as BER and eye diagrams;
`• Design high-speed serial communication systems;
`• Design equalization/pre-equalization filters, including FFE and
`coefficients;
`• Design equalization training methods;
`• Program a digital signal processor (“DSP”) to perform common
`transceiver functions;
`• Implement protocols for calibrating and setting equalization
`parameters; and
`• Configure host port connector and cable/card plugs with embedded
`transceivers.
`Ex-1003, ¶29.
`IV. CLAIM CONSTRUCTION
`Claims should be construed according to the ordinary and customary
`meaning as understood by a POSITA.
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`V. INVALIDITY GROUNDS
`Petitioner requests inter partes review and cancelation of the challenged
`claims on the following grounds:
`Grounds Claims Statutory Basis Prior Art
`1 1, 3, 4, 6-8, 10-
`11, 13-17, 19
`§103 Berke and Cornelius
`2 1, 3, 4, 6-8, 10-
`11, 13-17, 19
`§103 Berke and Ran
`3 2, 5, 9, 12, 18 §103 Berke, Cornelius, and Stauffer
`4 2, 5, 9, 12, 18 §103 Berke, Ran, and Stauffer
`5 1-19 §103 Ran, Mejia, and Stauffer
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`The Grounds render the challenged claims obvious because any differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was made to
`a POSITA to which the subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550
`U.S. 398, 406 (2007).
`None of these references were considered during examination. Ex-1003,
`¶21.
`A. Ground 1
`Ground 1 applies Berke’s techniques for selecting and updating pre-
`equalizer coefficient values to Cornelius’s active cable teachings, in particular for
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`communications between a pluggable module of the cable and host. Infra
`§V.A.9[8pre]; Ex-1003, ¶33.
`1. Berke (Ex-1004)
`Berke is post-AIA §102(a)(2) prior art; it was filed March 19, 2018 and
`published September 19, 2019. Berke teaches optimizations for equalization
`coefficients in a high-speed serial interface, namely that coefficients known to
`provide “robust” performance are stored in a “whitelist” comprising a “group of
`registers.” Ex-1004, ¶¶12-15, 30, FIG. 1. Whitelisted coefficients are selected as
`starting points for adaptive equalization training. Ex-1004, ¶33, ¶30, ¶13, ¶¶24-26;
`Ex-1003, ¶¶35-36.
`Berke is analogous art because it is in the same field. Compare supra §III
`with Ex-1004, Title, ¶¶1-4, 13, 35, 39. Berke is also reasonably pertinent because it
`relates to ensuring reliable data transmission through a communication channel.
`Ex-1004, ¶3; Ex-1003, ¶37.
`2. Cornelius (Ex-1005)
`Cornelius is prior art under post-AIA §§102(a)(1)-(2); it issued August 2013.
`Cornelius teaches a high-speed active cable with transceivers at each end. Ex-
`1005, 4:22-65, 6:11-24, 8:20-26, FIGS. 5-6. Cornelius uses equalization for
`various communication paths. Id., 11:45-51; Ex-1003, ¶39.
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`Cornelius is analogous art because it is in the same field. Compare supra
`§III with Ex-1005, Abstract, 1:15-22. Cornelius is also reasonably pertinent; it
`relates to ensuring reliable data transmission through a serial communications
`channel. Ex-1005, 11:45-62; Ex-1003, ¶40.
`3. Claim 1
`[1pre] A SerDes communications method that comprises, in a transceiver:
`To the extent the preamble is limiting, Ground 1 teaches a SerDes
`communications method. Berke teaches “a high-speed serial channel 100 of an
`information handling system,” where two components communicate over “a bi-
`directional serial data link,” which suggests a common serial architecture where
`data is serialized, transmitted, and then deserialized. Ex-1004, Abstract, ¶12
`(“Serial channel 100 includes a transmitter 110, a transmission channel 120, and a
`receiver 130.”), ¶1, ¶4 (“High-speed serial data interface … may include a
`transmitter and a receiver.”), FIG. 1:
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`Ex-1003, ¶41.
`Berke applies its teachings to standards with SerDes architectures, such as
`PCIe and SATA. Ex-1004, ¶12. Both included serialization and deserialization,
`which a POSITA would have understood given their widespread use. E.g., Ex-
`1010, 000192-000193; Ex-1011, 000621 (“[S]erializer/deserializer (SerDes)
`circuits make up a typical Serial ATA interface Phy.”); Ex-1008, 000058-61
`(listing SATA and PCI Express as “protocol standards for which HSS [High-Speed
`SerDes] cores are used.”), 000018. Therefore, Berke teaches or suggests a method
`for SerDes communications. Ex-1003, ¶42.
`Likewise, Cornelius teaches PCIe and uses its active cable to provide high-
`speed serial connections between computers. Ex-1005, 2:65-3:53.
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`This architecture serializes parallel computer data into a narrow, high-speed stream
`for cable transmission—similar to funneling water into a narrow pipe—and then
`restores it to its original parallel form through deserialization at the other end. Ex-
`1003, ¶43. The types of serial communications taught by Berke and Cornelius
`presume serialization in the transmitter and deserialization in the receiver; a
`POSITA would have recognized this when reading Berke and Cornelius because
`that is how serial communications have been used for decades. Supra §I.
`Therefore, a POSITA would have been motivated, and found it obvious, to
`combine Berke and Cornelius’s teachings by using Berke’s high-speed serial
`communications in a SerDes context. Ex-1003, ¶44.
`Berke further teaches a transceiver. Figure 1 shows a “[s]erial channel 100
`includes a transmitter 110, a transmission channel 120, and a receiver 130.”
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`Ex-1003, ¶45. This represents “one half” of a bi-directional data link, with the
`“other half” having “a receiver in the first component, and a transmitter in the
`second component, for communicating data back from the second component to
`the first component.” Ex-1004, ¶12. Berke thus teaches a transceiver at each end of
`the communication link, comprising a transmitter and a receiver and coupled to
`two unidirectional channels, as shown below:
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`Ex-1004, FIG. 1; Ex-1003, ¶46.
`[1a] selecting one of multiple registers to specify initial pre-equalizer
`coefficient values, each of the multiple registers corresponding to a
`different channel model;
`Berke teaches pre-equalizer coefficient values. For example, Berke’s
`transmitter 110 includes “a feed-forward equalization (FFE) module 114,” which
`“operates to proactively provide compensation to a transmitted signal.” Ex-1004,
`¶¶14-15. Berke’s FFE module performs pre-equalization because it is configured
`on the transmitter side, and it provides compensation to a signal before it is
`transmitted to the receiver. Id. Berke’s “transmitter 110 and receiver 130
`communicate with each other to optimize and adjust various compensation values
`within the transmitter and the receiver to compensate for the insertion loss and
`other signal degradations of transmission channel 120.” Ex-1004, ¶13. Here,
`Berke’s compensation values refer to equalization coefficients. Ex-1004, ¶4, ¶¶22-
`23, ¶30. The compensation values or equalization coefficients include those that
`configure Berke’s FFE. Ex-1004, ¶15 (“The amount of compensation is
`determined by enabling a number of circuit feed-forward taps.”). A POSITA would
`have understood Berke’s equalization coefficients that are used to configure the
`transmitter’s pre-equalization process (e.g., FFE) to be pre-equalizer coefficient
`values. Ex-1003, ¶47.
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`Berke teaches selecting one of multiple registers to specify initial pre-
`equalizer coefficient values. The registers comprise two or more of the registers
`that store pre-equalizer coefficients in the whitelist. Berke teaches that the
`“[t]ransmitter 110 includes … an equalization coefficient whitelist 118” that stores
`“certain equalization coefficient settings or combinations of equalization
`coefficient settings [that] are known to produce one or more of a particularly robust
`eye height or eye width.” Ex-1004, ¶14, ¶30, ¶32, FIG. 1; Ex-1003, ¶48.
`Berke teaches two options for implementing the whitelists: registers or
`memory. Ex-1004, ¶30 (teaching “a register or group of registers of transmitter
`110 and receiver 130”). Because Berke teaches storing multiple sets of whitelisted
`coefficient settings (Ex-1004, ¶33) in a group of registers (Ex-1004, ¶30), Berke
`teaches or suggests using each register to store a set of pre-equalizer coefficients.
`For example, one whitelist register in the transmitter stores one set of pre-equalizer
`coefficients for the transmitter. Indeed, Berke teaches using an addressable register
`design, with each register structured in a certain bit width (e.g., 32 bits or
`higher)—evident from Berke’s I/O interfaces (e.g., I2C and SPI). Ex-1004, ¶36.
`Given the typical width of multi-bit registers in transceiver circuits, storing a set of
`three or more FFE tap coefficients per register was a straightforward and efficient
`design choice that allowed reading/writing Berke’s register in one clock cycle (see
`id.), as compared to more complicated schemes. This use of registers was a long-
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`standing practice in the field. See, e.g., Ex-1030, 1:10-25, 2:23-51 (“coefficient
`register 14” supplies coefficients C0-C3), FIG. 1. Furthermore, it simplified
`control logic, among other benefits. Therefore, a POSITA would have been
`motivated and found it obvious to apply Berke’s register teachings, as explained
`above. Ex-1003, ¶¶49-50.
`A POSITA would have had a reasonable expectation of success given the
`simplicity of a register-based approach. Reading/writing to registers was a basic
`undergraduate skill supported by well-known protocols (e.g., I2C and SPI) that
`allowed specifying preferred bit width and total number of registers. Using
`multiple registers—each holding a set of coefficients—falls squarely within
`Berke’s teachings (Ex-1004, ¶¶30-33) and was an obvious implementation detail
`that would have applied a known technique to a known device ready for
`improvement to yield predictable results (a register-based whitelist, as Berke
`teaches). See Ex-1004, ¶30; Ex-1003, ¶51.
`Berke further teaches selecting one of the multiple registers to specify initial
`pre-equalizer coefficient values. Berke selects a whitelist set of equalization
`coefficients from multiple sets by configuring the serial channel with each set of
`coefficients for training and monitoring the performance of the channel, until a
`whitelist set of equalization coefficients that satisfies a desired performance level is
`selected:
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`[A]fter a first whitelist set of equalization coefficients is utilized for
`training serial cha nnel 100, control logic module 140 operates to
`monitor the performance of the serial channel. … If the performance of
`serial channel 100 falls below the desired performance level, then
`control logic module 140 selects a second whitelist set of equalization
`coefficients…
`Ex-1004, ¶33.
`2 The pre-equalizer coefficients stored in the whitelist at the
`transmitter are initial pre-equalizer coefficient values because they are used as the
`starting point for the training process. Ex-1004, ¶30 (“utiliz[ing] the coefficient
`settings … stored in equalization coefficient whitelist[] 116 [sic] … as a starting
`point for running the training algorithm.”). Because each set of coefficients is
`stored in a register (explained above), Berke teaches selecting the register with that
`set of coefficients. Ex-1003, ¶52.
`Berke teaches each of the multiple registers corresponding to a different
`channel model. Berke stores sets of pre-equalizer coefficients known to provide
`“robust” performance for respective channel characteristics, so that one of them
`can be selected to use for training. Ex-1004, ¶¶30-33. The whitelist registers
`contain coefficients used “to compensate for channel loss.” Ex-1004, ¶3, ¶15.
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`2 A POSITA would have understood that different parts of Berke are intended to be
`implemented together in a flexible manner. Ex-1004, ¶40.
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`Variations in channel loss arise from differences in channel characteristics—such
`as design, settings, and environmental conditions—where different channel
`characteristics correspond to different channel models. Ex-1003, ¶53.
`Berke determines pre-equalizer coefficients to include in its whitelist based
`on different channel characteristics, which “can be determined based upon
`knowledge gained during the design, development, or manufacturing of serial
`channel 100.” Ex-1004, ¶30. Such knowledge would have informed one about
`“variations in circuit design, component manufacture” (Ex-1004, ¶3), such as
`characteristics of circuit traces, connectors, and cables (e.g., length of a trace) (Ex-
`1004, ¶12), characteristics such as “insertion loss and other signal degradations”
`(Ex-1004, ¶13), and channel characteristics such as “impedance … based upon a
`design target” (Ex-1004, ¶19). Ex-1003, ¶54. In addition, whitelisted equalization
`coefficients can also be “determined based upon knowledge gained during normal
`operation of serial channel” (Ex-1004, ¶31), which would have included settings
`that were used during operation such as receiver equalization settings (Ex-1004,
`¶16, ¶18; infra §V.A.4) and environmental conditions such as temperature and
`noise levels (Ex-1004, ¶21). Ex-1003, ¶55.
`Each of the aforementioned channel characteristics impact the channel loss
`and frequency response characteristics. Ex-1004, ¶3, ¶¶12-13, ¶¶16-21. A set of
`whitelisted pre-equalizer coefficients added to the whitelist based on knowledge of
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`channel characteristics (Ex-1004, ¶¶30-31) corresponds to a channel model that
`represents or assumes the known and relied-upon channel characteristics. Ex-1004,
`¶¶12-13, ¶¶16-21; Ex-1003, ¶56. Since Berke teaches or suggests using each of
`multiple multi-bit registers at the transmitter side to store a set of pre-equalizer
`coefficients, each of the multiple registers with FFE coefficients in the whitelist
`correspond to a different channel model. Ex-1003, ¶57.
`[1b] updating the initial pre-equalizer coefficient values during a training
`phase; and
`Berke teaches a training process that updates the pre-equalizer coefficient
`values, among other compensation values. Ex-1004, ¶13 (“[T]ransmitter 110 and
`receiver 130 communicate with each other to optimize and adjust various
`compensation values within the transmitter and the receiver.”). Ex-1003, ¶58.
`Berke describes a training phase during which variations of pre-equalizer
`coefficients of the transmitter (e.g., “equalization setting,” “FFE tap settings”) are
`run and performance characteristics (e.g., “eye height and eye width,” “BER”) of
`data transmission are recorded. Ex-1004, ¶20; Ex-1003, ¶59.
`For the training process, Berke teaches using a “best-effort” approach to
`update pre-equalizer coefficient values. Ex-1004, ¶3; see also ¶¶24-29, FIG. 3; Ex-
`1003, ¶60. To do so, first, Berke “determine[s] if the variability in equalization
`coefficients derived over different runs of the training algorithm is greater than an
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`equalization variation thr