14 978-4-900784-03-1 2007 Symposium on VLSI Technology Digest of Technical Papers
`2-2
`Bit Cost Scalable Technology with Punch and Plug Process
`for Ultra High Density Flash Memory
`H.Tanaka, M.Kido, K.Yahashi*, M.Oomura*, R.Katsumata, M.Kito, Y .Fukuzumi, M.Sato, Y.Nagata**,
`Y
`.Matsuoka, Y .Iwata, H.Aochi and A.Nitayama
`Center for Semiconductor Research & Development and Process & Manufacturing Engineering Center*,
`TOSHIBA Corporation, Semiconductor Company
`Toshiba Information Systems (Japan) Corporation**
`8, Shinsugita-cho Isogo-ku, Yokohama Kanagawa 235-8522 Japan
`Tel) +81-45-770-3274, Fax)+81-45-770-3210, E-mail) hiroyasu5.tanaka@toshiba.co.jp
`Abstract
`We propose Bit-Cost Scalable (BiCS) technology which
`realizes a multi-stacked memory array with a few constant
`critical lithography steps regardless of number of stacked
`layer to keep a continuous reduction of bit cost. In this
`technology, whole stack of electrode plate is punched
`through and plugged by another electrode material. SONOS
`type flash technology is successfully applied to achieve
`BiCS flash memory. Its cell array concept, fabrication
`process and characteristics of key features are presented.
`Introduction
`It is strongly demanded to keep a trend of increasing bit
`density and reducing bit cost of flash memories. To achieve
`that, aggressive scaling of the device dimension and multi-
`level-cell have been developed. However, bit cost will turn
`to rise up near future, as shown in figure 1, because process
`cost will increase more rapidly than shrink rate.
`One solution to avoid such situation is three dimensionally
`stacked array structures as reported in previous papers [1] [2],
`in which planar NAND structures are simply stacked. But
`there are two severe issues on those structures. One is that
`several critical lithography steps to make minimum feature
`size are necessary for each stacked layer. The other is that the
`area of driver transistors for control gates is multiplied by the
`number of layers. Dotted line in the figure 2 illustrates the
`estimated bit cost of three dimensionally stacked NAND,
`calculated by a simple formula inset in figure 2. It is
`important to note that the cost does not decrease or even
`increases due to a yield loss and an area penalty if the
`number of stacked layers is more than three.
`In this paper, a novel SONOS flash memory using a newly
`devised Bit-Cost Scalable (BiCS) technology which realizes
`a multi-stacked array with a few constant number of
`critical lithography process steps, without area penalty and
`with continuous reduction of bit cost as shown as solid line
`in figure 2 is proposed.
`Concept
`Figures 3(a), 3(b) and figure 4 show schematic Birds-eye
`view, top down view of BiCS flash memory array and the
`equivalent circuit, respectively. String of the cells is on the
`plugs located vertically in the holes punched through whole
`stack of the gate plates. Each plate acts as control gate except
`the lowest plate which takes a role of the lower select gate.
`Cell size of BiCS memory is 6F
`2/n, where n is the number of
`control gate plates. Bit density can be increased by adding
`more gate plates, while the number of the critical lithography
`steps remains constant because whole stack of control gates
`is punched with only one lithography step. A single cell is
`accessed by control gate on the string which is selected by a
`bit line and an row select line. The bottom of memory plug is
`connected to source diffusion formed on the silicon substrate.
`For the erase operation of BiCS Flash memory, hole current
`which is generated by GIDL near the lower select gate is
`used. Edges of control gate are processed to be stair-like
`structure for via holes which are connected to driver
`transistors. They are shared by several rows of strings, so
`that the area for driver transistors does not increase even if
`more control gates are stacked. Table I summarizes the
`comparison of BiCS Flash and simply stacked 3D NAND.
`Fabrication
` Figure 5 shows the fabrication sequence. Lower select gate
`transistor, memory string and upper select gate transistor are
`fabricated individually. Gate material is P+ poly-Si. Holes
`for transistor channel or memory plug are punched through
`and LPCVD TEOS film or ONO films are deposited. The
`bottom of dielectric films are removed by RIE and plugged
`by amorphous Si. Arsenic is implanted and activated for
`drain and also source of upper device. Figure 6 shows
`schematic cross sections of vertical FET and SONOS
`memory cell on poly-Si gate. It should be pointed out that
`ONO films are deposited in the opposite order of the
`conventional SONOS device, i.e. from LPCVD TEOS film
`as top block oxide (5nm), LPCVD SiN film (11nm) and
`LPCVD TEOS film as tunnel oxide (2.5nm). Edges of
`control gate are processed into stair-like structure by
`repeating of RIE and resist sliming as shown in figure 8. For
`minimizing disturb, whole stack of control gate and lower
`select line are etched to have a slit which separates a block of
`memory plugs from each other. Only upper select gate is cut
`into line pattern to work as row address selector. Via hole
`and BL are processed on the array and peripheral circuit
`simultaneously.
`Result and Discussion
`Figures 7(a) and 7(b) show the cross sectional SEM images
`of the successfully fabricated 90nm BiCS flash cell array and
`the stair-like structure at the edge of control gates. Figure
`7(c) is a top down photograph of n x 512k bit BiCS Flash
`macro.
`Id-Vg characteristics of select gate FET (L=150nm,
`) 90nm) is shown in figure 9. Subthreshold slope is 250
`mV/dec. In the case that Ioff is 30 pA, on-current is 2.4 PA.
`Figure 10 shows Id-Vg characteristics of the vertical SONOS
`FET after program and erase. Figure 11 shows the
`program/erase characteristics of SONOS FET. Endurance to
`1E5 cycles is shown in figure 12. Vth shift is less than 0.5V
`after 1E4 cycle. Data retention measured on SONOS FET at
`initial and after 1000 cycles of endurance are shown in figure
`13. 2.5V of Vth window is remains after 10years.
`Conclusion
`We have proposed BiCS flash memory as one of the most
`cost-effective memories to increase bit density. We have
`confirmed that this technology is a promising candidate for
`the Ultra High Density Memory.
`Reference
`[1]Soon -Moon Jung et al, IEDM Tech. Dig., pp 37-40, 2006.
`[2]
`Erh-Kun Lai et al, IEDM Tech. Dig., pp 41-44, 2006.
`Sandisk Technologies, Inc. - Ex. 1026, Page 000001
`IPR2025-01281 (Sandisk Technologies, Inc. v. Longitude Flash Memory Solutions Ltd.)
`
`
`
`
`
`
`
`152007 Symposium on VLSI Technology Digest of Technical Papers
`-1
`0
`1
`2
`3
`4
`5
`6
`7
`1E-07 1E-04 1E-01 1E+02
`Program time (s)
`Vth (V)
`14V
`15V
`-11V
`-12V
`-13V
`0
`1
`2
`3
`4
`5
`1E+00 1E+03 1E+06 1E+09
`Retention time (s)
`Vth (V) Solid: Initial
`Open: Endurance
`1E-12
`1E-11
`1E-10
`1E-09
`1E-08
`1E-07
`1E-06
`1E-05
`-3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
`Gate Voltage (V)
`Drain Current (A)
`Program
`Vpro = 11V
`1sec
`Erase
`Vera = -8V
`1sec
`1E-15
`1E-14
`1E-13
`1E-12
`1E-11
`1E-10
`1E-09
`1E-08
`1E-07
`1E-06
`1E-05
`-3 -2 -1 0 1 2 3 4 5
`Gate Voltage (V)
`Drain Current (A)
`Vd = 0.8 V
`)= 90 nm
`L= 150 nm
`-1
`0
`1
`2
`3
`4
`5
`6
`7
`1E+00 1E+02 1E+04
`P/E Cycle Endurance
`Vth (V)
`-40%/Year
`Litho tool cost up
`number of process steps up
`etc.
`Time
`Bit Cost
`p+
`0
`0.1
`0.2
`0.3
`0.4
`0.5
`0.6
`0.7
`0.8
`0.9
`1
`1.1
`1.2
`1 2 3 4 5 6 7 8 9 10111213141516
`Number of Layer
`Relative Bit Cost
`Fig. 1 Bit cost trend of flash memory.
`TABLE I
`Comparison of three dimensional flash memories.
`Fig. 3 (a) Birds-eye view of BiCS flash
`memory, (b) Top down view of BiCS flash
`memory array.
`(a)
`Fig. 4 Equivalent circuit of BiCS flash memory.
`Fig. 8 Fabrication Sequence of edge of control
`gates into stair-like structure.
`Fig. 13 Data retention of vertical SONOS.Fig. 12 Endurance of vertical SONOS.
`Fig. 2 Bit Cost scalability of three dimensional
`flash memory.
`BiCS Flash
`3D Stacked
`NAND
`3URV &RQV
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`1$1'
`([SDQVLRQRI
`&XUUHQW7HFKQRORJ\
`+LJKHU&RVW
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`2-2
`Bit Cost Scalable Technology with Punch and Plug Process
`for Ultra High Density Flash Memory
`H.Tanaka, M.Kido, K.Yahashi*, M.Oomura*, R.Katsumata, M.Kito, Y .Fukuzumi, M.Sato, Y.Nagata**,
`Y
`.Matsuoka, Y .Iwata, H.Aochi and A.Nitayama
`Center for Semiconductor Research & Development and Process & Manufacturing Engineering Center*,
`TOSHIBA Corporation, Semiconductor Company
`Toshiba Information Systems (Japan) Corporation**
`8, Shinsugita-cho Isogo-ku, Yokohama Kanagawa 235-8522 Japan
`Tel) +81-45-770-3274, Fax)+81-45-770-3210, E-mail) hiroyasu5.tanaka@toshiba.co.jp
`Abstract
`We propose Bit-Cost Scalable (BiCS) technology which
`realizes a multi-stacked memory array with a few constant
`critical lithography steps regardless of number of stacked
`layer to keep a continuous reduction of bit cost. In this
`technology, whole stack of electrode plate is punched
`through and plugged by another electrode material. SONOS
`type flash technology is successfully applied to achieve
`BiCS flash memory. Its cell array concept, fabrication
`process and characteristics of key features are presented.
`Introduction
`It is strongly demanded to keep a trend of increasing bit
`density and reducing bit cost of flash memories. To achieve
`that, aggressive scaling of the device dimension and multi-
`level-cell have been developed. However, bit cost will turn
`to rise up near future, as shown in figure 1, because process
`cost will increase more rapidly than shrink rate.
`One solution to avoid such situation is three dimensionally
`stacked array structures as reported in previous papers [1] [2],
`in which planar NAND structures are simply stacked. But
`there are two severe issues on those structures. One is that
`several critical lithography steps to make minimum feature
`size are necessary for each stacked layer. The other is that the
`area of driver transistors for control gates is multiplied by the
`number of layers. Dotted line in the figure 2 illustrates the
`estimated bit cost of three dimensionally stacked NAND,
`calculated by a simple formula inset in figure 2. It is
`important to note that the cost does not decrease or even
`increases due to a yield loss and an area penalty if the
`number of stacked layers is more than three.
`In this paper, a novel SONOS flash memory using a newly
`devised Bit-Cost Scalable (BiCS) technology which realizes
`a multi-stacked array with a few constant number of
`critical lithography process steps, without area penalty and
`with continuous reduction of bit cost as shown as solid line
`in figure 2 is proposed.
`Concept
`Figures 3(a), 3(b) and figure 4 show schematic Birds-eye
`view, top down view of BiCS flash memory array and the
`equivalent circuit, respectively. String of the cells is on the
`plugs located vertically in the holes punched through whole
`stack of the gate plates. Each plate acts as control gate except
`the lowest plate which takes a role of the lower select gate.
`Cell size of BiCS memory is 6F
`2/n, where n is the number of
`control gate plates. Bit density can be increased by adding
`more gate plates, while the number of the critical lithography
`steps remains constant because whole stack of control gates
`is punched with only one lithography step. A single cell is
`accessed by control gate on the string which is selected by a
`bit line and an row select line. The bottom of memory plug is
`connected to source diffusion formed on the silicon substrate.
`For the erase operation of BiCS Flash memory, hole current
`which is generated by GIDL near the lower select gate is
`used. Edges of control gate are processed to be stair-like
`structure for via holes which are connected to driver
`transistors. They are shared by several rows of strings, so
`that the area for driver transistors does not increase even if
`more control gates are stacked. Table I summarizes the
`comparison of BiCS Flash and simply stacked 3D NAND.
`Fabrication
` Figure 5 shows the fabrication sequence. Lower select gate
`transistor, memory string and upper select gate transistor are
`fabricated individually. Gate material is P+ poly-Si. Holes
`for transistor channel or memory plug are punched through
`and LPCVD TEOS film or ONO films are deposited. The
`bottom of dielectric films are removed by RIE and plugged
`by amorphous Si. Arsenic is implanted and activated for
`drain and also source of upper device. Figure 6 shows
`schematic cross sections of vertical FET and SONOS
`memory cell on poly-Si gate. It should be pointed out that
`ONO films are deposited in the opposite order of the
`conventional SONOS device, i.e. from LPCVD TEOS film
`as top block oxide (5nm), LPCVD SiN film (11nm) and
`LPCVD TEOS film as tunnel oxide (2.5nm). Edges of
`control gate are processed into stair-like structure by
`repeating of RIE and resist sliming as shown in figure 8. For
`minimizing disturb, whole stack of control gate and lower
`select line are etched to have a slit which separates a block of
`memory plugs from each other. Only upper select gate is cut
`into line pattern to work as row address selector. Via hole
`and BL are processed on the array and peripheral circuit
`simultaneously.
`Result and Discussion
`Figures 7(a) and 7(b) show the cross sectional SEM images
`of the successfully fabricated 90nm BiCS flash cell array and
`the stair-like structure at the edge of control gates. Figure
`7(c) is a top down photograph of n x 512k bit BiCS Flash
`macro.
`Id-Vg characteristics of select gate FET (L=150nm,
`) 90nm) is shown in figure 9. Subthreshold slope is 250
`mV/dec. In the case that Ioff is 30 pA, on-current is 2.4 PA.
`Figure 10 shows Id-Vg characteristics of the vertical SONOS
`FET after program and erase. Figure 11 shows the
`program/erase characteristics of SONOS FET. Endurance to
`1E5 cycles is shown in figure 12. Vth shift is less than 0.5V
`after 1E4 cycle. Data retention measured on SONOS FET at
`initial and after 1000 cycles of endurance are shown in figure
`13. 2.5V of Vth window is remains after 10years.
`Conclusion
`We have proposed BiCS flash memory as one of the most
`cost-effective memories to increase bit density. We have
`confirmed that this technology is a promising candidate for
`the Ultra High Density Memory.
`Reference
`[1]Soon -Moon Jung et al, IEDM Tech. Dig., pp 37-40, 2006.
`[2]
`Erh-Kun Lai et al, IEDM Tech. Dig., pp 41-44, 2006.
`Sandisk Technologies, Inc. - Ex. 1026, Page 000001
`IPR2025-01281 (Sandisk Technologies, Inc. v. Longitude Flash Memory Solutions Ltd.)
`
`
`
`
`
`
`
`152007 Symposium on VLSI Technology Digest of Technical Papers
`-1
`0
`1
`2
`3
`4
`5
`6
`7
`1E-07 1E-04 1E-01 1E+02
`Program time (s)
`Vth (V)
`14V
`15V
`-11V
`-12V
`-13V
`0
`1
`2
`3
`4
`5
`1E+00 1E+03 1E+06 1E+09
`Retention time (s)
`Vth (V) Solid: Initial
`Open: Endurance
`1E-12
`1E-11
`1E-10
`1E-09
`1E-08
`1E-07
`1E-06
`1E-05
`-3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
`Gate Voltage (V)
`Drain Current (A)
`Program
`Vpro = 11V
`1sec
`Erase
`Vera = -8V
`1sec
`1E-15
`1E-14
`1E-13
`1E-12
`1E-11
`1E-10
`1E-09
`1E-08
`1E-07
`1E-06
`1E-05
`-3 -2 -1 0 1 2 3 4 5
`Gate Voltage (V)
`Drain Current (A)
`Vd = 0.8 V
`)= 90 nm
`L= 150 nm
`-1
`0
`1
`2
`3
`4
`5
`6
`7
`1E+00 1E+02 1E+04
`P/E Cycle Endurance
`Vth (V)
`-40%/Year
`Litho tool cost up
`number of process steps up
`etc.
`Time
`Bit Cost
`p+
`0
`0.1
`0.2
`0.3
`0.4
`0.5
`0.6
`0.7
`0.8
`0.9
`1
`1.1
`1.2
`1 2 3 4 5 6 7 8 9 10111213141516
`Number of Layer
`Relative Bit Cost
`Fig. 1 Bit cost trend of flash memory.
`TABLE I
`Comparison of three dimensional flash memories.
`Fig. 3 (a) Birds-eye view of BiCS flash
`memory, (b) Top down view of BiCS flash
`memory array.
`(a)
`Fig. 4 Equivalent circuit of BiCS flash memory.
`Fig. 8 Fabrication Sequence of edge of control
`gates into stair-like structure.
`Fig. 13 Data retention of vertical SONOS.Fig. 12 Endurance of vertical SONOS.
`Fig. 2 Bit Cost scalability of three dimensional
`flash memory.
`BiCS Flash
`3D Stacked
`NAND
`3URV &RQV
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`1$1'
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`9HUWLFDO)(7
`0XOWL*DWH6WDFN5,(
`2F
`3F
`Fig. 9 Id-Vg characteristics of vertical
`transistor.
`Fig. 11 Program/Erase characteristics.
`(b)
`Fig. 10 Id-Vg characteristics for Program/Erase
`of vertical SONOS.
`1
`1
`1) (1
`
`¸
`¹
`·¨
`©
`§
`
`
`n
`v f
`Y
`AnC Cn
`...
`Resist
`Upper
`SG
`Control
`Gate
`(c)
`(b)
`poly-Si
`Body
`poly-Si
`Gate
`Charge Trap Layers
`(a)
`poly-Si
`Gate
`n+
`n-
`n+
`Cap SiN
`Lower
`SG
`Fig. 6 (a) Cross section of BiCS flash memory
`string, (b) Cross section of vertical SONOS cell,
`(c) Cross sections of vertical FET.
`Fig. 7 (a) Cross sectional SEM of BiCS flash
`memory string, (b) Cross sectional SEM of edge
`of control gates, (c) n x 512 kbit macro image.
`Upper
`SG
`Control
`Gate
`Lower
`SG
`(c)
`(b)(a)
`Lower
`SG
`Source
`Line
`Upper
`SG
`Bit Line
`Control
`Gate
`n : Number of stacked layers.
`Cf : Cost for common part.
`Cv : Cost per single layer.
`A : Area penalty rate per single layer.
`Y : Yield loss per single layer.
`poly-Si
`Body
`(1) STI (6) Control Gate Formation
`(2) Lower Select Gate (7) Slit
`(3) Lower SG Plug (8) Upper Select Gate
`(4) Control Gate Deposition (9) Upper SG Plug
`RIE
`RIE
`Slimming
`Bit Line
`Control
`Gate
`Lower
`SG
`Upper
`SG
`Bit Line
`Upper SG
`(row select line)
`(5) Memory Plug (10) BEOL
`Fig. 5 Fabrication sequence of BiCS flash
`memory.
`Memory array
`Sandisk Technologies, Inc. - Ex. 1026, Page 000002
`
`
`
`
`
`
`
`
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