IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Sandisk Technologies, Inc.,
`Petitioner,
`
`V.
`
`Longitude Flash Memory Solutions Ltd.,
`Patent Owner.
`
`Case No. IPR2025-01283
`
`U.S. Patent No. 9,929,240
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 9,929,240
`
`
`
`
`
`
`
`
`TABLE OF CONTENTS
`
`EXHIBIT LIST .ottt ettt ettt e et e esnaesnaeenneas 4
`L. TECHNICAL BACKGROUND ......oiiiiiiiiiieeieeeeeee et 8
`A. Floating Gate Flash Memory...........cccceeviiiiiiinieeniieeieecee e 8
`
`B. SONOS-Type Flash Memory.........ccccceeevieriiieniiieiieeieeeieeeiee e 11
`
`C. Well-Known Configurations of SONOS-Type Flash Memory.......... 13
`
`II. THE 240 PATENT ..ottt 14
`A. Overview of Alleged Invention...........cccceeevvieiiienciieniie e, 14
`
`B. Prosecution HiStOTY ........cccviiiiiiiiieiiieciie et 18
`
`C. Priofity Date ......cccoviieiiiiieiiee ettt e 21
`
`[I. FIELD AND LEVEL OF ORDINARY SKILL......cccccoteriiiiieieieeieeeee. 24
`IV. CLAIM CONSTRUCTION .....ccccieiiieiiiiieeieeieeiteste e 25
`A. “oxygen-rich nitride” and “oxygen-lean nitride”...............ccceeeenneennn. 25
`
`B. “high work function gate electrode™ ...........ccccoveieriiieiniieeeiiieeeeees 26
`
`C. “semiconductor material Structure™............ccevueerieeniiieniieniieeie e 27
`
`V. IDENTIFICATION OF CHALLENGE .......ccccoiviiiiiieeeeee e, 28
`A, Statutory GroUNdS........ccveeciiiiiiieniieeiee et e 28
`
`B. Relied-Upon Prior Art......c.cociiiiiiiiiieciieciieeee et 29
`
`1. Lee *255 (EX. 1004) .o 29
`
`2. Lee 961 (EX. 1005) c.eioiiiiiiieeieeieeeeeeeeeee e 31
`
`3. Fujiwara (EX. 1000) .....c.coviiriiiiiiiinieiieceeeee e 34
`
`4. Hwang (EX. 1048) ...ccuviiieiieeeeeeeee et 37
`
`
`
`
`
`
`
`
`VI. INVALIDITY GROUNDS. ..ottt 39
`
`A. Ground 1: Obviousness over Lee *255, Lee *961, and Fujiwara........ 39
`1. Independent claim 1........c.coooeviiieiiiiiiiii e 41
`2. Dependent Claims 3-7, 9, 11...cccoooiiiiiiiieee e 64
`
`B. Ground 2: Obviousness over Lee 255, Lee *961, Fujiwara, and
`HWANG. ...ttt e e s eetre e et e e e 73
`1 Independent Claim 12.........ccccevvviiiiiiiiniiecieeee e 74
`2 Dependent Claims 13-15......ccciiiiiiiiiiiiieeeeeeee e 81
`3 Independent Claim 16..........cccoevvviiiiieiiiieeieee e 84
`4 Dependent Claims 17, 18.....cccoioviiiiiiiiieeieeeeee e 92
`VII. CONCLUSION......cctttittetieiie ettt ettt ettt e seeseaeenbeeseesseesseeenseenseenseenns 94
`VIIL. STANDING .....oooiieiteiieeee ettt et ettt ste et eese e saessaeenseenseensee e 94
`I[X. MANDATORY NOTICES AND FEES ......coooiiieieeeeeeeeeee e 95
`CLAIM APPENDIX ..ottt ettt ettt sseeete b e e e saaesnseenneenes 97
`
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`
`
`EXHIBIT LIST
`
`Exhibit No. |Description
`
`1001 U.S. Patent No. 9,929,240 to Polishchuk et al. (“the *240 patent™)
`
`1002 Prosecution file history for the *240 patent, U.S. Patent
`Application No. 15/335,180 (“Pros. Hist.”)
`
`1003 Declaration Jack C. Lee
`
`1004 U.S. Patent Application Publication No. 2012/0068255 to
`Changhyun Lee, et al. (“Lee ’255”)
`
`1005 Korean Patent Publication No. 2011-0118961 to Gi1 Hong Lee et
`al. and Certified English Translation of Korean Patent Publication
`No. 2011-0118961 to Gi Hong Lee et al. (“Lee 961”)
`
`1006 U.S. Patent Application Publication No. 2006/0065919A1 to
`Ichiro Fujiwara (“Fujiwara”)
`
`1007 L. Lukasiak and A. Jakubowski, History of Semiconductors,
`Journal of Telecommunications and Information Technology,
`Vol. 3 (2010) (“Lukasiak™)
`
`1008 U.S. Patent No. 4,203,158 to Dov Frohman-Bentchkowsky, et al.
`(“Frohman-Bentchkowsky”)
`
`1009 U.S. Patent Application Publication No. 2006/0255399 to Ju-
`Hyung Kim, et al. (“Kim ’399”)
`
`1010 U.S. Patent Application Publication No. 2003/0122204 to
`Kazumasa Nomoto, et al. (“Nomoto”™)
`
`1011 U.S. Patent Application Publication No. 2009/0179253 to Levy, et
`al. (“Levy”)
`
`1012 U.S. Patent Application Publication No. 2011/0045647 to Jin-
`Hwa Heo, et al. (“Heo”)
`
`1013 U.S. Patent Application Publication No. 2011/0281429 to Udayan
`Ganguly, et al. (“Ganguly”)
`
`1014 US 2006/0113586 to Wang (“Wang ’5867)
`
`
`
`
`
`
`
`
`
`Exhibit No.
`
`Description
`
`1015
`
`U.S. Patent No. 6,897,533 to Jean Yee-Mei Yang, et al.
`(“Yang ’533”)
`
`1016
`
`U.S. Patent Application Publication No. 2006/0198189 to Hang-
`Ting Lue, et al. (“Lue 189”)
`
`1017
`
`U.S. Patent Application Publication No. 2009/0059676 to Shen
`Chih Lai, et al. (“Lai ’676”)
`
`1018
`
`Erh-Kun Lai, et al., A Multi-Layer Stackable Thin-Film Transistor
`(TFT) NAND-Type Flash Memory, Proceedings of the 2006
`International Electron Devices Meeting (IEEE Dec. 2006) (“Lai
`Article”)
`
`1019
`
`U.S. Patent Application Publication No. 2005/0006696A1 to
`Mitsuhiro Noguchi, et al. (“Noguchi”)
`
`1020
`
`Antonio Arreghini, et al., Experimental Characterization of the
`Vertical Position of the Trapped Charge in Si Nitride-Based
`Nonvolatile Memory Cells, IEEE Transactions on Electron
`Devices, Vol. 55, No. 5 (May 2008) (“Arreghini”)
`
`1021
`
`U.S. Patent Application Publication No. 2010/0157680A1 to
`Masaaki Higuchi, et al. (“Higuchi”)
`
`1022
`
`U.S. Patent Application Publication No. 2008/0128790 to Jin-Hyo
`Jung (“Jung”)
`
`1023
`
`U.S. Patent Application Publication No. 2003/0198106 to Jeong-
`Hyuk Choi (“Choi”).
`
`1024
`
`U.S. Patent Application Publication No. 2009/0026460 to Tien-
`Fan Ou, et al. (“Ou”)
`
`1025
`
`Falong Zhou, et al., VDNROM: A Novel Four-Bits-Per-Cell
`Vertical Channel Dual-Nitride-Trapping-Layer ROM for High
`Density Flash Memory Applications, Proceeding of 2006
`
`European Solid-State Device Research Conference (IEEE Sept.
`2006) (“VDNROM”)
`
`1026
`
`H. Tanaka, et al., Bit Cost Scalable Technology with Punch and
`Plug Process for Ultra High Density Flash Memory, 2007 IEEE
`Symposium on VLSI Technology (June 2007) (“Tanaka’)
`
`
`
`
`
`
`
`
`
`Exhibit No.
`
`Description
`
`1027 Toshiba Press Release, Toshiba Develops New NAND Flash
`Technology (June 12, 2007) (“Toshiba PR”)
`
`1028 U.S. Patent Application Publication No. 2010/0178759A1 to
`JinGyun Kim, et al. (“Kim >759”)
`
`1029 Moon Kyung Kim, et al., A Comparison of N+ Type and P+ Type
`Polysilicon Gate in High Speed Non-Volatile Memories, Material
`Research Society Symposium Proceedings, Vol. 997 (MRS 2007)
`(“Kim Article”)
`
`1030 U.S. Patent Application Publication No. 2006/0118858 to Sang-
`hun Jeon (“Jeon”)
`
`1031 U.S. Patent Application Publication No. 2005/0237809 to Yen-
`Hao Shih, et al. (“Shih™)
`
`1032 U.S. Patent Application Publication No. 2012/0276696 to Jun-
`Kyu Yang, et al. (“Yang *696”)
`
`1033 U.S. Patent Application Publication No. 2013/0270625 to Byong-
`hyun Jang, et al. (“Jang”)
`
`1034 U.S. Patent Application Publication No. 2012/0068247 to
`Changhyun Lee, et al. (“Lee ’247”)
`
`1035 U.S. Patent Application Publication No. 2012/0299086 to Jaegoo
`Lee (“Lee '086”)
`
`1036 U.S. Patent Application Publication No. 2011/0316064 to Jung
`Ho Kim, et al. (“Kim *064”)
`
`1037 U.S. Provisional Application No. 60/940,160 (*“’160 Provisional
`App.”)
`
`1038 Prosecution file history for the 434 patent (U.S. Application No.
`12/152,518) (“’434 Pros. Hist.”)
`
`1039 Prosecution file history for the *374 patent (U.S. Application No.
`13/288,919) (“’374 Pros. Hist.”)
`
`1040 Prosecution file history for the 537 patent (U.S. Application No.
`13/539,466) (“’537 Pros. Hist.”)
`
`1041 U.S. Patent No. 6,912,163 to Wei Zheng, et al. (“Zheng”)
`
`1042
`
`S.M. Sze and K. Ng, Physics of Semiconductor Devices (3" Ed.
`
`-6-
`
`
`
`
`
`
`
`
`
`Exhibit No.
`
`Description
`
`Wiley-Interscience 2007) (“Sze”)
`
`1043 U.S. Patent Application Publication No. 2010/0019312 to
`Katsuyuki Sekine, et al. (“Sekine”)
`
`1045 Declaration of June Munford
`
`1046 IEEE Declaration of Gordon MacPherson
`
`1047 Intentionally Omitted
`
`1048 U.S. Patent Application Publication No. 2012/0061744 to Sung-
`Min Hwang et al (“Hwang”)
`
`1049 Excerpts from The American Heritage Dictionary of the English
`Language (5" Ed. 2011) (American Heritage Excerpts)
`
`1050 US 2008/0272424 to Kim et al. (“Kim ’424”)
`
`1051 US 2007/0029625 to Lue et al. (“Lue ’625”)
`
`1052 US 2006/0008959 to Hagemeyer et al., (“Hagermeyer”)
`
`1053 Prosecution file history for the 336 patent (U.S. Application No.
`15/864,832) (“’336 Pros. Hist.”)
`
`1054 Infringement Contentions from SanDisk Corp. v. IPValue
`Management, Inc., et al., No. 25-cv-02389 (N.D. Cal.)
`(Infringement Contentions)
`
`1055 Excerpts from Merriam-Webster's Collegiate Dictionary (11th Ed.
`2003) (Merriam-Webster Excerpts)
`
`1056 Excerpts from New Oxford American Dictionary (3rd Ed. 2010)
`(New Oxford Excerpts)
`
`1057 US 5,998,826 to Hung et al. (“Hung”)
`
`1058 US 2009/0268522 to Maejima (“Maejima’)
`
`1059 EP 0 810 667 A2 by Hyundai (“Hyundai”)
`
`1060 US 2003/0135690 to Lee et al. (“Lee *690™)
`
`
`
`
`
`
`
`
`
`Petitioner respectfully requests that the Board institute inter partes review
`and cancel claims 1, 3-7, 9, and 11-18 (the “Challenged Claims”) of U.S. Patent
`No. 9,929,240 (the *240 patent).
`
`I. TECHNICAL BACKGROUND
`
`The 240 patent is directed generally to non-volatile memory (or “NVM”),
`which is a type of computer memory that can retain stored information even after
`power is removed. Ex. 1001 (°240 patent), 1:33-37; Ex. 1003, 9948-49. More
`specifically, the *240 patent purports to improve the data retention capabilities of
`silicon—oxide—nitride—oxide-silicon (“SONOS”) flash memory devices. Ex. 1001
`(’240 patent), 1:65-2:7, 2:38-50; Ex. 1003, qq18-19, 56. As discussed below,
`SONOS-type flash memory devices were well-known at the time of the application
`for the ’240 patent.
`
`A. Floating Gate Flash Memory
`
`Flash memory is a type of semiconductor NVM that was invented in the
`1980s. Ex. 1003, 950. Early flash memory devices were based on a “floating gate”
`metal-oxide—semiconductor field-effect transistor (MOSFET) design. /d., §51. The
`design included an electrically insulated gate that “floats” between two oxide
`
`layers, as shown here:
`
`
`
`
`
`
`
`
`27
`
`28
`18 26
`\
`AN
`N LR0GRAMN GATE.
`30~ 17
`\\ FLOATING \\NCATE
`1/ '
`
`- 7RAT
`\\J\U\‘S\{ &4\\5\-\\
`
`Ex. 1008 (Frohman-Bentchkowsky), Fig. 1; see also id., 4:1-31; Ex. 1003, §51.
`
`Because the floating gate is electrically isolated, any electron placed in the
`
`gate will be trapped there after voltage is removed. See, e.g., Ex. 1008 (Frohman-
`
`Bentchkowsky), 1:18-23, 3:55-57, 5:5-7; Ex. 1003, 952. This allows a floating gate
`
`transistor to function as NVM. In the simplest example, the presence of sufficient
`
`electrons in the floating gate will cause the memory to be read as a “1,” while the
`
`absence of electrons in the floating gate will cause the memory to be read as a “0.”
`
`Ex. 1013 (Ganguly), 1:20-23.
`
`
`
`
`
`
`
`
`During a program/write operation, electrons can be placed in the floating
`gate using a “tunneling” procedure, where an electric field is applied that causes
`
`electrons from the substrate to “tunnel” through an oxide layer to the floating gate:
`
`write [
`
`Control gate
`oxide layer
`
`Tunriel ¢xid? laller
`
`urce Drain
`
`substrate g
`
`Ex. 1003, 953.
`During an erase/wipe operation, the opposite electric field is applied,
`
`causing the electrons trapped in the control gate to “tunnel” back to the substrate:
`
`-10-
`
`
`
`
`
`
`
`
`wipe
`
`Control gate
`oxide layer
`
`Tunnel ¢xid» layer
`
`substrate
`
`Ex. 1003, 954.
`
`B. SONOS-Type Flash Memory
`
`By the early 2000s, flash memory devices were commonly designed to use
`charge-trapping SONOS technology. See, e.g., Ex. 1010 (Nomoto), Fig. 3H,
`[0032]-[0038]; Ex. 1003, 955. As noted above, “SONOS” is a reference to the
`layers of the NVM device: silicon-oxide-nitride-oxide-silicon. SONOS-type flash
`memory is similar to floating gate memory except that a non-conductive silicon
`nitride layer is used to trap charges rather than the floating gate. Ex. 1003, 456. An
`example of a “conventional” SONOS memory device is provided in Kim ’399 (Ex.
`
`1009), which was filed on February 15, 2006:
`
`-11-
`
`
`
`
`
`
`
`
`FIG. 1 (CONVENTIONAL ART)
`
`100
`/125
`120
`NN\ N\ gty
`} \ +—110
`+—105
`- e
`
`Ex. 1009 (Kim ’399), Fig. 1, [0006]-[0008]; Ex. 1003, 956.
`
`As reflected above, a conventional SONOS memory device in 2006
`included: (i) a silicon semiconductor substrate 105 with source/drain regions 110;
`(i1) an oxide tunnel insulating film 115 (green); (ii1) a nitride charge trapping film
`120 (red); (iv) a silicon oxide blocking insulating film 125 (blue); and (v) silicon
`control gate 130 (gray). Ex. 1003, 4956-57.
`
`Like floating gate memory, SONOS charge trap memory transistors work by
`“tunneling” electrons into and out of the nitride charge trapping layer. Ex. 1003,
`958. During a programming step, a positive voltage is applied to the gate, which
`causes electrons from the substrate to tunnel through the tunnel oxide and into the
`
`nitride storage layer:
`
`-12-
`
`
`
`
`
`
`
`
`? +V
`Polysilicon gate
`
`Oxide blocking layer
`Nitride storage layer o000O0CGO
`Oxige tunneling layer
`
`000000
`
`P-Si
`
`Silicon substrate
`
`Ex. 1003, 958.
`
`When the voltage is removed, the electrons remain in the nitride storage
`layer. Ex. 1003, 958. To perform an erase/clear step, a negative voltage is applied
`to the gate, which causes electrons to tunnel from the nitride storage layer back
`through the tunnel oxide into the silicon substrate. /d., 459.
`
`C. Well-Known Configurations of SONOS-Type Flash Memory
`
`Prior to July 2012, a person of ordinary skill in the art (a “POSITA”) would
`have been familiar with several routine configurations of SONOS-type flash
`memory devices and the predictable benefits of those configurations. See Ex. 1003,
`Part II1.C.4-7. For example, a POSITA would have been familiar with:
`
`o Configuring SONOS devices to include multiple charge storage layers,
`
`such as SONNOS configurations. Ex. 1003, 9960-66 (discussing Ex.
`
`-13-
`
`
`
`
`
`
`
`
`1011 (Levy), Ex. 1010 (Nomoto), Ex. 1012 (Heo), Ex. 1009 (Kim ’399),
`Ex. 1013 (Ganguly), and Ex. 1014 (Wang)).
`
`Configuring SONOS devices to include an intermediate oxide layer
`between two nitride layers, such as SONONOS configurations. Ex. 1003,
`967-72 (discussing Ex. 1015 (Lue ’189), Ex. 1015 (Yang ’533), Ex.
`1017 (Lai ’676), Ex. 1018 (Lai Article), Ex. 1019 (Noguchi), and Ex.
`1020 (Arreghini)).
`
`Using high work function materials for the gate electrodes of
`SONOS/SONNOS/SONONOS devices. Ex. 1003, 9989-91 (discussing
`Ex. 1029 (Kim Article), Ex. 1015 (Lue ‘189), Ex. 1017 (Lai ‘676), Ex.
`1012 (Heo), Ex. 1030 (Jeon), and Ex. 1031 (Ou)).
`
`Arranging SONOS/SONNOS/SONONOS devices to have vertical
`configurations. Ex. 1003, 9973-88 (discussing Ex. 1021 (Higuchi), Ex.
`1028 (Kim ‘759), Ex. 1023 (Choi), Ex. 1031 (Ou), Ex. 1022 (Jung), Ex.
`1025 (VDNROM), Ex. 1043 (Sekine), Ex. 1026 (Tanaka), and Ex. 1027
`(Zhou)).
`
`THE °240 PATENT
`
`Overview of Alleged Invention
`
`The ’240 patent issued on March 27, 2018 from an application filed on
`
`October 26, 2016. See Ex. 1001 (°240 patent), 000001. The 240 patent purports to
`
`improve the data retention capabilities of SONOS memory devices using an
`
`“oxide-nitride-nitride-oxide (ONNO) stack” with a “multi-layer charge-trapping
`
`region.” Ex. 1001 (°240 patent), 1:65-2:7, 2:38-50; Ex. 1003, q918-19, 55. Figure
`
`-14-
`
`
`
`
`
`
`
`
`4A, annotated below, depicts one embodiment of the ONNO stack of the ’240
`
`patent:
`
`402 ‘j
`4 | -— Oxygen-lean second nitride layer 422b
`1 w422 |
`
`i
`: 3 | +— Oxygen-rich first nitride layer 422a
`i
`. 4— Tunnel dielectric layer 416
`
`Source and drain
`(S/D) region 410
`
`AY_ Source and drain
`(S/D) region 410
`
`FIG. 4A
`
`Ex. 1001 (°240 patent), Fig. 4A; see also Ex. 1003 94920-21.
`
`As reflected above, figure 4A includes “one or more diffusion regions 410”
`(gold) that are ‘“‘separated by a channel region 412” (purple). Ex. 1001 (°240
`patent), 8:55-58; Ex. 1003, 922. In this figure, the ONNO stack is aligned above
`the horizontal channel region. /d. The stack includes “tunnel dielectric layer 416
`(green), “multi-layer charge trapping region 422” (red), “blocking dielectric layer
`420” (blue), and “high work function gate electrode 414 (gray). Ex. 1001 (°240
`
`patent), 8:52-10:15; Ex. 1003, 922.
`
`-15-
`
`
`
`
`
`
`
`
`The ’240 patent further states that the ONNO stack may be modified to have
`an intermediate oxide layer between the two nitride layers, forming an ONONO
`structure. Ex. 1001 (°240 patent), Fig. 4B, 10:5-12; Ex. 1003, 924. An example of
`this configuration, with the intermediate oxide layer annotated in orange, is shown
`
`in figure 4B:
`
`,,,,,,,,
`
`» ¢ e 4 8 2
`o v ¢ J = s P
`L S R L R R |
`L ‘¢ ¢ 4 F N Y T B B
`7 . ‘. D : . : 4
`A A I I L |
`7 R R I B R R R B A A I A e |
`P S P v :
`i
`
`a'll'l""""lal‘i'l"
`402 & [RAASLACEATUANAS VAN o
`N\ R 2 T +&— Oxygen-lean second nitride layer 422b
`
`P T ) [ L T
`' L L I T . L L S .
`
`- ey v
`DT T A S N T
`RN
`
`’ ! - b ' 1 < \ - - -
`RS UL LT L LA 8L L e Oxide anti-tunneling layer 422c
`
`P T T T A S R
`
`Ex. 1001 (°240 patent), Fig. 4B; Ex. 1003, 924.
`
`While figures 4A and 4B depict horizontally-oriented memory transistors,
`the *240 patent states that there are alternative implementations of the ONNO (or
`ONONO) stack. Ex. 1001 (240 patent), 8:47-20:3; Ex. 1003, 926-29. For
`
`example, figures 8A and 8B are directed to a vertically-oriented (‘“three-
`
`-16-
`
`
`
`
`
`
`
`
`dimensional” or “3D”) memory transistor structure with an ONONO stack. Ex.
`1001 (240 patent), Figs. 8-10, 17:11-20:3; Ex. 1003, 9930-31. Figure 8 A shows a
`
`transistor with a channel region (purple) that extends vertically between diffusion
`
`regions (gold):
`/ Source 304
`800 -~ N
`\ i SRR / Multilayer charge trapping region 810
`804
`
`T\
`
`Blocking oxide layer 812
`
`Tunnel dielectric layer 808 =% 808
`
`High work function gate
`electrode 814
`
`Drain 806
`
`FIG. 8A
`
`Ex. 1001 (240 patent), Fig. 84, 17:10-18:8; Ex. 1003, 930.
`
`Figure 8B depicts a magnified view of the cross section of the ONONO
`
`stack from figure 8A:
`
`-17-
`
`
`
`
`
`
`
`
`Oxide anti-tunneling
`
`Tunnel dielectric layer 810c Blocking oxide
`layer 808 1 layer 812
`fR— .l. AR . p————— V—p—— -
`' :
`' :
`H :
`H :
`H :
`' :
`. ‘
`{ ;
`. ‘
`s 810a g1ob | 812 |i
`. ‘
`. '
`H :
`. ‘
`. ‘
`i | [s808 s810c :
`N B IS 1 SO IS i
`Oxygen-rich first Oxygen-lean second
`nitride layer 810a nitride layer 810b
`
`Ex. 1001 (°240 patent), Fig. 8B, 17:49-56; 4932-33.
`
`Figures 9 and 10 depict methods of fabricating vertical channel memory
`devices, including a “gate first” method (Fig. 9) and “gate last” method (Fig. 10).
`Ex. 1001 (°240 patent), 3:30-33, 18:14-19:14; Ex. 1003, q934-35.
`
`B. Prosecution History
`
`Igor Polishchuk, Sagy Charel Levy, and Krishnaswamy Ramkumar
`(collectively, “the Applicants™) filed the application for the 240 patent on October
`26, 2016, which included application claims 1-20. Ex. 1002 (Pros. Hist.),
`00004247. Subsequently, the Applicants submitted information disclosure
`statements listing more than 500 prior art references (id., 000148-182, 000620-631,
`001079-1086, 001479-1483, 001707-1710, 001741-1744, 001762-1765, 001840-
`
`1843, 001874-1877) and amended the application to replace original claims 1-20
`18-
`
`
`
`
`
`
`
`
`with new claims 21-40 (id., p.104-110). After the preliminary amendment,
`Applicants advanced three independent claims: 21, 33, and 38 (corresponding to
`issued claims 1, 12, and 16). Ex. 1002 (Pros. Hist.), 000105-109, 001827; Ex.
`1003, 9936-38.
`
`The Examiner rejected independent application claims 21, 33, and 38,
`finding it would have been obvious to a POSITA to combine NVM references
`teaching multi-layer charge trapping regions, high work function gate electrodes,
`and integrated MOS logic transistors. Ex. 1002 (Pros. Hist.), 001616-1628; Ex.
`1003, 940. While rejecting the independent claims, the Examiner allowed the
`dependent claims reciting vertical channels (25, 34, 36, and 39). Id., 001629. Ex.
`1003, 9938-39. Although SONOS devices with vertical channels were well-known
`in the prior art (see Ex. 1003, 9973-88), the Examiner did not apply any of those
`references during examination.
`
`Rather than disputing the Examiner’s obviousness determinations with
`respect to the independent claims, Applicants filed amendments to those claims.
`Ex. 1002 (Pros. Hist.) (Pros. Hist.), 001722-1738. Applicants amended claims 33
`and 38 (issued claims 12 and 16) to add vertical channel limitations. id., 001726-
`1728, 001735-1736. Applicants amended claim 21 (issued claiml) to require that
`the multi-layer charge trapping region include an intermediate “anti-tunneling
`
`layer.” Id., 001724, 001731-1735; Ex. 1003, q941-42.
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`On October 4, 2017, the Examiner issued a Notice of Allowability for
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`application claims 21-40. Ex. 1002 (Pros. Hist.), 001793-1801; Ex. 1003, 943. In
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`providing the reasons for allowance, the Examiner stated the following elements
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`were absent from the prior art:
`
`For application claim 21 (issued claim 1), the prior art “discloses all
`limitations of claim 21 except for . . . ‘an anti-tunneling layer disposed
`between the first and second dielectric layers, wherein the anti-tunneling
`layer includes an oxide layer.” Ex. 1002 (Pros. Hist.), 001799; Ex. 1003,
`44.
`
`For application claim 33 (issued claim 12), the Examiner stated that the
`prior art discloses everything except for “the channel is vertical and
`oriented substantially perpendicular to a semiconductor material structure,
`and a tunnel dielectric layer, a multi-layer charge trapping layer, and a
`blocking dielectric layer disposed between the gate structure and the
`
`channel.” Ex. 1002 (Pros. Hist.), 001799-1800; Ex. 1003, 945.
`
`For application claim 38 (issued claim 16), the Examiner stated that the
`prior art discloses everything except for “the channel is vertical and
`oriented substantially perpendicular to a semiconductor material structure;
`and a metal oxide semiconductor (MOS) logic device including a gate
`oxide layer and a second high work function gate electrode disposed
`
`thereon.” Ex. 1002 (Pros. Hist.), 001800; Ex. 1003, 946.
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`C. Priority Date
`
`The earliest possible priority date for the Challenged Claims of the 240
`patent is July 1, 2012, the date of the filing of U.S. Patent Application No.
`13/539,466, which issued as U.S. Patent No. 8,633,573. Ex. 1003, 947.
`
`On its face, the 240 patent purports to claim priority to a provisional patent
`application filed on May 25, 2007 through a chain of related applications
`
`represented in the following chart:
`
`App No. Filing Date | Patent No.
`A | 60/940,160 | 5/25/2007 | n/a “the 160 provisional”
`B | 12/152,518 | 5/13/2008 | 8,063,434 | “the 434 patent”
`C | 13/288,919 | 11/3/2011 8,859,374 | “the *374 patent;” divisional of B
`D | 13/539,466 | 7/1/2012 8,633,537 | “the ’537 patent;” continuation-in-
`Part of C
`E | 14/159,315 | 1/20/2014 9,093,318 | “the 318 patent;” continuation of D
`F | 14/811,346 | 7/28/2015 9,502,543 | “the ’543 patent;” continuation of E
`G | 15/335,180 | 10/26/2016 |9,929,240 | “the *240 patent;” continuation of F
`
`Ex. 1001 (°240 patent), 1:8-22; Ex. 1003, 4997-98.
`
`To obtain the benefit of the filing date of the earlier related applications, the
`Challenged Claims must have written description support those applications. Ariad
`Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010); Augustine
`
`Med., Inc. v. Gaymar Indus., Inc., 181 F.3d 1291, 1302-03 (Fed. Cir. 1999) (“A
`
`21-
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`
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`CIP application contains subject matter from a prior application and may also
`contain additional matter not disclosed in the prior application . . . Different claims
`of such an application may therefore receive different effective filing dates.”). The
`written description support must have “sufficient detail that one skilled in the art
`can clearly conclude that the inventor invented the claimed invention as of the
`filing date sought.” Anascape, Ltd. v. Nintendo of Am., Inc., 601 F.3d 1333, 1335
`(Fed. Cir. 2010). The question is whether the subject matter is disclosed in the
`specification, not whether the subject matter would have been obvious. Lockwood
`v. Am. Airlines, Inc., 107 F.3d 1565, 1571-1572 (Fed. Cir. 1997).
`
`Here, the Challenged Claims each include limitations that lack written
`support in the applications filed prior to July 1, 2012—the ’160 Provisional
`Application (filed May 25, 2007), the *518 Application (filed May 13, 2008), and
`the ’919 Application (filed November 3, 2011) (collectively, the “Earlier
`Applications™). Ex. 1003, 999.
`
`Independent claim 1 requires a memory device that includes “an anti-
`tunneling layer disposed between the first and second dielectric layers, wherein the
`anti-tunneling layer includes an oxide layer.” Ex. 1001 (°240 patent), claim 1; Ex.
`1003, 9100. The Earlier Applications do not provide written description support for
`this limitation. To the contrary, the Earlier Applications disclose first and second
`
`dielectric layers that are adjacent to each other without any intermediate layer
`
`00
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`between. See, e.g., Ex. 1037 (160 Provisional App.), 9-10 (Fig. 1); Ex. 1038 (°434
`Pros. Hist.), 000137-139 (Fig. 2A-3) ; Ex. 1039 (°’374 Pros. Hist), 000197-199
`(Figs. 2A-3); Ex. 1003, 99101-102. Applicants first added figures and written
`description of an intermediate anti-tunneling layers in the continuation-in-part
`application for the ’537 patent, which was filed on July 1, 2012. See Ex. 1040
`(’537 Pros. Hist.), pp. 218-278; compare id. with Ex. 1038 (434 Pros. Hist.), pp.
`pp. 111-139 and Ex. 1039 (374 Pros. Hist.), pp. 158-199.
`
`Independent claims 12 and 16 require memory devices with channels,
`“wherein the channel is vertical and oriented substantially perpendicular to a
`semiconductor material structure.” Ex. 1001 (°240 patent), claims 12, 16. The
`Earlier Applications are also silent as to this claim limitation. See Ex. 1037; Ex.
`1038; Ex. 1039 (’374 Pros. Hist.); Ex. 1003, 49103-105. The Earlier Applications
`exclusively disclose horizontally-oriented semiconductor devices. See, e.g., Ex.
`1038 (’434 Pros. Hist.), 000139; Ex. 1003, 4104. The Applicants first added
`subject matter concerning vertically-oriented memory devices—e.g., figures 8-10
`of the ’240 patent—on July 1, 2012 in connection with a continuation-in-part
`application that later issued as the ’537 patent. See Ex. 1040 (’537 Pros. Hist.),
`000218-278; compare id. with Ex. 1038 (434 Pros. Hist.), 000111-139; Ex. 1039
`
`(’374 Pros. Hist.), 000158-199; Ex. 1003, 4105.
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`Because features of the independent claims of the *240 patent (claims 1, 12,
`and 16) are not disclosed in any of the Earlier Applications, the earliest possible
`priority date for the 240 patent is July 1, 2012. Ex. 1003, 9106.
`
`III. FIELD AND LEVEL OF ORDINARY SKILL
`
`The °240 patent is in the field of non-volatile semiconductor memory. See,
`e.g., Ex. 1001 (°240 patent), 1:26-29; Ex. 1003, q107. Each of the Challenged
`Claims i1s directed to either a “semiconductor device, comprising a memory
`device” (see id., claims 12, 16) or a “memory device” (see id., claim 1).
`
`A POSITA in the relevant field as of July 1, 2012 would have had at least
`(1) a master’s degree in electrical engineering, materials science, physics, or a
`related degree, and at least 3-5 years of experience in semiconductor devices and
`fabrication technologies; or (2) a bachelor’s degree in electrical engineering,
`materials science, physics, or a related degree, and at least 5-6 years of experience
`in semiconductor devices and fabrication technologies. Ex. 1003, 44105-106.
`
`In view of the types of problems encountered in the art and prior art
`solutions to those problems, a POSITA in the relevant timeframe above would
`have been familiar with:
`
`o Floating gate flash memory technology (see Ex. 1003, 4950-54, 107);
`
`o The structure and composition of SONOS-type memory devices (see id.,
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`1955-59, 107);
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`4.
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`o SONNOS and SONONOS configurations of SONOS-type memory
`devices (see id., §973-88, 107);
`
`o Vertically-oriented configurations of SONOS-type memory transistors,
`
`including 3D NAND structures (see id., 9973-88, 107); and
`
`o The use of high work function materials, such as p+ doped polysilicon, to
`form gate electrodes for SONOS-type memory devices (see id., §Y89-91,
`107).
`
`IV. CLAIM CONSTRUCTION
`A. “oxygen-rich nitride” and “oxygen-lean nitride”
`
`Independent claims 1, 12, and 16 recite “oxygen-lean” and ‘“oxygen-rich”
`nitride layers. The ’240 patent does not provide a general definition of these terms,
`but does provide an example of “oxygen-rich” and “oxygen-lean” in connection
`with the embodiment depicted in figure 6:
`
`By oxygen-rich it is meant wherein a concentration of
`oxygen in the oxygen-rich first nitride layer 616a is from
`about 15 to about 40%, whereas a concentration of
`oxygen in [an] oxygen-lean second nitride layer 616b is
`
`less than about 5%.
`
`Ex. 1001 (°240 patent), 13:53-57; Ex. 1003, §9109-110.
`Based on this statement, a POSITA would have understood that (i) a nitride
`
`layer with about 5% or less oxygen is within the bounds of “oxygen-lean; and (ii)
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`a nitride layer with about 15% or more oxygen is within the bounds of “oxygen-
`rich.” Ex. 1003, q111.
`
`B. “high work function gate electrode”
`
`Independent claims 12 and 16 (and dependent claims 9 and 11) of the 240
`patent require “a high work function gate electrode.” This term was well-known to
`a POSITA prior to July 2012. Ex. 1003, 4489-91, 112. The 240 patent uses “high
`work function gate electrode” according to its ordinary meaning: “[b]y high work
`function gate electrode it is meant that the minimum energy needed to remove an
`electron from the gate electrode is increased.” Ex. 1001 (°240 patent), 4:1-3. The
`’240 patent states that polysilicon doped with p-type impurities (e.g., boron) is an
`example of a high work function gate material. Ex. 1001 (°240 patent), 7:27-35;
`Ex. 1003, 9113. Again, this is consistent with a POSITA’s understanding of the
`term prior to July 2012. Ex. 1012 (Heo), [0046]; Ex. 1017 (Lai ‘676), [0067],
`[0072]; Ex. 1041 (Zheng), 5:36-37, 5:52-62; Ex. 1003, 9112, 229, n. 8.
`
`A POSITA thus would have understood “high work function gate electrode”
`in the context of the *240 patent to have its ordinary meaning, which encompasses
`gate electrodes comprised of, for example, polysilicon doped with p-type
`impurities and other materials known as high work function materials. Ex. 1012
`(Heo), [0046]; Ex. 1017 (Lai ‘676), [0067], [0072]; Ex. 1041 (Zheng), 5:36-37,
`
`5:52-62; Ex. 1003, 9114, 229.
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`C. “semiconductor material structure”
`
`Independent claims 12 and 16 and dependent claims 3, 4, 5, 14, 15, and 17
`recite various limitations in relation to a “semiconductor material structure.” The
`claims do not set forth what makes up the ‘“semiconductor material structure.”
`While the *240 patent’s specification explains that a substrate may be formed of a
`“semiconductor material” (Ex. 1001 (°240 patent), 4:45-52) it does not explicitly
`set forth what else, if anything, would be included in a “semiconductor material
`structure.” Ex. 1003, qq115-116.
`
`During the prosecution of a descendent of the 240 patent, Applicants stated
`that:
`
`the words and phrases “memory device” and
`
`b
`
`“semiconductor material structure,” as used throughout
`
`the present claims and application are synonymous with
`the words and phrases “memory transistor” and
`“semiconductor substrate” - which are explicitly
`supported in connection with Figs. 3 and 8-10, in the
`
`above cited paragraphs.
`
`Ex. 1053 (°336 Pros. Hist.), 137); Ex. 1003, q117. This understanding is also
`consistent with how “semiconductor material structure” is used in the claims of the
`’240 patent. Ex. 1003, 9118-125; Ex. 1001 (°240 patent), claims 12, 16, 5, 14, 17,
`
`2,4 Figs. 9, 3, 6A, 7A, 18:9-22. Further, Patent Owner has identified a silicon
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`substrate as a “semiconductor material structure” in parallel litigation. Ex. 1054
`(Infringement Contentions), 000017-18.
`
`In view of the prosecution history, a POSITA would have considered
`“semiconductor material structure” to mean semiconductor substrate. Ex. 1003,
`I9118-125.
`
`V. IDENTIFICATION OF CHALLENGE
`A. Statutory Grounds
`
`Petitioner requests inter partes review and cancelation of the Challenged
`
`Claims on the following grounds:
`
`Grounds Claims Statutory Basis | Prior Art
`
`1 1,3-7,9,11 § 103 Obviousness | Lee 255, Lee 961
`
`and Fujiwara
`
`2 12-18 § 103 Obviousness | Lee ’255, Lee *961,
`
`Fujiwara, and Hwang
`
`Under 35 U.S.C. § 103, a party may not obtain a patent “if the differences
`between the subject matter sought to be patented and the prior art are such that the
`subject matter as a whole would have been obvious” to a POSITA at the time of
`the invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). “The
`
`combination of familiar elements according to known methods is likely to be
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`obvious when it does no more than yield predictable results.” Id. As discussed
`below, the challenged claims of the 240 patent are obvious under § 103.
`
`B. Relied-Upon Prior Art
`1. Lee 255 (Ex. 1004)
`
`Lee ’255 i1s a U.S. Patent Application Publication that was published on
`March 22, 2012 from an application filed on August 29, 2011. Ex. 1004 (Lee
`’255), 000001. Lee 255 is prior art under § 102(a) because the invention was
`described in a U.S. patent application that was filed and published before July 1,
`2012. Ex. 1003, 9127.
`
`Lee ’255 was not cited or considered during prosecution of the 240 pate