(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2013/0027843 A1
`SEO et al.
`(43) Pub. Date:
`Jan. 31, 2013
`
`US 20 1 30027843Al
`
`(54) MULTI-LAYERED CERAMIC ELECTRONIC
`COMPONENT
`
`(52) U.S.Cl.
`
`.................................................. .. 361/321.2
`
`(75)
`
`Inventors: Byung Kil SEO, Suwon (KR); Byung
`Sung KANG, Suwon (KR)
`
`(57)
`
`ABSTRACT
`
`(73) Assignee: Samsung Electro-Mechanics Co., Ltd.
`
`(21) Appl. No.: 13/558,883
`
`(22)
`
`Filed:
`
`Jul. 26, 2012
`
`(30)
`
`Foreign Application Priority Data
`
`Jul. 26, 2011
`
`(KR) ...................... .. 10-2011-0074042
`
`Publication Classification
`
`(51)
`
`Int. Cl.
`H01G 4/12
`
`(2006.01)
`
`There is provided a multi-layered ceramic electronic compo-
`nent including: a ceramic main body including a dielectric
`layer; and inner electrode layers disposed to face each other,
`with the dielectric layer interposed therebetween,
`in the
`ceramic main body, wherein when an average thickness ofthe
`dielectric layer is defined as td, the average thickness td is
`td:15 um, and the number of dielectric grains per 10 um
`within the dielectric layer is 15 or greater. Since a uniform,
`thick dielectric layer can be obtained with fine dielectric
`powder, a high voltage multi-layered ceramic electronic com-
`ponent having excellent withstand voltage characteristics can
`be implemented.
`
`000001
`
`AVX CORPORATION
`
`Exhibit 1016
`
`PGR2017-00010
`
`Exhibit 1016
`PGR2017-00010
`AVX CORPORATION
`
`000001
`
`

`

`Patent Application Publication
`
`Jan. 31, 2013 Sheet 1 of 3
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`US 2013/0027843 A1
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`10
`
`B'
`
`FIG.
`
`1
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`000002
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`000002
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`

`Patent Application Publication
`
`Jan. 31, 2013 Sheet 2 of 3
`
`US 2013/0027843 A1
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`
`
`
`
`
`MU"
`
`
`
`1-0/zm"
`
`FIG. 3
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`000003
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`000003
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`Patent Application Publication
`
`Jan. 31, 2013 Sheet 3 of 3
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`US 2013/0027843 A1
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`
`
`1_Oum"
`
`FIG. 5
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`000004
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`000004
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`

`US 2013/0027843 A1
`
`Jan. 31,2013
`
`MULTI-LAYERED CERAMIC ELECTRONIC
`COMPONENT
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application claims the priority ofKorean Patent
`Application No. 10-2011-0074042 filed on Jul. 26, 2011, in
`the Korean Intellectual Property Office, the disclosure of
`which is incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`[0002]
`[0003] The present invention relates to a high pressure
`multi-layered
`ceramic
`electronic
`component
`having
`improved withstand voltage characteristics.
`[0004]
`2. Description of the Related Art
`[0005] As electronic products have tended to be reduced in
`size, multi-layered ceramic electronic components have
`accordingly been required to be reduced in size and yet have
`a large capacity.
`[0006] Thus, efforts have been undertaken to make dielec-
`tric and inner electrodes thinner and multi-layered through
`various methods, and recently, multi-layered ceramic elec-
`tronic components including an increased number of thinner
`dielectric layers have been manufactured.
`[0007] Meanwhile, multi-layered ceramic electronic com-
`ponents used for the purpose of applying a high voltage are
`required to have high withstand voltage characteristics.
`[0008] However, when the dielectric layers are formed to be
`overly thin, they may be broken at a relatively low voltage,
`making it difficult to apply a high voltage thereto.
`[0009] Thus, when having high voltage applied thereto,
`dielectric layers are designed to be thicker to reduce voltage
`applied per thickness, thus withstanding high voltage.
`[0010] Also, a printed pattern of inner electrodes is formed
`to have small overlap portions between inner electrodes, thus
`reducing voltage applied to the inner dielectric layers.
`[0011] However, high voltage multi-layered ceramic elec-
`tronic components having excellent withstand voltage char-
`acteristics are still in demand.
`
`SUMMARY OF THE INVENTION
`
`[0012] An aspect of the present invention provides a high
`pressure multi-layered ceramic electronic component having
`improved withstand voltage characteristics.
`[0013] According to an aspect of the present invention,
`there is provided a multi-layered ceramic electronic compo-
`nent including: a ceramic main body including a dielectric
`layer; and inner electrode layers disposed to face each other,
`with the dielectric layer interposed therebetween,
`in the
`ceramic main body, wherein when an average thickness ofthe
`dielectric layer is defined as td, the average thickness td is
`td:15 um, and the number of dielectric grains per 10 um
`within the dielectric layer is 15 or greater.
`[0014] The inner electrode layers may include first and
`second inner electrodes each having one ends thereof alter-
`nately exposed to respective opposed end surfaces of the
`ceramic main body.
`[0015] The inner electrode layers may include: a plurality
`of first and second inner electrodes each having respective
`one ends exposed to respective end surfaces in a lengthwise
`direction of the ceramic main body; and at least one or more
`
`floating electrodes forming an overlap area with the first and
`second inner electrodes, with the dielectric layer interposed
`therebetween.
`
`[0016] When an average particle diameter of the dielectric
`grains is defined as De, the average particle diameter De may
`satisfy the condition of Dei0.4 pm,
`in particular, 0.21
`um§De§0.4 pm.
`[0017] The average thickness of the dielectric layer may be
`an average thickness of the dielectric layer in the section in a
`lengthwise and thicknesswise direction taken from a central
`portion in the widthwise direction of the ceramic main body.
`[0018] According to another aspect of the present inven-
`tion, there is provided a multi-layered ceramic electronic
`component including: a ceramic main body including a plu-
`rality of dielectric layers laminated therein; and a plurality of
`inner electrode layers disposed to face each other, with each
`ofthe plurality of dielectric layers interposed therebetween in
`the ceramic main body, wherein when an average thickness of
`the dielectric layer is defined as td, the average thickness td
`may be td: 15 um, and the number of dielectric grains per 10
`um within the dielectric layer may be 15 or greater.
`[0019] The inner electrode layers may include first and
`second inner electrodes each having one ends thereof alter-
`nately exposed to respective opposed end surfaces of the
`ceramic main body.
`[0020] The inner electrode layers may include: a plurality
`of first and second inner electrodes having respective one
`ends exposed to respective end surfaces in a lengthwise direc-
`tion of the ceramic main body; and at least one or more
`floating electrodes forming an overlap area with the first and
`second inner electrodes with the dielectric layer interposed
`therebetween.
`
`[0021] When an average particle diameter of the dielectric
`grains is defined as De, the average particle diameter De may
`satisfy the condition of De§0.4 pm,
`in particular, 0.21
`um§De§0.4 pm.
`[0022] The average thickness of the dielectric layer may be
`an average thickness ofthe dielectric layer at a central portion
`in the section in a lengthwise and thicknesswise direction
`taken from the central portion in the widthwise direction of
`the ceramic main body.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0023] The above and other aspects, features and other
`advantages of the present invention will be more clearly
`understood from the following detailed description taken in
`conjunction with the accompanying drawings, in which:
`[0024]
`FIG. 1 is a perspective view schematically showing
`a multi-layered ceramic capacitor according to an embodi-
`ment of the present invention;
`[0025]
`FIG. 2 is a cross-sectional view taken along line
`B-B‘ in FIG. 1;
`[0026]
`FIG. 3 is an enlarged view of area ‘S’ in FIG. 2;
`[0027]
`FIG. 4 is a cross-sectional view taken along line
`B-B‘ in FIG. 1 according to another embodiment of the
`present invention; and
`[0028]
`FIG. 5 is an enlarged view of area ‘S’ in FIG. 4.
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENT
`
`[0029] The invention may be embodied in many different
`forms and should not be construed as being limited to the
`embodiments set forth herein. Rather, these embodiments are
`000005
`
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`

`

`US 2013/0027843 Al
`
`Jan. 31,2013
`
`provided so that this disclosure will be thorough and com-
`plete, and will fully convey the scope ofthe invention to those
`skilled in the art. In the drawings, the shapes and dimensions
`of elements may be exaggerated for clarity, and the same
`reference numerals will be used throughout to designate the
`same or like components.
`[0030] Exemplary embodiments of the present invention
`will now be described in detail with reference to the accom-
`
`panying drawings.
`[0031]
`FIG. 1 is a perspective view schematically showing
`a multi-layered ceramic capacitor according to an embodi-
`ment of the present invention.
`[0032]
`FIG. 2 is a cross-sectional view taken along line
`B-B‘ in FIG. 1, and FIG. 3 is an enlarged view of area ‘S’ in
`FIG. 2.
`
`[0043] The average thickness of the dielectric layer 1 may
`refer to an average thickness of the dielectric layer formed
`between the adjacent inner electrode layers 21 and 22.
`[0044] The average thickness td of the dielectric layer 1
`may be measured by scanning an image of a dielectric layer
`section in a lengthwise direction ofthe ceramic main body 10
`by using a scanning electron microscope (SEM) of l0,000><
`magnification.
`[0045]
`In detail, the average value can be measured by
`measuring the thickness of 30 points (or spots), of one dielec-
`tric layer, at an equidistant intervals in the lengthwise direc-
`tion on the scarmed image.
`[0046] The multi-layered ceramic capacitor according to an
`embodiment of the present invention is a component for a
`high voltage, and in order to enhance withstand voltage char-
`acteristics by increasing a breakdown voltage (BDV), the
`average thickness td of the dielectric layer 1 may be 15 pm or
`greater.
`[0047] Here, a high voltage refers to a voltage band, for
`example, ranging from 1 KV to 5 KV, but the present inven-
`tion is not limited thereto and the multi-layered ceramic
`capacitor according to an embodiment of the present inven-
`tion can also be applicable to a middle voltage ranging from
`100 V to 630 V.
`
`[0033] With reference to FIGS. 1 and 2, a multi-layered
`ceramic electronic component according to an embodiment
`of the present invention may include a ceramic main body 10
`including a dielectric layer 1; and inner electrode layers 21
`and 22 disposed to face each other, with the dielectric layer 1
`interposed therebetween,
`in the ceramic main body 10,
`wherein when an average thickness of the dielectric layer 1 is
`defined as td, the average thickness td may be t(1215 um, and
`the number of dielectric grains per 10 um within the dielectric
`layer 1 may be 15 or greater.
`[0034] The inner electrode layers 21 and 22 may include
`first and second inner electrodes, and one end of each of the
`inner electrodes may be alternately exposed to the respective
`opposed end surfaces of the ceramic main body.
`[0035] Hereinafter, a multi-layered ceramic electronic
`component, in particular, a multi-layered ceramic capacitor,
`according to an embodiment of the present invention will be
`described, but the present invention is not limited thereto.
`[0036] According to an embodiment of the present inven-
`tion, a material used for forming the dielectric layer 1 is not
`particularly limited so long as it can obtain sufficient capaci-
`tance. For example, the material may be barium titanate (Ba-
`TiO3) powder.
`[0037] The material for forming the dielectric layer 1 may
`be formed by adding various materials such as a ceramic
`additive, an organic solvent, a plasticizer, a binding agent, a
`dispersing agent, and the like, to powder such as barium
`titanate (BaTiO3) powder, or the like, according to the pur-
`pose of the present invention.
`[0038] The inner electrode layers 21 and 22 are not particu-
`larly limited. For example, the inner electrode layers 21 and
`22 may be formed by using a conductive paste formed of one
`or more of silver (Ag), lead (Pb), platinum (Pt), nickel (Ni),
`and copper (Cu).
`[0039]
`In order to form capacitance, outer electrodes 3 may
`be formed on outer surfaces of the ceramic main body 10 and
`may be electrically connected to the first and second inner
`electrodes 21 and 22.
`
`[0040] The outer electrodes 3 may be formed of the same
`conductive material as that of the inner electrodes 21 and 22,
`and may be formed by using copper (Cu), silver (Ag), nickel
`(Ni), or the like, but the present invention is not limited
`thereto.
`
`[0041] The outer electrodes 3 may be formed by applying
`the conductive paste prepared by adding glass frit to the metal
`powder, and then firing the same.
`[0042]
`In the multi-layered ceramic capacitor according to
`an embodiment ofthe present invention, an average thickness
`td of the dielectric layer 1 may be 15 pm or greater.
`
`Ifthe average thickness td of the dielectric layer 1 is
`[0048]
`lower than 15 pm, the breakdown voltage may be lowered
`over the high voltage applied to the multi-layered ceramic
`electronic component.
`[0049] With reference to FIGS. 2 and 3, in the multi-layered
`ceramic capacitor according to an embodiment of the present
`invention, the number of dielectric grains per 10 um in the
`dielectric layer 1 may be 15 or greater.
`[0050]
`In order to measure the number of dielectric grains
`per 10 pm, the ceramic main body 10 may be cut in the
`lamination direction of the dielectric layer 1 and then the
`section as illustrated in FIG. 2 may be measured by a line
`dividing method.
`[0051]
`In detail, the number of dielectric grains per 10 um
`was determined by measuring the number of dielectric grains
`measured by using a scale bar of 10 pm.
`[0052]
`In order to measure the number of dielectric grains,
`the number of dielectric grains may be measured by scanning
`the image of the section in the lengthwise direction of the
`ceramic main body 10 by the SEM.
`[0053]
`For example, as shown in FIG. 2, with respect to a
`certain dielectric layer extracted from an image obtained by
`scanning the section in a lengthwise and thicknesswise (L-T)
`direction taken from a central portion in the widthwise (W)
`direction of the ceramic main body 10 by using the SEM, the
`number of dielectric grains at a certain point among thirty
`points at equidistant intervals in the lengthwise direction may
`be measured by using a 10 um-scale bar.
`[0054] Also, the certain point may be a central point among
`the thirty points at equidistant intervals in the lengthwise
`direction, and the number of dielectric grains at the central
`point may be measured by using the 10 um-scale bar.
`[0055] The thirty points at equidistant intervals may be
`determined at a capacitance formation portion which corre-
`sponds to an area in which the first and second inner elec-
`trodes 21 and 22 overlap.
`in the multi-layered
`[0056] With reference to FIG. 3,
`ceramic capacitor according to an embodiment of the present
`invention, it is noted that the number of dielectric grains
`measured at one point of the section in the lengthwise and
`000006
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`

`

`US 2013/0027843 A1
`
`Jan. 31,2013
`
`thicknesswise (L-T) direction taken from the central portion
`in the widthwise (W) direction ofthe ceramic mainbody 10 in
`FIG. 2 is 15 or greater.
`[0057] The characteristics of the multi-layered ceramic
`capacitor in which the number of dielectric grains per 10 pm
`in the dielectric layer 1 is 15 or greater can be implemented by
`adjusting an average particle diameter ofthe dielectric grains.
`[0058]
`In detail, according to an embodiment ofthe present
`invention, when an average particle diameter of the dielectric
`grains is defined as De, the average particle diameter De may
`satisfy the condition of De§0.4 pm,
`in particular, 0.21
`um§De§0.4 pm.
`[0059]
`In this manner, by adjusting the average particle
`diameter of the dielectric grains such that De§0.4 pm, in
`particular, 0.21 um§De§0.4 pm, a larger number of dielec-
`tric grains may be present per dielectric layer 1, thus improv-
`ing withstand voltage.
`[0060] Namely, the breakdown voltage per unit thickness
`ofthe dielectric layer 1 can be increased by the larger number
`of the dielectric grains per layer.
`[0061]
`If the average particle diameter of the dielectric
`grains exceeds 0.4 pm, the average number of dielectric
`grains per layer would be reduced to lead to a reduction in
`withstand voltage characteristics allowing for the dielectric
`grains to withstand voltage, so the effect ofwithstand voltage
`improvement would not be great.
`[0062] Also, if the average particle diameter of the dielec-
`tric grains is reduced to become smaller than 0.21 pm, the
`effect of the insulation characteristics would not be great.
`[0063] The reason for this is because, when the particle
`diameter of the dielectric grains is reduced, although the
`average number of particles of the dielectric grains per layer
`will be increased, withstand voltage characteristics for one
`grain to withstand are reduced.
`[0064] As described above, according to an embodiment of
`the present invention, the dielectric grains may be adjusted to
`have an average particle diameter De, namely, De§0.4 um, in
`particular, 0.21 p.m§De§0.4 um, such that the average thick-
`ness td of the dielectric layer 1 is 15 pm or greater and the
`number of dielectric grains per 10 pm is 15 or greater in the
`dielectric layer 1, whereby a relatively thick, uniform dielec-
`tric layer can be obtained to thus implement a high voltage
`multi-layered ceramic electronic component having excellent
`withstand voltage characteristics.
`[0065]
`FIG. 4 is a cross-sectional view taken along line
`B-B‘ in FIG. 1 according to another embodiment of the
`present invention, and FIG. 5 is an enlarged view of area ‘S’
`in FIG. 4.
`
`[0066] With reference to FIG. 4, the inner electrode layers
`may include first and second inner electrodes 2a and 2b
`having respective one ends exposed to respective end surfaces
`in the lengthwise direction of the ceramic main body 10 and
`at least one or more floating electrodes 4 forming an overlap
`area with the first and second inner electrodes 2a and 2b with
`
`the dielectric layer 1 interposed therebetween.
`[0067] According to the present embodiment, since the at
`least one or more floating electrodes 4 forming an overlap
`area with the first and second inner electrodes 2a and 2b
`
`having the dielectric layer 1 interposed therebetween is pro-
`vided, an electrical field concentration due to the reduction in
`the thickness of the dielectric layer can be prevented and
`required withstand voltage performance can be obtained.
`[0068] With reference to FIG. 5, the multi-layered ceramic
`electronic component according to an embodiment of the
`
`present invention can obtain further improved withstand volt-
`age performance by including the floating electrode 4 and the
`dielectric layer 1 having the thickness td of 15 pm or greater
`and adjusting the number of dielectric grains per 10 pm in the
`dielectric layer 1 such that it is 15 or greater.
`[0069] Hereinafter, a multi-layered ceramic electronic
`component, in particular, a multi-layered ceramic capacitor,
`according to an embodiment of the present invention will be
`described, but the present invention is not limited thereto, and
`a description of overlap characteristics with those of the fore-
`going embodiment of the present invention will be omitted.
`[0070] The multi-layered ceramic capacitor may include a
`plurality of the first and second inner electrodes 2a and 2b
`having respective one ends exposed to respective end surfaces
`in the lengthwise direction of the ceramic main body 10, and
`at least one or more floating electrodes 4 forming an overlap
`area with the first and second inner electrodes 2a and 2b with
`
`the dielectric layer 1 interposed therebetween.
`[0071] Also, the first and second inner electrodes 2a and 2b
`and the floating electrode 4 may be alternately laminated
`between the dielectric layers 1.
`[0072] The multi-layered ceramic capacitor may be config-
`ured to include a plurality of capacitor units in a serial con-
`nection owing to the at least one or more floating electrodes 4.
`[0073] Accordingly, a multi-layered ceramic capacitor
`which is small but has large capacity can be implemented, and
`since withstand voltage can be increased per unit thickness of
`the dielectric layer, a high voltage multi-layered ceramic
`capacitor having excellent withstand voltage performance
`can also be implemented.
`[0074] Meanwhile, according to an embodiment of the
`present invention, the multi-layered ceramic capacitor may
`include the floating electrodes 4, the thickness td ofthe dielec-
`tric layer 1 may be 15 pm or greater, and the number of
`dielectric grains per 10 pm in the dielectric layer 1 may be
`adjusted to be 15 or greater,
`thereby obtaining further
`improved withstand voltage performance.
`[0075] Here, the thickness of the dielectric layer 1 and the
`number of dielectric grains per 10 um are the same as those
`described above so, a description thereof will be omitted.
`[0076] Because the number of the dielectric grains per 10
`pm in the dielectric layer 1 is adjusted to be 15 or greater,
`withstand voltage per unit thickness of the dielectric can be
`further increased, and accordingly, withstand voltage perfor-
`mance can be further improved.
`[0077] A multi-layered ceramic electronic component
`according to another embodiment of the present invention
`may include a ceramic main body including a plurality of
`dielectric layers laminated therein; and a plurality of inner
`electrode layers disposed to face each other, with each of the
`plurality of dielectric layers interposed therebetween in the
`ceramic main body, wherein when an average thickness ofthe
`dielectric layer 1 is defined as td, the average thickness td may
`be td§15 um, and the number of dielectric grains per 10 um
`within the dielectric layer 1 may be 15 or greater.
`[0078] The multi-layered ceramic electronic component
`according to the present embodiment is the same as the multi-
`layered ceramic electronic component according to the fore-
`going embodiment, except that the plurality of dielectric lay-
`ers and the plurality of first and second inner electrode layers
`are laminated therein, so a repeated description will be omit-
`ted.
`
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`US 2013/0027843 A1
`
`Jan. 31,2013
`
`[0079] The inner electrode layers may include first and
`second inner electrodes alternately exposed to the respective
`opposed end surfaces of the ceramic main body.
`[0080] Also, the inner electrode layers may include a plu-
`rality of first and second inner electrodes each having respec-
`tive one ends exposed to the respective end surfaces in the
`lengthwise direction of the ceramic main body, and at least
`one or more floating electrodes forming an overlap area with
`the first and second inner electrodes 2a and 2b with the
`
`dielectric layer interposed therebetween.
`[0081] When an average particle diameter of the dielectric
`grains is defined as De, the average particle diameter De may
`satisfy the condition of De§0.4 pm,
`in particular, 0.21
`um§De§0.4 pm.
`[0082] An average thickness ofthe dielectric layers may be
`an average thickness of the dielectric layer at the central
`portion in the section in the lengthwise and thickness (L-T)
`direction taken from the central portion in the widthwise (W)
`direction of the ceramic main body.
`[0083] The measurement of the average value may extend
`to ten dielectric layers to measure an average thickness of the
`ten dielectric layers, to thereby further generalize the average
`thickness of the dielectric layer.
`[0084] Meanwhile, as shown in FIG. 2, with respect to the
`central dielectric layer at the section in the lengthwise and
`thicknesswise (L-T) direction taken from the central portion
`in the widthwise (W) direction of the ceramic main body 10,
`the number of dielectric grains at a certain point among thirty
`points at equidistant intervals in the lengthwise direction may
`be measured by using a 10 um-scale bar.
`[0085] The present invention will be described in more
`detail through examples, but the present invention is not lim-
`ited thereto.
`
`[0086] The Example was manufactured to test improve-
`ments in withstand voltage characteristics and reliability of
`the multi-layered ceramic capacitor in which the first and
`second inner electrodes and the floating electrode 4 are alter-
`nately laminated between the dielectric layers, the thickness
`td of the dielectric layers is 15 um or greater, and the number
`of dielectric grains per 10 um within the dielectric layers is 15
`or greater.
`[0087] The multi-layered ceramic capacitor according to
`the Example was manufactured through the following opera-
`tions.
`
`First, slurry formed by including powder such as
`[0088]
`barium titanate (BaTiO3) or the like was applied to a carrier
`film and dried to prepare a plurality of ceramic green sheets,
`thus forming the dielectric layer 1.
`[0089] The thickness of the plurality of ceramic green
`sheets was set such that an average thickness of the dielectric
`layer after a firing operation was 15 pm.
`[0090] An average thickness of the dielectric layer was
`designed to have a fine difference according to each example
`in consideration of shrinkage after the firing operation.
`[0091] The average thickness of the dielectric layer was
`measured by using a measurement program after capturing an
`image of the dielectric layer by using an optical microscope.
`[0092] Here, the average particle diameter De ofthe dielec-
`tric grains was adjusted to be 0.4 um or smaller. In detail, in
`Examples 1 to 3, the average particle diameter De of the
`dielectric grains was adjusted to be 0.40 pm, 0.32 pm, and
`0.21 pm, respectively.
`
`[0093] Next, conductive paste for inner electrodes having
`an average nickel particle size of 0.05 pm to 0.2 pm was
`prepared.
`[0094] The conductive paste for inner electrodes was
`applied to the green sheet through screen printing to form
`inner electrodes, and 50 layers were laminated to form a
`lamination body.
`[0095] Here, the inner electrodes were manufactured such
`that a plurality of first and second inner electrodes 2a and 2b
`having respective one ends exposed to the respective end
`surfaces in the lengthwise direction ofthe ceramic main body
`10 and at least one or more floating electrodes 4 forming an
`overlap area S with the first and second inner electrodes 2a
`and 2b were alternately formed.
`[0096] Thereafter, the lamination body was compressed
`and cut to generate a chip having a 3216 standard size, and the
`chip was fired at a temperature of 1050[ to 1200[ under a
`reduction atmosphere of 0.1% of H2 or less.
`[0097] Then, the resultant structure underwent processes
`such as an external electrode formation process, a plating
`process, or the like, so as to be a multi-layered ceramic
`capacitor.
`[0098] Meanwhile, Comparative Example 1 was manufac-
`tured according to the same method except that the average
`particle diameter of dielectric grains and the number of
`dielectric grains per 10 um within the dielectric layer were
`different in comparison to the Example.
`[0099] Also, Comparative Examples 2 and 3 were manu-
`factured according to the same method, except that the aver-
`age thickness ofthe dielectric layer was 12.0 um and 10.0 um,
`lower than 15 pm, respectively, after a firing operation, in
`comparison to the Example.
`[0100] Table 1 below shows the comparison of the average
`thickness of the dielectric layer after a firing operation, the
`average particle diameter of the dielectric grains, the average
`breakdown voltage V according to the number of dielectric
`grains per 10 pm in the dielectric layer, and withstand voltage
`V per dielectric grain.
`
`TABLE 1
`
`Average
`particle
`diameter
`(De) of
`dielectric
`grain (pm)
`
`Average
`thickness
`(td) of
`dielectric
`layer after
`firing (pm)
`
`Average
`dielectric With-
`break-
`stand
`down
`voltage
`voltage
`(V) per
`(V)
`grain
`
`Number of
`dielectric
`grains per
`10 pm
`
`0.52
`
`0.40
`
`0.40
`
`15.0
`
`12.0
`
`10.0
`
`11
`
`15
`
`15
`
`626
`
`849
`
`694
`
`39.6
`
`47.2
`
`46.3
`
`No.
`
`Experimental
`Example 1
`Comparative
`Example 2
`Comparative
`Example 3
`
`[0101] With reference to Table 1, Experimental Example 1
`shows a case in which the average thickness of the dielectric
`layer was 15 um, and it is noted that when the average particle
`diameter of the dielectric grains and the number of dielectric
`grains per 10 um exceed the range of the numerical values of
`the present invention, the breakdown voltage and withstand
`voltage are problematic.
`[0102] Meanwhile, Comparative Examples 2 and 3 show
`cases in which the average thickness of the dielectric layer
`was smaller than 15 um, and it is noted that although the
`average particle diameter of the dielectric grains and the
`number of dielectric grains per 10 um exceeded the range of
`000008
`
`000008
`
`

`

`US 2013/0027843 Al
`
`Jan. 31,2013
`
`the numerical values of the present invention, there were no
`defects with breakdown voltage and withstand voltage.
`[0103] Thus, it is noted that the multi-layered ceramic elec-
`tronic component according to an embodiment of the present
`invention has an effect in terms of breakdown voltage and
`withstand voltage when the average thickness td after the
`dielectric layer 1 is fired is 15 pm or greater, by explanation to
`be below provided.
`[0104] Table 2 below shows a comparison of the average
`particle diameter of the dielectric grains, the average break-
`down voltage V according to the number of dielectric grains
`per 10 pm in the dielectric layer, and withstand voltage V per
`dielectric grain, when the average thickness of the dielectric
`layer after the firing operation was 15 pm.
`[0105] The breakdown voltage (BDV) characteristics were
`evaluated while applying a DC voltage at a rate of 10V/sec.
`
`TABLE 2
`
`Average
`thickness
`of
`dielectric
`layer
`after
`firing
`(td)
`
`15.0
`
`15.0
`15.0
`15.0
`
`Average
`particle
`diameter
`(De) of
`dielectric
`grain (um)
`
`0.52
`
`0.40
`0.32
`0.21
`
`No.
`
`Comparative
`Example 1
`Exa.mple 1
`Exa.mple 2
`Exa.mple 3
`
`Number of
`dielectric
`grains per
`10 um
`
`Average
`dielectric
`breakdown
`voltage
`(V)
`
`With-
`stand
`voltage
`(V) per
`grain
`
`11
`
`15
`16
`20
`
`626
`
`781
`937
`965
`
`39.6
`
`42.7
`38.9
`34.6
`
`[01 06] As noted from Table 2, as the average diameter De of
`the dielectric grains was reduced, the average number of
`dielectric particles of the dielectric layer was increased, and
`accordingly, the average breakdown voltage was drastically
`increased.
`
`[0107] Namely, in the case of Comparative Example 1 in
`which the average particle diameter De of the dielectric grain
`exceeded 0.5 pm, the average breakdown voltage was low as
`compared with Examples 1 through 3, each having an average
`particle diameter of 0.5 um or smaller.
`[0108] Meanwhile, it is noted that the insulation character-
`istics of Examples 1
`through 3 in which the numbers of
`dielectric grains per 10 pm in the dielectric layer were 15, 16,
`and 20,
`respectively, superior to those of Comparative
`Example 1 in which the number of dielectric grains per 10 um
`in the dielectric layer was 11.
`[0109]
`In the case of Example 3, the average particle diam-
`eter of the dielectric grains was 0.21 pm, whose effect of
`increasing the average breakdown voltage was not relatively
`great in comparison to Example 2.
`[01 1 0] The reason is determined to be that when the particle
`diameter of the dielectric grains was reduced, the average
`number of particles of the dielectric grains per layer was
`increased, but the withstand voltage characteristics which
`each grain can withstand are reduced.
`[0111] Thus, although the average particle diameter of the
`dielectric grains was further reduced to become smaller than
`0.21 pm, the effect of the insulation characteristics was not
`great.
`[0112] As a result, by having at least one or more floating
`electrodes forming an overlap area with the first and second
`inner electrodes with the dielectric layer interposed therebe-
`tween, an electrical field concentration due to the reduction in
`000009
`
`the thickness of the dielectric layer may be prevented and
`withstand voltage characteristics may be improved.
`[0113]
`In addition, the thickness td of the dielectric layer is
`15 pm or greater and the average particle diameter De of the
`dielectric grains is 0.4 pm or smaller, and in this case, when
`the number of the dielectric grains per 10 um in the dielectric
`layer is 15 or greater, withstand voltage characteristics may
`be further improved and the reliability may also be improved.
`[0114] According to an embodiment of the present inven-
`tion, the high voltage multi-layered ceramic capacitor can be
`implemented to be small and have high capacity, and reliabil-
`ity thereof can be improved owing to the excellent withstand
`voltage characteristics.
`[0115] As set forth above, according to embodiments ofthe
`invention, since a uniform,
`thick dielectric layer can be
`obtained with fine dielectric powder, a high voltage multi-
`layered ceramic electronic component having excellent with-
`stand voltage characteristics can be implemented.
`[0116] While the present invention has been show