M-0048 US
`
`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS
`
`WITH LOCALITY EXPLOITATION
`
`Venkat Konda
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is related to and incorporates by referencein its entirety the PCT
`
`Application Serial No. PCT /US08/56064 entitled "FULLY CONNECTED
`
`GENERALIZED MULTI-STAGE NETWORKS"by Venkat Konda assigned to the same
`
`assignee as the current application, filed March 6, 2008, the U.S. Provisional Patent
`
`10
`
`Application Serial No. 60/905,526 entitled "LARGE SCALE CROSSPOINT
`
`REDUCTION WITH NONBLOCKING UNICAST & MULTICAST IN
`
`ARBITRARILY LARGE MULTI-STAGE NETWORKS"by Venkat Kondaassigned to
`
`the same assignee as the current application, filed March 6, 2007, and the U.S.
`
`Provisional Patent Application Serial No. 60/940, 383 entitled "FULLY CONNECTED
`
`15
`
`GENERALIZED MULTI-STAGE NETWORKS"by Venkat Konda assigned to the same
`
`assignee as the current application, filed May 25, 2007.
`
`This application is related to and incorporates by referencein its entirety the PCT
`
`Application Serial No. PCT /US08 / 64603 entitled "FULLY CONNECTED
`
`GENERALIZED BUTTERFILY FAT TREE NETWORKS"by Venkat Konda assigned
`
`20
`
`to the same assigneeas the current application, filed May 22, 2008, the U.S. Provisional
`
`Patent Application Serial No. 60/940, 387 entitled "FULLY CONNECTED
`
`GENERALIZED BUTTERFLY FAT TREE NETWORKS"by Venkat Konda assigned
`
`to the same assigneeas the current application, filed May 25, 2007, and the U.S.
`
`Provisional Patent Application Serial No. 60/940, 390 entitled "FULLY CONNECTED
`
`GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS"by Venkat
`
`Konda assigned to the same assigneeas the current application, filed May 25, 2007
`
`This application is related to and incorporates by reference in its entirety the PCT
`
`Application Serial No. PCT /US08 / 64604 entitled "FULLY CONNECTED
`
`-l-
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`FLEX LOGIX EXHIBIT 1029
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`FLEX LOGIX EXHIBIT 1029
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`M-0048 US
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`GENERALIZED MULTI-LINK MULTI-STAGE NETWORKS"by Venkat Konda
`
`assigned to the same assignee as the current application, filed May 22, 2008,the U.S.
`
`Provisional Patent Application Serial No. 60/940, 389 entitled "FULLY CONNECTED
`
`GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTL-
`
`STAGE NETWORKS"by Venkat Kondaassigned to the same assignee as the current
`
`application, filed May 25, 2007, the U.S. Provisional Patent Application Serial No.
`
`60/940, 391 entitled "FULLY CONNECTED GENERALIZED FOLDED MULTI-
`
`STAGE NETWORKS"by Venkat Kondaassigned to the same assignee as the current
`
`application, filed May25, 2007 and the U.S. Provisional Patent Application Scrial No.
`
`10
`
`60/940, 392 entitled "FULLY CONNECTED GENERALIZED STRICTLY
`
`NONBLOCKING MULTI-LINK MULTLSTAGE NETWORKS"by Venkat Konda
`
`assigned to the same assignee as the current application, filed May 25, 2007.
`
`This application is related to and incorporates by referencein its entirety the PCT
`
`Application Serial No. PCT /US08/64605 entitled "VLSI LAYOUTS OF FULLY
`
`15
`
`CONNECTED GENERALIZED NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed May 22, 2008, and the U.S. Provisional Patent
`
`Application Serial No. 60/940, 394 entitled "VLSI LAYOUTS OF FULLY
`
`CONNECTED GENERALIZED NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed May 25, 2007.
`
`20
`
`This application is related to and incorporates by referencein its entirety the U.S.
`
`Provisional Patent Application, Attorney Docket No. M-0049 USentitled "VILST
`
`LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID
`
`NETWORKS"by Venkat Kondaassigned to the same assignee as the current application,
`
`filed concurrently.
`
`25
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG, 1A is a diagram 100A of an exemplary symmetrical multi-link multi-stage
`
`network Voi4-mine(N.d,8) having a variation of inverse Benes connection topology of
`
`nine stages with N = 32, d = 2 and s=2, strictly nonblocking nctwork for unicast
`-2-
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`connections and rearrangeably nonblocking network for arbitrary fan-out multicast
`
`connections, in accordance with the invention.
`
`FIG. 1B is a diagram 100B of the equivalent symmetrical folded multi-link multi-
`
`stage network V,,otd_miink N,d,5) of the network 100A shown in FIG. 1A, having a
`
`variation of inverse Benes connection topology offive stages with N = 32, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and rearrangeably nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1C is a diagram 100C layout of the network V,0id_miing (Vs d,8) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links belonging with in each block
`
`10
`
`only.
`
`FIG. 1D is a diagram 100D layout of the network V,‘0.td_mtine(N,d,S) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(1,1) for 1 = [1, 64] and
`
`ML(8,i) for i = [1,64].
`
`FIG. 1E is a diagram 100E layoutof the network Vj.jain, (N.d,8) shown in FIG.
`
`15
`
`1B, in one embodiment, illustrating the connection links ML(2,i) for 1 = [1, 64] and
`
`ML(7,1) for 1 = [1,64].
`
`FIG. 1F is a diagram 100F layout of the network Vji4ming (N.d,5) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and
`
`ML(6,ji) for i = [1,64].
`
`20
`
`FIG. 1G is a diagram 100G layout of the network V,‘0.td_mtine(N,d,S) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(4,1) for 1 = [|1, 64] and
`
`ML(5,1) for i = [1,64].
`
`FIG. 1H is a diagram 100H layout of a network Vj..7ning (N.d,8) where N = 128,
`
`d = 2, and s = 2, in one embodiment, illustrating the connection links belonging with in
`
`25
`
`each block only.
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`FIG. 11 is a diagram 100I detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V,4.(N,d,5) OF Visiting (Nd, 8)-
`
`FIG. 1J is a diagram 100J detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing Vi...5¢(N.d,5).
`
`FIG. 1K is a diagram 100K detailed connections of BLOCK 1_2? in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N d,s) or Vi4(N,d,5).
`
`10
`
`FIG. 1K1 is a diagram 100M1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V(N,d,s) or V,,(N,d,8) fors = 1.
`
`FIG. 1L is a diagram 100L detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`15
`
`when the layout 100C is implementing Vig (N,d,s).
`
`FIG. 1L1 is a diagram 100L1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming out
`
`whenthe layout 100C is implementing V,,(NV,d,s) fors=1.
`fi
`
`FIG. 2A is a diagram 200A of an exemplary symmetrical multi-link multi-stage
`
`20
`
`network Viimine (Nd, 5) having inverse Benes connection topology of nine stages with
`
`N = 24, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG. 2B is a diagram 200B of the equivalent symmetrical folded multi-link multi-
`
`25
`
`stage network Viitine (N.d,5) of the network 200A shownin FIG, 2A, having inverse
`
`Benes connection topology of five stages with N = 24, d= 2 and s=2,strictly nonblocking
`
`4.
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`network for unicast connections and rearrangeably nonblocking networkfor arbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`FIG. 2C is a diagram 200C layout of the network Vjold-mint (Nd, 8) shown in FIG,
`
`2B, in one embodiment, illustraung the connection links belonging with in each block
`
`only.
`
`FIG, 2D is a diagram 200D layout of the network V,01id_mine(V+ d,S) shown in
`
`FIG. 2B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 48] and
`
`ML(8,1) for i = [1,48].
`
`FIG. 2E is a diagram 200E layoutof the network Voiimine (N.d,5) shown in FIG.
`
`10
`
`2B, in one embodiment, illustrating the connection links ML(2,i) for 1 = [1, 32] and
`
`ML(7,i) for 1 = [1,32].
`
`FIG, 2Fis a diagram 200Flayout of the network Vfoldnine (Nd, 8) shown in FIG.
`
`2B, in one embodiment, illustrating the connection links ML(3,i) for 1 = [1, 64] and
`
`ML(6,1) for 1 = [1,64].
`
`15
`
`FIG, 2G is a diagram 200G layout of the network V,01id_mineNV» d,8) shown in
`
`FIG. 2B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`ML(5,1) for i = [1,64].
`
`FIG. 3A is a diagram 300A layout of the topmost
`
`row of the network
`
`Voia-mink (N,d,5) with N = 512, d = 2 and s=2,
`
`in one embodiment,
`
`illustrating the
`
`20
`
`provisioning of 2’s BW.
`
`FIG. 3B is a diagram 300B layout of the topmost
`
`row of the network
`
`Vvoie-mink (N.d,5) with N = 512, d = 2 and s=2,
`
`in one embodiment,
`
`illustrating the
`
`provisioning of 4’s BW.
`
`FIG. 3C is a diagram 300C layout of the topmost
`
`row of the network
`
`Viota-mink (N,d,5) with N = 512, d = 2 and s=2,
`
`in one embodiment,
`
`illustrating the
`
`provisioning of 8’s BW with nearest neighbor connectivity first.
`5-
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`FIG. 3D is a diagram 300D layout of the topmost
`Vi0.ia—mtine (Nod, 5) with N = 512, d = 2 and s=2,
`
`in one embodiment,illustrating the
`
`row of the network
`
`provisioning of 8’s BW with nearest neighbor connectivity recursively.
`
`FIG. 4A is a diagram 400A layout of the topmost
`
`row of the network
`
`Vfold-miine (Nd, 5) with N = 512, d = 2 and s=2,
`
`in one embodiment,
`
`illustrating the
`
`provisioning of 2’s BW infirst stage.
`
`FIG. 4B is a diagram 400B layout of the topmost
`
`row of the network
`
`Venta—-mtine (Nd, 8) with N = 512, d = 2 and s=2,
`
`in one embodiment,illustrating the
`
`remaining nearest neighbor connectivity in the second stage by provisioning 4’s BW,8’s
`
`10
`
`BW etc.
`
`FIG. 4C is a diagram 400C layout of the topmost
`
`row of the network
`
`Vvfold-miine (Nd, 8) with N = 512, d = 2 and s=2, in one embodiment, illustrating the third
`
`stage, by provisioning 4’s and 8’s BW.
`
`FIG.
`
`5
`
`is
`
`a diagram 500 layout of
`
`the topmost
`
`row of
`
`the network
`
`15
`
`Vieta_mline N58) with N = 512, d = 2 and s = 2, in one embodiment, illustrating the
`
`provisioning of 8’s BW and 16’s BW in Partial & Tapered Connectivity (Bandwidth) in a
`
`stage.
`
`FIG.
`
`6 is
`
`a diagram 600 layout of
`
`the topmost
`
`row of
`
`the network
`
`Vinta—-mtine (N.S) with N = 2048, d = 2 and s = 2, in one embodiment, illustrating the
`
`20
`
`provisioning of 8’s BW, 16’s BW and 32’s BW in Partial & Tapered Connectivity
`
`(Bandwidth) in a stage.
`
`FIG.
`
`7
`
`is
`
`a diagram 700 layout of
`
`the topmost
`
`row of
`
`the network
`
`Vfold-mint (Nd, 8) with N = 2048, d = 2 and s = 2, in one embodiment,illustrating the
`
`provisioning of 8’s BW, 16’s BW and 32’s BW in Partial & Tapered Connectivity
`
`25
`
`(Bandwidth) in a stage with equal length wires.
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`DETAILED DESCRIPTION OF THE INVENTION
`
`‘The present invention is concerned with the VLSI layouts of arbitrarily large
`
`switching networks for broadcast, unicast and multicast connections. Particularly
`
`switching networks consideredin the current invention include: generalized multi-stage
`
`networks V(N,,N,,d,s), generalized folded multi-stage networks V,,,(N,,N,,d,5),
`
`generalized butterfly fat tree networks V,,(N,.N,,d,5), generalized multi-link multi-
`
`stage networksV,,,,,,(N,,N,,d,8). generalized folded multi-link multi-stage networks
`
`Vvfola—mink (N,,N,,4,8), generalized multi-link butterfly fat tree networks
`
`mu
`V tinkbj (N,,N,,d,5), and generalized hypercube networks V,
`
`cube
`
`(N,,N,,d,s) fors =
`
`10
`
`1,2,3 or any numberin general.
`
`Efficient VLSI layout of networks on a semiconductor chip are very important
`
`and greatly influence many important design parameters such as the area taken up by the
`
`network on the chip, total numberof wires, length of the wires, latency of the signals,
`
`capacilance and hence the maximum clock speed of operation. Some networks may not
`
`15
`
`even be implemented practically on a chip dueto the lack of efficient layouts. The
`
`different varieties of multi-stage networks described above have not been implemented
`
`previously on the semiconductor chipsefficiently. or example in I'ield Programmable
`
`Gate Array (FPGA) designs, multi-stage networks described in the current invention have
`
`not been successfully implemented primarily duc to the lack of efficient VLSI layouts.
`
`20
`
`Current commercial FPGA products such as Xilinx Vertex, Altera’s Stratix implement
`
`island-style architecture using mesh and segmented meshrouting interconnects using
`
`either full crossbars or sparse crossbars. These routing interconnects consumelarge
`
`silicon area for crosspoints, long wires, large signal propagation delay and hence
`
`consumelot of power.
`
`25
`
`The current invention discloses the VLSI layouts of numeroustypes of multi-
`
`stage networks which are very efficient and exploit spacial locality in the connectivity.
`
`Moreoverthey can be embedded on to mesh and segmented meshrouting interconnects
`
`of current commercial FPGA products. The VLSI layouts disclosed in the current
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`invention are applicable to including the numerousgeneralized multi-stage networks
`
`disclosed in the following patent applications:
`
`1) Strictly and rearrangeably nonblocking forarbitrary fan-out multicast and
`
`unicast for generalized multi-stage networks V(N,,N,,d,s) with numerous connection
`
`topologies and the scheduling methods are described in detail in the PCT Application
`
`Serial No. PCT /US08 /56064that is incorporated by reference above.
`
`2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized butterfly fat tree networks V,,(N,,N,,d,5) with numerous
`
`connection topologies and the scheduling methodsare described in detail in the PCT
`
`10
`
`Application Serial No. PCT /US08 / 64603that is incorporated by reference above.
`
`3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and
`
`strictly nonblocking for unicast for generalized multi-link multi-stage networks
`
`Vtien (N,»N,,.d,8) and generalized folded multi-link multi-stage networks
`
`Vjott-mine (N,N,.d,5) with numerous connection topologies and the scheduling methods
`
`15
`
`are described in detail in the PCT Application Serial No. PCT /US08 /64604 thatis
`
`incorporated by reference above.
`
`4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized multi-link butterfly fat tree networks V,,jingog (N,.N2,d,5) with
`
`numerous connection topologies and the scheduling methodsare described in detail in the
`
`20
`
`PCT Application Serial No. PCT /US08/64603that is incorporated by reference above.
`
`5) Strictly and rearrangeably nonblocking forarbitrary fan-out multicast and
`
`unicast for generalized folded multi-stage networks V,,,,(N,,N,,d,5) with numerous
`
`connection topologies and the scheduling methods are described in detail in the PCT
`
`Application Serial No. PCT /US08 / 64604 that is incorporated by reference above.
`
`25
`
`6) Strictly nonblocking for arbitrary fan-out multicast and unicast for generalized
`
`multi-link multi-stage networks V,,,,,,(V,,N,,d,8) and generalized folded multi-link
`
`multi-stage networks V,0.amine (N,,N,,d,8) with numerous connection topologies and
`-8-
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`M-0048 US
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`the scheduling methodsare described in detail in the PCT Application Serial No.
`
`PCT /US08 /64604 that is incorporated by reference above.
`
`7) VLSI layouts of numerous types of multi-stage networks are described in the
`
`PCT Application Serial No. PCT /US08/64605 entitled "VLSI LAYOUTS OF FULLY
`
`CONNECTED NETWORKS" thatis incorporated by reference above.
`
`8) VLSI layouts of numerous types of multi-stage pyramid networks with locality
`
`exploitation are described in U.S. Provisional Patent Application Docket No. M-0049 US
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND
`
`PYRAMID NETWORKS"by Venkat Konda assigned to the same assignee as the current
`
`10
`
`application, filed concurrently.
`
`In addition the layouts of the current invention are also applicable to generalized
`
`multi-stage pyramid networks V,(N,,N,,d,s) , generalized folded multi-stage pyramid
`
`networks Vfod-p (N,,N,.d,5), generalized butterfly fat pyramid networks
`
`Vig (N,,N,,d,5), generalized multi-link multi-stage pyramid networks
`
`15
`
`Vntint-p (N1,N,,d, 5), generalized folded multi-link multi-stage pyramid networks
`
`Vjott—miine_p (N1,N>,4,8), generalized multi-link butterfly fat pyramid networks
`
`cube
`Vtinkbp (N,,N,,d,8), generalized hypercube networksV,,_,.(N,,N,,d,s) and
`
`generalized cube connected cycles networks V..-(N,,N,.d,8) for s = 1,2,3 or any
`
`numberin general.
`
`20
`
`Symmetric RNB generalized multi-link multi-stage network V,,,,,,(V,,N,,d,5)5
`
`Connection Topology: Nearest Neighbor connectivity and with Full Bandwidth:
`
`Referring to diagram 100A in FIG.1A, in one embodiment, an exemplary
`
`generalized multi-link multi-stage network V,,,,,,(V,,N.,.d,8) where N; = No =32; d=
`
`25
`
`2; and s = 2 with nine stages of one hundred and forty four switches forsatisfying
`
`communication requests, such as setting up a telephone call or a data call, or a connection
`
`between configurable logic blocks, between an input stage 110 and output stage 120 via
`-9-
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`middle stages 130, 140, 150, 160, 170, 180 and 190 is shown where input stage 110
`
`consists of sixteen, two by four switches IS1-IS16 and output stage 120 consists of
`
`sixteen, four by two switches OS1-OS16. Andall the middle stages namely the middle
`
`stage 130 consists of sixteen, four by four switches MS(1,1) - MS(1,16), middle stage 140
`
`consists of sixteen, four by four switches MS(2,1) - MS(2,16), middle stage 150 consists
`
`of sixteen, four by four switches MS(@3,1) - MS(3,16), middle stage 160 consists of
`
`sixteen, four by four switches MS(4,1) - MS(4,16), middle stage 170 consists ofsixteen,
`
`four by four switches MS(5,1) - MS(5,16), middle stage 180 consists of sixteen, four by
`
`four switches MS(6,1) - MS(6,16), and middle stage 190 consists of sixteen, four by four
`
`10
`
`switches MS(7,1) - MSC7,16).
`
`Asdisclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is
`
`incorporated by reference above, such a network can be operated in rearrangeably non-
`
`blocking mannerfor arbitrary fan-out multicast connections and also can be operated in
`
`strictly non-blocking mannerfor unicast connections.
`
`15
`
`In one embodimentof this network each of the input switches [S1-[S16 and
`
`output switches OS1-OS16 are crossbar switches. ‘The number of switches of input stage
`
`110 and of output stage 120 can be denoted in general with the variable = , where N is
`
`the total numberofinletlinks or outlet links. The number of middle switches in each
`
`middle stage is denoted by = . The size ofeach input switch IS1-I$16 can be denoted in
`
`20
`
`general with the notation d*2d and each output switch OS1-OS16 can be denoted in
`
`general with the notation 2d *d. Likewise, the size of each switch in any of the middle
`
`stages can be denoted as 2d * 2d. A switch as used herein can be either a crossbar
`
`switch, or a network of switches each of which in turn may be a crossbar switch or a
`
`network of switches. A symmetric multi-stage network can be represented with the
`
`25
`
`notation V,,,,,,(N.d,5), where N represents the total numberofinlet links ofall input
`
`switches (for example the links IL1-IL32), d represents the inlet links of each input
`
`switch or outlet links of each output switch, and s is the ratio of numberof outgoing
`
`links from each input switch to the inlet links of each input switch.
`
`-10-
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`Lach ofthe - input switches IS1 —IS16 are connected to exactly d switches in
`
`middle stage 130 through two links each for a total of 2xd_ links (for example input
`
`switch IS1 is connected to middle switch MS(1,1) through the middle links ML(1,1),
`
`ML(1,2), and also connected to middle switch MS(1,2) through the middle links ML(1,3)
`
`and ML(1,4)). The middle links which connect switches in the same row in two
`
`successive middle stages are called hereinafter straight middle links; and the middle links
`
`which connect switches in different rows in two successive middle stages are called
`
`hereinafter cross middle links. or example, the middle links ML(1,1) and ML(1,2)
`
`connect input switch IS1 and middle switch MS(1,1), so middle links ML(1,1) and
`
`10
`
`ML(1,2) are straight middle links; where as the middle links ML(1,3) and ML(1,4)
`
`connect input switch IS1 and middle switch MS(1,2), since input switch [S1 and middle
`
`switch MS(1,2) belong to two different rows in diagram 100A of FIG. 1A, middle links
`
`ML(1,3) and ML(1,4) are cross middle links.
`
`Eachof the - middle switches MS(1,1) - MS(1,16) in the middle stage 130 are
`
`15
`
`connected from exactly d input switches through twolinks each for a total of 2xd_ links
`
`(for example the middle links ML(1,1) and ML(1,2) are connected to the middle switch
`
`MS(1,1) from input switch IS1, and the middle links ML(1,7) and ML(1,8) are connected
`
`to the middle switch MS(1,1) from input switch IS2) and also are connected to exactly d
`
`switches in middle stage 140 through twolinks each for a total of 2xd_ links (for
`
`example the middle links ML(2,1) and ML(2,2) are connected from middle switch
`
`MS(1,1) to middle switch MS(2,1), and the middle links ML(2,3) and ML(2,4) are
`
`connected from middle switch MS(1,1) to middle switch MS(2,3)).
`
`Eachof the
`
`middle switches MS(2,1) — MS(2,16) in the middle stage 140 are
`
`connected from exactly d middle switches in middle stage 130 through two links each
`
`for a total of 2xd links (for example the middle links ML(2,1) and ML(2,2) are
`
`connected to the middle switch MS(2,1) from input switch MS(1,1), and the middle links
`
`ML(1,11) and ML(1,12) are connected to the middle switch MS(2,1) from input switch
`
`MS(,3)) and also are connected to exactly d switches in middle stage 150 through two
`
`links each for a total of 2d_links (for example the middle links ML(3,1) and ML(3,2
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`are connected from middle switch MS(2,1) to middle switch MS(3,1), and the middle
`
`links ML(3,3) and ML(3,4) are connected from middle switch MS(2,1) to middle switch
`
`MS(3,6)).
`
`Applicant notes that the topology of connections between middle switches
`
`MS(2,1) — MS(2,16) in the middle stage 140 and middle switches MS(3,1) —- MS(3,16) in
`
`the middle stage 150 is not the typical inverse Benes topology but the connectivity of the
`
`lin.
`generalized multi-link multi-stage network V,,,,,,(N,,N,,d,8) LOOA shownin FIG.1A is
`
`effectively the same, or alternatively the network 100A shownin FIG. 1A is topologically
`
`equivalent to the network with inverse Benes network topology. Howeveras will be
`
`10
`
`describedlater in layouts of FIG. 1C — FIG. 1G,the length of the connection from a given
`
`inlet link to its destination outlet links may consist of different route resulting in different
`
`latency and different powerdissipation for a given multicast or unicast assignment. As
`
`will be described later in the layouts of FIG. 1C — FIG. 1G, the connection topology of
`
`middle links between middle stages 140 and 150 is in such a waythat nearest neighbor
`
`blocks are connected directly and then the rest of the blocks are connected in inverse
`
`Benes topology.
`
`Eachof the — middle switches MS(3,1) — MS(3,16) in the middle stage 150 are
`
`connected from exactly d middle switches in middle stage 140 through twolinks each
`
`for a total of 2d links (for example the middle links ML(3,1) and ML(3,2) are
`
`20
`
`connected to the middle switch MS(@3,1) from input switch MS(,1), and the middle links
`
`ML(2,23) and ML(2,24) are connected to the middle switch MS(3,1) from input switch
`
`MS(2,6)) and also are connected to exactly d switches in middle stage 160 through two
`
`links each for a total of 2xd links (for example the middle links ML(4,1) and ML(4,2
`
`are connected from middle switch MS(3,1) to middle switch MS(4,1), and the middle
`
`25
`
`links ML(4,3) and ML(4,4) are connected from middle switch MS(3,1) to middle switch
`
`MS(4,11)).
`
`Applicant notes that the topology of connections between middle switches
`
`MS(3,1) — MS(3,16) in the middle stage 150 and middle switches MS(4,1) — MS(4,16) in
`
`the middle stage 160 is not the typical inverse Benes topology but the connectivity of the
`
`-12-
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`generalized multi-link multi-stage network V,,,,,,(V,,N,,d,s) 100A shown in T'IG, 1A is
`
`effectively the same,or alternatively the network LOOA shown in FIG. IA is topologically
`
`equivalent to the network with inverse Benes network topology. Howeveras will be
`
`described later in layouts of FIG. 1C — FIG. 1G,the length of the connection from a given
`
`inletlink to its destination outlet links may consist of different route resulting in different
`
`latency and different power dissipation for a given multicast or unicast assignment. As
`
`will be described later in the layouts of FIG. 1C — FIG. 1G,the connection topology of
`
`middle links between middle stages 150 and 160 is in such a way that nearest neighbor
`
`blocks are connected directly and then the rest of the blocks are connected in inverse
`
`10
`
`Benestopology.
`
`Each of the - middle switches MS(4,1) — MS(4,16) in the middle stage 160 are
`
`connected from exactly d middle switches in middle stage 150 through twolinks each
`
`for a total of 2xd links (for example the middle links ML(4,1) and ML(4,2) are
`
`connected to the middle switch MS(4,1) from input switch MS(3,1), and the middle links
`
`15
`
`ML(4,43) and ML(4,44) are connected to the middle switch MS(4,1) from input switch
`
`MS(3,11)) and also are connected to exactly d switches in middle stage 170 through two
`
`links each for a total of 2xd_ links (for example the middle links ML(5,1) and ML(5,2
`
`are connected from middle switch MS(4,1) to middle switch MS(5,1), and the middle
`
`links ML(5,3) and ML(5,4) are connected from middle switch MS(4,1) to middle switch
`
`20
`
`MS(5,11)).
`
`Applicant notes that the topology of connections between middle switches
`
`MS(4,1) — MS(4,16) in the middle stage 160 and middle switches MS(5,1) — MS(5,16) in
`
`the middle stage 170 is not the typical inverse Benes topology but the connectivity of the
`
`generalized multi-link multi-stage network V,,,,,,(NV,,N,,d,8) 100A shown in FIG, 1A is
`
`25
`
`effectively the sameor alternatively the network 100A shownin FIG. 1A is topologically
`
`equivalent to the network with inverse Benes network topology. Howeveras will be
`
`describedlater in layouts of FIG. 1C — FIG. 1G,the length of the connection from a given
`
`inlet link to its destination outlet links may consist of different route resulting in different
`
`latency and different powerdissipation for a given multicast or unicast assignment. As
`
`30
`
`will be described later in the layouts of FIG. 1C — FIG. 1G, the connection topology of
`
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`middle links between middle stages 160 and 170is in such a waythat nearest neighbor
`
`blocks are connected directly and then the rest of the blocks are connected in inverse
`
`Benestopology.
`
`Eachof the > middle switches MS(5,1) — MS(5,16) in the middle stage 170 are
`
`connected from exactly d middle switches in middle stage 160 through two links each
`
`for a total of 2xd links (for example the middle links ML(5,1) and ML(5,2) are
`
`connected to the middle switch MS(5,1) from input switch MS(4,1), and the middle links
`
`ML(5,43) and ML(5,44) are connected to the middle switch MS(5,1) from input switch
`
`MS(4,11)) and also are connected to exactly d switches in middle stage 180 through two
`
`10
`
`links each for a total of 2xd_ links (for example the middle links ML(6,1) and ML(6,2
`
`are connected from middle switch MS(5,1) to middle switch MS(6,1), and the middle
`
`links ML(6,3) and ML(6,4) are connected from middle switch MS(5,1) to middle switch
`
`MS(6,6)).
`
`Applicant notesthat the topology of connections between middle switches
`
`15
`
`MS(5,1) — MS(5,16) in the middle stage 170 and middle switches MS(6,1) —- MS(6,16) in
`
`the middle stage 180 is not the typical inverse Benes topology but the connectivity of the
`
`generalized multi-link multi-stage network V,,,,,,(V,,N,,d,8) 100A shown in FIG, 1A is
`
`effectively the sameor alternatively the network 100A shownin FIG.1A is topologically
`
`equivalent to the network with inverse Benes network topology. Howeveras will be
`
`20
`
`described later in layouts of FIG. 1C — FIG. 1G,the length ofthe connection from a given
`
`inlet link to its destination outlet links may consist of different route resulting in different
`
`latency and different power dissipation for a given multicast or unicast assignment. As
`
`will be described later in the layouts of FIG. 1C — FIG. 1G, the connection topology of
`
`middle links between middle stages 170 and 180 is in such a way that nearest neighbor
`
`25
`
`blocks are connected directly and then the rest of the blocks are connected in inverse
`
`Benes topology.
`
`Each of the - middle switches MS(6,1) — MS(6,16) in the middle stage 180 are
`
`connected from exactly d middle switches in middle stage 170 through twolinks each
`
`for a total of 2Xd links (for example the middle links ML(6,1) and ML(6,2) are
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`connected to the middle switch MS(6,1) from input switch MS(5,1), and the middle links
`
`ML(6,23) and ML({6,24) are connected to the middle switch MS(6,1) from input switch
`
`MS4,6)) and also are connected to exactly d switches in middle stage 190 through two
`
`links each for a total of 2d_links (for example the middle links ML(7,1) and ML{7,2
`
`are connected from middle switch MS(6,1) to middle switch MS(7,1), and the middle
`
`links ML(7,3) and ML(7,4) are connected from middle switch MS(6,1) to middle switch
`
`MS(7,3)).
`
`Eachof the - middle switches MS(7,1) — MS(7,16) in the middle stage 190 are
`
`connected from exactly d middle switches in middle stage 180 through two links each
`
`10
`
`for a total of 2xd links (for example the middle links ML(7,1) and ML(7,2) are
`
`connected to the middle switch MS(7,1) from input switch MS(6,1), and the middle links
`
`ML(7,11) and ML(7,12) are connected to the middle switch MS(7,1) from input switch
`
`MS(6,3)) and also are connected to exactly d switches in middle stage 120 through two
`
`links each for a total of 2xd_ links (for example the middle links ML(8,1) and ML(8,2
`
`15
`
`are connected from middle switch MS(7,1) to middle switch MS(8,1), and the middle
`
`links ML(8,3) and ML(8,4) are connected from middle switch MS(7,1) to middle switch
`
`OS2).
`
`Each of the - middle switches OS1 — OS16 in the middle stage 120 are
`
`connected from exactly d middle switches in middle stage 190 through two links each
`
`for a total of 2xd links (for example the middle links ML(8,1) and ML(@8,2) are
`
`connected to the output switch OS1 from input switch MS(7,1), and the middle links
`
`ML(8,7) and ML(8,8) are connected to the output switch OS1 from input switch
`
`MS(7,2)).
`
`Finally the connection topology of the network 100A shownin FIG. 1A is
`
`25
`
`logically similar to back to back inverse Benes connection topology with nearest neighbor
`
`connections betweenall the middle stages starting from middle stage 140 and middle
`
`stage 180.
`
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`Referring to diagram 100B in FIG. 1B, is a folded version of the multi-link multi-
`
`stage network 100A shownin FIG. 1A. The network 100B in FIG. 1B showsinputstage
`
`110 and output stage 120 are placed together. That is input switch IS1 and output switch
`
`OS1 are placed together, input switch IS2 and output switch OS2 are placed together, and
`
`similarly input switch [S16 and output switch OS16 are placed together. All the right
`
`going links {ie., inlet links IL1 — IL32 and middle links ML(1,1) - ML(1,64)} correspond
`
`to input switches IS1 - [S16, and all the left going links {i.e., middle links ML(8,1) -
`
`ML(8,64) and outlet links OL1-OL32} correspond to output switches OS1 - OS16.
`
`Middle stage 130 and middle stage 190 are placed together. That is middle
`
`10
`
`switches MS(1,1) and MS(7,1) are placed together, middle switches MS(1,2) and
`
`MS(7,2) are placed together, and similarly middle switches MS(1,16) and MS(7,16) are
`
`placed together. All the right going middle links {i.e., mid