UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`FLEX LOGIX TECHNOLOGIES, INC.
`Petitioner
`
`v.
`
`KONDA TECHNOLOGIES INC.
`Patent Owner
`
`____________________
`
`Patent No. 10,003,553 B2
`____________________
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`DECLARATION OF R. JACOB BAKER, PH.D., P.E.
`IN SUPPORT OF PETITION FOR POST GRANT REVIEW
`OF U.S. PATENT NO. 10,050,553
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`Page 1 of 179
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`FLEX LOGIX EXHIBIT 1002
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
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`TABLE OF CONTENTS
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`INTRODUCTION .......................................................................................... 1
`I.
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`II.
`III. MATERIALS REVIEWED ........................................................................... 5
`IV. PERSON OF ORDINARY SKILL IN THE ART ......................................... 7
`V.
`TECHNICAL BACKGROUND .................................................................... 8
`A.
`Field-Programmable Gate Arrays (FPGAs) ......................................... 9
`VI. OVERVIEW OF THE ’553 PATENT ......................................................... 17
`VII. CLAIM CONSTRUCTION ......................................................................... 36
`VIII. THE ’814 PCT APPLICATION, THE ’615 PROVISIONAL
`APPLICATION, AND THE ’168 APPLICATION DO NOT
`SUPPORT THE FEATURES OF CLAIMS 1, 2, 4, 9, 11, 12, AND 14 ..... 36
`A.
`Claim 9 ............................................................................................... 37
`B.
`Claims 1, 2, and 4 ............................................................................... 40
`1.
`“Zero Or More Cross Links Connected From a Switch in
`a Stage in a Subnetwork to a Switch in the Same
`Numbered Stage in One or More Other Subnetworks”
`(Claim 1) .................................................................................. 42
`“Said Cross Links Between Switches of Stages In Any
`Two Said Subnetworks Are Connected As Either Vertical
`Links Only, Or Horizontal Links Only, Or Both Vertical
`Links And Horizontal Links” (Claim 2) .................................. 46
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`2.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
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`3.
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`4.
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`
`
`X.
`
`“Said Horizontal Links Between Switches in Two Said
`Stages Are Substantially of Equal Length and Said
`Vertical Links Between Switches in Two Said Stages Are
`Substantially Of Equal Length in the Entire Two-
`Dimensional Grid of Rows and Columns” (Claim 4) .............. 48
`“Said Horizontal Links Between Switches in Two Said
`Stages are Substantially of a Hop Length h and said
`Vertical Links Between Switches in Two Said Stages are
`Substantially of a Hop Length v Where h ≥ 0 and v ≥ 0”
`(Claim 4) .................................................................................. 49
`Claims 11, 12, and 14 ......................................................................... 51
`C.
`IX. OVERVIEW OF THE PRIOR ART ............................................................ 52
`A. Wong ................................................................................................... 52
`THE PRIOR ART DISCLOSES ALL OF THE FEATURES OF
`CLAIMS 1-5, 9-15, and 17-19 OF THE ’553 PATENT .............................. 58
`A. Wong Discloses the Features of Claims 1-7, 9-15, and 17-19 ........... 58
`1.
`Claim 1 .................................................................................... 64
`2.
`Claim 2 .................................................................................. 140
`3.
`Claim 3 .................................................................................. 141
`4.
`Claim 4 .................................................................................. 145
`5.
`Claim 5 .................................................................................. 147
`6.
`Claim 6 .................................................................................. 147
`7.
`Claim 7 .................................................................................. 148
`8.
`Claim 9 .................................................................................. 149
`9.
`Claim 10 ................................................................................ 152
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
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`10. Claim 11 ................................................................................ 153
`11. Claim 12 ................................................................................ 169
`12. Claim 13 ................................................................................ 170
`13. Claim 14 ................................................................................ 170
`14. Claim 15 ................................................................................ 171
`15. Claim 17 ................................................................................ 172
`16. Claim 18 ................................................................................ 173
`17. Claim 19 ................................................................................ 173
`XI. CONCLUSION ........................................................................................... 175
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`
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`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by Flex Logix, Inc. (“Petitioner”) as an
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`independent expert consultant in this proceeding before the United States Patent
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`and Trademark Office (“PTO”) regarding U.S. Patent No. 10,003,553 (“the ’553
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`patent”) (Ex. 1001).1 I have been asked to consider whether certain references
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`discloses the features recited in claims 1-7, 9-15, and 17-19 of the ’553 patent. My
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`opinions are set forth below.
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`2.
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`I am being compensated at a rate of $615/hour for my work in this
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`proceeding. My compensation is in no way contingent on the nature of my
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`findings, the presentation of my findings in testimony, or the outcome of this or
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`any other proceeding. I have no other interest in this proceeding.
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`II. BACKGROUND AND QUALIFICATIONS
`3.
`I presently serve as a Professor of Electrical and Computer
`
`Engineering at the University of Nevada, Las Vegas (UNLV). All of my opinions
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`stated in this declaration are based on my own personal knowledge and
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`1 Where appropriate, I refer to exhibits that I understand are to be attached to the
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`petition for Post Grant Review of the ’553 patent.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`professional judgment. In forming my opinions, I have relied on my knowledge
`
`and experience in designing, developing, researching, and teaching regarding
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`circuit design and memory devices referenced in this declaration.
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`4.
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`I am over 18 years of age and, if I am called upon to do so, I would be
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`competent to testify as to the matters set forth herein. I understand that a copy of
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`my current curriculum vitae, which details my education and professional and
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`academic experience, is being submitted by Petitioner. The following provides an
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`overview of some of my experience that is relevant to the matters set forth in this
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`declaration.
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`5.
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`I have been teaching electrical engineering at UNLV since 2012.
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`Prior to this position, I was a Professor of Electrical and Computer Engineering at
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`Boise State University from 2000. Prior to my position at Boise State University, I
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`was an Associate Professor Electrical Engineering between 1998 and 2000 and
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`Assistant Professor of Electrical Engineering between 1993 and 1998 at the
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`University of Idaho. I have been teaching electrical engineering since 1991.
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`6.
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`I received my Ph.D. in Electrical Engineering from the University of
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`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
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`from UNLV in 1988 and 1986, respectively.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`As described in my curriculum vitae, which I understand is being
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`7.
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`provided as Exhibit 1003, I am a licensed Professional Engineer in the state of
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`Idaho and have more than 30 years of experience, including extensive experience
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`in circuit designs for networks and communications including the design of
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`modems, driver circuits, phase- and delay-locked loops for PCI, USB, and DDR
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`standard specifications.
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`8.
`
`I have taught courses in integrated circuit design (analog, digital,
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`mixed-signal, memory circuit design, etc.), linear circuits, microelectronics,
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`communication systems, and fiber optics. As a professor, I have been the main
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`advisor to seven Doctoral students and 79 Master’s students.
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`9.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
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`(two editions), CMOS Circuit Design, Layout, and Simulation (four editions), and
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`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and
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`coauthored, more than 100 papers and presentations in the areas of solid-state
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`circuit design, the design of field programmable gate array (FPGA) data
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`converters, and circuits used in standard specification implementations including
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`double data rate (DDR) for communications. I am the named inventor on 149
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`granted U.S. patents in CMOS integrated circuit designs including array topologies
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`3
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`including flash memory and DRAM. My textbook CMOS Circuit Design, Layout,
`
`and Simulation includes, among other things, sections covering digital logic gates
`
`as well as phase- and delay-locked loops for networking and communications.
`
`10.
`
`I have received numerous awards for my work, including the
`
`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
`
`Award is bestowed annually upon an outstanding young electrical/computer
`
`engineering educator in recognition of the educator’s contributions to the
`
`profession.
`
`11.
`
`I am a Fellow of the IEEE for contributions to memory circuit design.
`
`I have also received the IEEE Circuits and Systems Education Award (2011).
`
`12.
`
`I have received the President’s Research and Scholarship Award
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`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
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`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`University. I have also received the Tau Beta Pi Outstanding Electrical and
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`Computer Engineering Professor award the four years I have been at UNLV.
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`13.
`
`I am not an attorney and offer no legal opinions, but in the course of
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`my work, I have had experience studying and analyzing patents and patent claims
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`from the perspective of a person skilled in the art.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`III. MATERIALS REVIEWED
`14. The opinions contained in this Declaration are based on the
`
`documents I reviewed, my professional judgment, as well as my education,
`
`experience, and knowledge regarding integrated circuits, including networks and
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`switches used to implement field programmable gate arrays (FPGAs).
`
`15.
`
`In forming my opinions expressed in this Declaration, I reviewed the
`
`’553 patent (Ex. 1001); File History of the ’553 patent (Ex. 1004); File History of
`
`U.S. Application No. 14/199,168 (Ex. 1005); Application Body As Filed of PCT
`
`Application No. PCT/US12/53814 (Ex. 1006); File History of U.S. Provisional
`
`Application No. 61/531,615 (Ex. 1007); U.S. Patent No. 6,940,308 (“Wong”) (Ex.
`
`1008); U.S. Patent No. 8,270,400, issued on September 18, 2012 (Ex. 1011); PCT
`
`Application No. PCTUS0856064 (Ex. 1012); File History of U.S. Provisional
`
`Application No. 60/905,526 (Ex. 1013); File History of U.S. Provisional
`
`Application. No. 60/940,383 (Ex. 1014); U.S. Pat. No. 8,170,040, issued May 1,
`
`2012 (Ex. 1015); PCT Application No. PCT/US08/64603 (Ex. 1016); File History
`
`of U.S. Provisional Application No. 60/940,387 (Ex. 1017); File History of U.S.
`
`Provisional Application No. 60/940,390 (Ex. 1018); U.S. Pat. No. 8,363,649 (Ex.
`
`1019); PCT Application No. PCT/U08/64604 (Ex. 1020); File History of U.S.
`
`Provisional Application No. 60/940,389 (Ex. 1021); File History of U.S.
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`Provisional Application No. 60/940,391 (Ex. 1022); File History of U.S.
`
`Provisional Application No. 60/940,392 (Ex. 1023); U.S. Pat. No. 8,269,523,
`
`issued September 18, 2012 (Ex. 1024); PCT Application No. PCT/US08/64605
`
`(Ex. 1025); File History of U.S. Provisional Application No. 60/940,394 (Ex.
`
`1026); U.S. Pat. No. 8,898,611, issued Nov. 25, 2014 (Ex. 1027); PCT Application
`
`No. PCT/US10/52984 (Ex. 1028); File History of U.S. Provisional Application No.
`
`61/252,603 (Ex. 1029); File History of U.S. Provisional Application No.
`
`61/252,609 (Ex. 1030); File History of U.S. Application No. 14/329,876 (Ex.
`
`1031); U.S. Patent No. 9,509,634, issued on Nov. 29, 2016 (Ex. 1032); File
`
`History of U.S. Provisional Application No. 61/846,083 (Ex. 1033); File History of
`
`U.S. Patent Application No. 12/601,275 (issued as U.S. Patent 8,269,523 submitted
`
`as Ex. 1024) (Ex. 1034); U.S. Patent No. 9,374,322, issued June 21, 2016 (issued
`
`from U.S. Application No. 14/199,168 submitted as Ex. 1005) (Ex. 1035); File
`
`History of U.S. Provisional Application No. 60/984,724 (Ex. 1039); U.S. Patent
`
`No. 3,358,269 (Ex. 1040); and any other materials I refer to in this Declaration in
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`support of my opinions.
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`16. All of the opinions contained in this declaration are based on the
`
`documents I reviewed and my knowledge and professional judgment. My opinions
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`have also been guided by my appreciation of how a person of ordinary skill in the
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`art would have understood the claims and the specification of the ’553 patent at the
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`time of the alleged invention, which I have been asked to initially consider was the
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`early-to-mid 2010s timeframe (including September 7, 2011, the filing date of U.S.
`
`Provisional Patent Application No. 61/531,615, which I understand is the earliest
`
`possible priority date for the ’553 patent.). My opinions reflect how one of
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`ordinary skill in the art would have understood the ’553 patent, the prior art to the
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`patent, and the state of the art at the time of the alleged invention.
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`17. Based on my experience and expertise, it is my opinion that certain
`
`references disclose the features recited in claims 1-7, 9-15, and 17-19 of the ’553
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`patent.
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`IV. PERSON OF ORDINARY SKILL IN THE ART
`18.
`I am familiar with the level of ordinary skill in the art with respect to
`
`the alleged inventions of the ’553 patent as of what I understand is the earliest
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`possible priority date of September 7, 2011, which is the filing date of U.S.
`
`Provisional Patent Application No. 61/531,615 to which the ’553 patent claims
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`priority. Specifically, based on my review of the ’553 patent, the technology, the
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`educational level and experience of active workers in the field, the types of
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`problems faced by workers in the field, the solutions found to those problems, the
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`sophistication of the technology in the field, and drawing on my own experience, I
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`believe a person of ordinary skill in the art would have had would have had a
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`master’s degree in electrical engineering or a similar field, and at least two to three
`
`years of experience with integrated circuits and networks. More education can
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`supplement practical experience and vice versa. Depending on the engineering
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`background and level of education of a person, it would have taken a few years for
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`the person to become familiar with the problems encountered in the art and to
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`become familiar with the prior and current solutions to those problems.
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`19. All of my opinions in this declaration are from the perspective of one
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`of ordinary skill in the art, as I have defined it here, during the relevant timeframe,
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`i.e., early-to-mid 2010s.
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`V. TECHNICAL BACKGROUND
`20.
`In this section, I present a brief overview of certain aspects of
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`switching networks and FPGAs at the time of the alleged invention that will assist
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`in better understanding the ’553 patent and the prior art that I discuss in this
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`declaration. For example, the prior art I discuss in this declaration and the ’553
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`patent generally relates to switching networks that can be used to route signals
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`between logic blocks included on an integrated circuit device. Below, I begin with
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`a description of some fundamental aspects of FPGAs such as those described in the
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`’553 patent and/or prior art references cited in this declaration.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`A.
`Field-Programmable Gate Arrays (FPGAs)
`21. Wong (Ex. 1008), which issued on September 6, 2005, provides a
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`good overview of FPGAs and example networks used in FPGAs. FPGAs are
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`integrated circuits that are designed to allow a user to configure the circuitry of the
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`FPGA to perform a desired function after the FPGA integrated circuit has already
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`been manufactured. (Ex. 1008 at 1:18-21.) As the name implies, FPGAs include
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`an array or arrays of programmable logic blocks (e.g., gates), where the
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`connections between the logic blocks can be set up after manufacturing and
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`therefore are considered to be “field-programmable.” In other words, once
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`manufacturing is complete, the FPGA integrated circuit device includes logic and a
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`network interconnecting the logic, where the user can configure the logic and
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`interconnection network such that the FPGA performs a desired processing
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`function. The interconnection network on the FPGA is used to provide the
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`configurable connections between the programmable logic blocks. (Id. at 1:22-25.)
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`22.
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`In FPGAs such as those discussed in Wong, the interconnection
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`network that connects the logic blocks includes links between programmable
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`switches, where the links provide connections between the switches and also
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`provide connections from the switches to the logic blocks in the FPGA. As such,
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`the links are the inputs to, and outputs from, the switches. Within each switch, the
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`inputs to the switch are programmably routed to particular outputs of the switch.
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`(Id. at 1:61-2:6.) For example, figure 3D of Wong below illustrates an
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`interconnection network that includes a plurality of switches 20 (shown as square
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`boxes) that can be used to route any of the inputs to the network on the left to any
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`of the outputs of the network on the right. (Id. at 4:18-26, FIG. 3D.) The arrows
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`between the switches correspond to the “links” in the network. According to
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`Wong, the particular network illustrated in figure 3D is an 8x8 Benes network that
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`has eight inputs and eight outputs. (Id. at 2:36-37.)
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`(Id. at FIG. 3D.)
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`23. Each of the switches 20 shown in the network of figure 3D above is a
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`2x2 switch that has two inputs and two outputs. (Id. at 2:31-37, 5:4-6.) As shown
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`in figures 2A and 2B of Wong below, each switch can be set up in either a “pass”
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`configuration where the inputs are passed straight through to the outputs or set up
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`in a “cross” configuration where the upper input is routed to the lower output and
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`vice-versa. (Id. at 2:27-29, 5:6-13.)
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`(Id. at FIGs. 2A, 2B.)
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`24. A controlling configuration bit is used to determine how the inputs to
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`the switch are routed to the outputs of the switch (e.g., whether the switch is in a
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`“pass” or “cross” configuration). (Id. at 3:48-50.) For example, figure 2C of
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`Wong, replicated below, shows how multiplexers are used to implement a 2x2
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`switch with the functionality of the switches shown in figures 2A and 2B. The
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`multiplexers are controlled by a configuration bit or control bit that is used to
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`determine which outputs are connected to which inputs of the switch.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`(Ex. 1008 at FIG. 2C (annotated).)
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`25. By controlling the individual switches in the network, the routing of
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`the inputs to the network to selected outputs can be controlled. By placing some of
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`the switches in the “pass” configuration and others in the “cross” configuration, the
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`network of switches can be used to route any of the eight inputs to any of the eight
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`outputs. (Id. at 5:65-67.) For example, as shown in figure 3E of Wong below, a
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`particular configuration of the switches reverses the ordering of input signals at the
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`output terminals of the network. (Id. at 2:38-40, 5:67-6:5.) For example, by
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`setting each of the switches to be either “pass” or “cross” as shown below in figure
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`U.S. Patent No. 10,003,553
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`3E, the top-most input on the left (“000”) is routed such that it comes out at the
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`bottom-most output on the right, whereas the bottom-most input on the left (“111”)
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`is routed to the top-most output on the right. In traversing the network, each of the
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`inputs to the network passes through five switches in the network.
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`(Id. at FIG. 3E.)
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`26. As demonstrated by Wong, it was well known long before the time of
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`the alleged invention in the ’553 patent to use networks, such as, for example, the
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`one depicted above in figure 3E of Wong, in FPGA devices. Moreover, it was also
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`well known to modify such networks in order to make them more efficient as the
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`interconnection network for an FPGA. For example, because the logic cells used
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`in the FPGA include both inputs and outputs, the network can be folded in half in
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
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`order to put both the inputs to the network and the outputs from the network
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`adjacent to each other for easy connection to the inputs and outputs of the logic
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`cells. (Id. at 6:52-61.) Such folding is illustrated by figure 4A of Wong, where the
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`folding is done along the dotted line 31. (Id. at 6:65-67.)
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`(Id. at FIG. 4A.)
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`27. The resulting folded network is shown in figures 4B and 4C of Wong
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`below, where figure 4C has rearranged the connections between the switches in the
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`network so that the shorter connections are closer to the logic cells, which are
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`placed on the left hand side of the network. (Id. at 7:6-21.) As can be seen in
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`figures 4B and 4C, folding the network puts switches 1.1 and 5.1 together and
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`switches 2.1 and 4.1 together.
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`U.S. Patent No. 10,003,553
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`(Id. at FIGs. 4B, 4C.)
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`28. A physical layout of the network shown in figure 4C with the
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`accompanying logic cells for an FPGA is shown below in figure 13A of Wong.
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`The physical layout shown in Figure 13A includes the network of switches 82 and
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`associated logic cells 81. (Id. at 13:12-26.)
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`U.S. Patent No. 10,003,553
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`(Id. at FIG. 13A.)
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`29. A person of ordinary skill in the art would have understood that the
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`physical layout corresponds to how the circuitry is physically arranged on the
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`integrated circuit device. In other words, in the integrated circuit FPGA that
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`includes the network shown in figure 13A above, the logic cells 81 would be
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`arranged vertically in a column, and the switches 82 would be arrayed in rows and
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`U.S. Patent No. 10,003,553
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`columns with appropriate connections corresponding to the illustrated links
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`provided on the integrated circuit. The arrows on the right-hand side of figure 13A
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`correspond to the top level connections between the network and primary
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`input/output (I/O) of the FPGA. (Id. at 13:42-43.) A person of ordinary skill in the
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`art would have understood that the signals provided to the FPGA, which the logic
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`cells 81 are used to process, are provided on the primary inputs of the FPGA,
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`whereas the results generated by that processing are provided on the primary
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`outputs of the FPGA.
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`30. As depicted in figure 13A of Wong, logic cells 81 are included in the
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`FPGA along with switch cells 82. (Id. at 13:22-23 (“There are two logic cells 81
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`per switch cell 82….”).) The logic cells in an FPGA are used to process the inputs
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`provided to the FPGA. The processing functions performed by the logic cells are
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`often configurable by the user. As such, not only the connections between the
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`logic cells are configurable, but the actual processing functions performed by the
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`logic cells are also configurable by the user after manufacturing is complete.
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`VI. OVERVIEW OF THE ’553 PATENT
`31. The ’553 patent is entitled “Optimization of Multi-Stage Hierarchical
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`Networks for Practical Routing Applications.” (Ex. 1001 at Title.) The ’553
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`patent acknowledges that multi-stage hierarchical networks were known and used
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`in many applications at the time of the alleged invention. (Ex. 1001 at 2:66-3:1
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`(“Multi-stage interconnection networks such as Benes networks and butterfly fat
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`tree networks are widely useful in telecommunications, parallel and distributed
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`computing.”).) Practical applications where the multi-stage hierarchical networks
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`can be used include “FPGA routing of hardware designs.” (Id. at 4:47-48.)
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`32. The ’553 patent recognizes that VLSI (very large scale integration)
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`layouts for integrated circuits with such networks were known, but states that such
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`layouts are “inefficient and complicated.” (Id. at 3:2-4.) For example, the ’553
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`patent acknowledges that Wong (Ex. 1008) discloses a layout of a Benes network.2
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`(Ex. 1001 at 3:30-36). However the ’553 patent contends that prior art network
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`layouts “require large area to implement the switches on the chip, large number of
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`wires, longer wires, with increased power consumption, increased latency of the
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`signal which effect the maximum clock speed of operation.” (Id. at 3:43-48.)
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`33. Evidently in an attempt to address these issues, the ’553 patent alleges
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`to disclose “[s]ignificantly optimized multi-stage networks, useful in wide target
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`applications” where the “optimized multi-stage networks in each block employ
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`2 Benes networks were originally developed by Vaclav E. Benes at Bell Labs in the
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`mid-1960s. (See, e.g., Ex.1040 at Cover.)
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`U.S. Patent No. 10,003,553
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`several rings of stages of switches with inlet and outlet links.” (Ex. 1001 at 3:58-
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`67 (emphasis added).) Notably, each of figures 1-15 of the ’553 patent illustrates,
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`describes, or relates to the use of “rings” in a “multi-stage hierarchical network.”
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`(Id. at FIGs. 1-15, 4:42-6:22, (explicitly referring to a “multi-stage hierarchical
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`network” where the inclusion of a “ring” is provided in the description of each of
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`figures 1-15 or in the drawing itself); see also id. at 8:56-9:3 (description of rings
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`110 and 120 in figures 1A-1B), 33:26-48 (discussion of rings with respect to
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`figures 7-8).) However, as discussed below in this section, “rings,” which the ’553
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`patent describes as an important aspect of the alleged optimizations to the prior art
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`multi-stage hierarchical networks, are not recited in the claims of the ’553 patent.
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`34.
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`I understand that the ’553 patent issued June 19, 2018 from U.S.
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`Patent Application No. 15/140,470 (“the ’470 application”) (Ex. 1004), which was
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`filed April 28, 2016. (Ex. 1001 at Cover; Ex. 1004 at 203-204.) While the ’553
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`patent states that it is a continuation application that claims priority to U.S. Patent
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`Application 14/199,168 (“the ’168 application”) (Ex. 1001 at 1:8-13), I understand
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`that the ’553 patent issued without properly claiming priority to any earlier filed
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`patents or applications. (Ex. 1001 at cover page (showing no related patent data or
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`priority information); Ex. 1004 at 149.)
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`35. However, I understand that a request for a certificate of correction was
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`issued on February 19, 2019 (Ex. 1004 at 1), where the certificate states that the
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`’553 patent claims priority to the ’168 application (Ex. 1005), which in turn claims
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`priority to PCT/US12/53814 (“the ’814 PCT application”) (Ex. 1006) filed
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`September 6, 2012 and U.S. provisional application 61/531,615 (“the ’615
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`provisional application”) (Ex. 1007), filed September 7, 2011. The ’168
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`Application issued as U.S. Patent 9,374,322 (“the ’322 patent”) (Ex. 1035) on June
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`21, 2016. (Ex. 1035, Cover.) I also have been informed that U.S. Patent
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`Application 15/984,408 is currently pending and claims priority to the ’470
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`application. I have created the demonstrative below to help visualize the purported
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`priority chain for the ’553 patent.
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`U.S. Patent No. 10,003,553
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`36. As noted above, the ’470 application purports to be a continuation
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`application with respect to the ’168 application (Ex. 1004 at 7-8, Ex. 1001 at 1:8-
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`14), and the ’168 application purports to be a continuation of the ’814 PCT
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`application, which in turn describes itself as a “Continuation in Part Application
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`to” the ’615 provisional. (Ex. 1005 at 10; Ex. 1006 at 1:6-10.) Below, I
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`sometimes refer to the collection of the ’168 application, the ’814 PCT application,
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`and the ’615 provisional application as the “alleged priority applications of the
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`’553 patent.”
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`37. The ’553 patent incorporates the ’168 Application, the ’814 PCT
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`application, and the ’615 provisional application by reference. (Ex. 1001 at 1:8-
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`25.) Numerous additional patents and applications are also incorporated by
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`reference in the ’553 patent. (See, e.g., Ex. 1001 at 1:26-2:62.) I have reviewed
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`the alleged priority applications of the ’553 patent as well as the additional patents
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`and applications that are incorporated by reference in columns 1 and 2 of the ’553
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`patent, which I understand are being submitted as Exhibits 1011-1034. After
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`reviewing the claims that issued in the ’553 patent in view of the claims included
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`in the alleged priority applications of the ’553 patent, it is evident that the claims of
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`the ’553 patent are directed to subject matter that is very different than the subject
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`matter to which the claims in the alleged priority applications of the ’553 patent are
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`directed (i.e., the claims set forth in the ’168 application and the ’814 PCT
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`application).
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`38.
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`I understand that the claims that issued in the ’553 patent are derived
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`from an amendment filed January 8, 2018 (during prosecution of the ’470
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`application) in which Patent Owner canceled pending original claims 1-20 and
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`added new claims 21-40. (Ex. 1004 at 69-85.) Originally filed claims 1-20 of the
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`U.S. Patent No. 10,003,553
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`’470 application differ significantly from those filed in the amendment that
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`eventually issued in the ’553 patent. For example, the original claims all included
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`“rings,” which as I noted above are described in the specification of the ’553 patent
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`as a fundamenta