UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`FLEX LOGIX TECHNOLOGIES, INC.
`Petitioner
`
`v.
`
`KONDA TECHNOLOGIES INC.
`Patent Owner
`
`____________________
`
`Patent No. 10,003,553 B2
`____________________
`
`DECLARATION OF R. JACOB BAKER, PH.D., P.E.
`IN SUPPORT OF PETITION FOR POST GRANT REVIEW
`OF U.S. PATENT NO. 10,050,553
`
`Page 1 of 142
`
`FLEX LOGIX EXHIBIT 1002
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
`
`
`TABLE OF CONTENTS
`
`INTRODUCTION .......................................................................................... 1
`I.
`BACKGROUND AND QUALIFICATIONS ................................................ 1
`II.
`III. MATERIALS REVIEWED ........................................................................... 5
`IV. PERSON OF ORDINARY SKILL IN THE ART ......................................... 7
`V.
`TECHNICAL BACKGROUND .................................................................... 8
`A.
`Field-Programmable Gate Arrays (FPGAs) ......................................... 9
`VI. OVERVIEW OF THE ’553 PATENT ......................................................... 17
`VII. CLAIM CONSTRUCTION ......................................................................... 36
`VIII. THE ’814 PCT APPLICATION, THE ’615 PROVISIONAL
`APPLICATION, AND THE ’168 APPLICATION DO NOT
`SUPPORT THE FEATURES OF CLAIMS 1, 2, 4, 9, 11, 12, AND 14 ..... 36
`A.
`Claim 9 ............................................................................................... 37
`B.
`Claims 1, 2, and 4 ............................................................................... 40
`1.
`“Zero Or More Cross Links Connected From a Switch in
`a Stage in a Subnetwork to a Switch in the Same
`Numbered Stage in One or More Other Subnetworks”
`(Claim 1) .................................................................................. 42
`“Said Cross Links Between Switches of Stages In Any
`Two Said Subnetworks Are Connected As Either Vertical
`Links Only, Or Horizontal Links Only, Or Both Vertical
`Links And Horizontal Links” (Claim 2) .................................. 46
`
`2.
`
`
`
`
`
`i
`
`
`
`Page 2 of 142
`
`

`

`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
`
`3.
`
`4.
`
`
`
`X.
`
`“Said Horizontal Links Between Switches in Two Said
`Stages Are Substantially of Equal Length and Said
`Vertical Links Between Switches in Two Said Stages Are
`Substantially Of Equal Length in the Entire Two-
`Dimensional Grid of Rows and Columns” (Claim 4) .............. 48
`“Said Horizontal Links Between Switches in Two Said
`Stages are Substantially of a Hop Length h and said
`Vertical Links Between Switches in Two Said Stages are
`Substantially of a Hop Length v Where h ≥ 0 and v ≥ 0”
`(Claim 4) .................................................................................. 49
`Claims 11, 12, and 14 ......................................................................... 51
`C.
`IX. OVERVIEW OF THE PRIOR ART ............................................................ 52
`A.
`Published PCT Application No. WO 2008/109756 A1 (“Konda
`’756 PCT”) ......................................................................................... 52
`B. Wong ................................................................................................... 55
`THE PRIOR ART DISCLOSES ALL OF THE FEATURES OF
`CLAIMS 1-5, 9-15, and 17-19 OF THE ’553 PATENT .............................. 60
`A.
`Konda ’756 PCT Discloses the Features of Claims 1-7, 9-15,
`and 17-19 ............................................................................................ 61
`1.
`Claim 1 .................................................................................... 62
`2.
`Claim 2 .................................................................................. 104
`3.
`Claim 3 .................................................................................. 105
`4.
`Claim 4 .................................................................................. 108
`5.
`Claim 5 .................................................................................. 109
`6.
`Claim 6 .................................................................................. 110
`
`
`
`
`
`ii
`
`
`
`Page 3 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,353
`
`Claim 7 .................................................................................. 111
`7.
`Claim 9 .................................................................................. 112
`8.
`Claim 10 ................................................................................ 114
`9.
`10. Claim 11 ................................................................................ 115
`11. Claim 12 ................................................................................ 119
`12. Claim 13 ................................................................................ 121
`13. Claim 14 ................................................................................ 121
`14. Claim 15 ................................................................................ 122
`15. Claim 17 ................................................................................ 123
`16. Claim 18 ................................................................................ 124
`17. Claim 19 ................................................................................ 124
`Konda ’756 PCT in Combination with Wong Discloses or
`Suggests the Features of Claims 1-7, 9-15, and 17-19 ..................... 125
`1.
`Claim 1 .................................................................................. 125
`2.
`Claim 11 ................................................................................ 136
`3.
`Claims 2-7, 9-10, 12-15, and 17-19 ...................................... 137
`XI. CONCLUSION ........................................................................................... 138
`
`B.
`
`
`
`
`
`iii
`
`
`
`Page 4 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by Flex Logix, Inc. (“Petitioner”) as an
`
`independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office (“PTO”) regarding U.S. Patent No. 10,003,553 (“the ’553
`
`patent”) (Ex. 1001).1 I have been asked to consider whether certain references
`
`disclose or suggest the features recited in claims 1-7, 9-15, and 17-19 of the ’553
`
`patent. My opinions are set forth below.
`
`2.
`
`I am being compensated at a rate of $615/hour for my work in this
`
`proceeding. My compensation is in no way contingent on the nature of my
`
`findings, the presentation of my findings in testimony, or the outcome of this or
`
`any other proceeding. I have no other interest in this proceeding.
`
`II. BACKGROUND AND QUALIFICATIONS
`3.
`I presently serve as a Professor of Electrical and Computer
`
`Engineering at the University of Nevada, Las Vegas (UNLV). All of my opinions
`
`stated in this declaration are based on my own personal knowledge and
`
`
`1 Where appropriate, I refer to exhibits that I understand are to be attached to the
`
`petition for Post Grant Review of the ’553 patent.
`
`
`
`
`
`1
`
`
`
`Page 5 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`professional judgment. In forming my opinions, I have relied on my knowledge
`
`and experience in designing, developing, researching, and teaching regarding
`
`circuit design and memory devices referenced in this declaration.
`
`4.
`
`I am over 18 years of age and, if I am called upon to do so, I would be
`
`competent to testify as to the matters set forth herein. I understand that a copy of
`
`my current curriculum vitae, which details my education and professional and
`
`academic experience, is being submitted by Petitioner. The following provides an
`
`overview of some of my experience that is relevant to the matters set forth in this
`
`declaration.
`
`5.
`
`I have been teaching electrical engineering at UNLV since 2012.
`
`Prior to this position, I was a Professor of Electrical and Computer Engineering at
`
`Boise State University from 2000. Prior to my position at Boise State University, I
`
`was an Associate Professor Electrical Engineering between 1998 and 2000 and
`
`Assistant Professor of Electrical Engineering between 1993 and 1998 at the
`
`University of Idaho. I have been teaching electrical engineering since 1991.
`
`6.
`
`I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
`
`from UNLV in 1988 and 1986, respectively.
`
`
`
`
`
`2
`
`
`
`Page 6 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`As described in my curriculum vitae, which I understand is being
`
`7.
`
`provided as Exhibit 1003, I am a licensed Professional Engineer in the state of
`
`Idaho and have more than 30 years of experience, including extensive experience
`
`in circuit designs for networks and communications including the design of
`
`modems, driver circuits, phase- and delay-locked loops for PCI, USB, and DDR
`
`standard specifications.
`
`8.
`
`I have taught courses in integrated circuit design (analog, digital,
`
`mixed-signal, memory circuit design, etc.), linear circuits, microelectronics,
`
`communication systems, and fiber optics. As a professor, I have been the main
`
`advisor to seven Doctoral students and 79 Master’s students.
`
`9.
`
`I am the author of several books covering the area of integrated circuit
`
`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
`
`(two editions), CMOS Circuit Design, Layout, and Simulation (four editions), and
`
`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and
`
`coauthored, more than 100 papers and presentations in the areas of solid-state
`
`circuit design, the design of field programmable gate array (FPGA) data
`
`converters, and circuits used in standard specification implementations including
`
`double data rate (DDR) for communications. I am the named inventor on 149
`
`granted U.S. patents in CMOS integrated circuit designs including array topologies
`
`
`
`
`
`3
`
`
`
`Page 7 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`including flash memory and DRAM. My textbook CMOS Circuit Design, Layout,
`
`and Simulation includes, among other things, sections covering digital logic gates
`
`as well as phase- and delay-locked loops for networking and communications.
`
`10.
`
`I have received numerous awards for my work, including the
`
`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
`
`Award is bestowed annually upon an outstanding young electrical/computer
`
`engineering educator in recognition of the educator’s contributions to the
`
`profession.
`
`11.
`
`I am a Fellow of the IEEE for contributions to memory circuit design.
`
`I have also received the IEEE Circuits and Systems Education Award (2011).
`
`12.
`
`I have received the President’s Research and Scholarship Award
`
`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
`
`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`University. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor award the four years I have been at UNLV.
`
`13.
`
`I am not an attorney and offer no legal opinions, but in the course of
`
`my work, I have had experience studying and analyzing patents and patent claims
`
`from the perspective of a person skilled in the art.
`
`
`
`
`
`4
`
`
`
`Page 8 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`III. MATERIALS REVIEWED
`14. The opinions contained in this Declaration are based on the
`
`documents I reviewed, my professional judgment, as well as my education,
`
`experience, and knowledge regarding integrated circuits, including networks and
`
`switches used to implement field programmable gate arrays (FPGAs).
`
`15.
`
`In forming my opinions expressed in this Declaration, I reviewed the
`
`’553 patent (Ex. 1001); File History of the ’553 patent (Ex. 1004); File History of
`
`U.S. Application No. 14/199,168 (Ex. 1005); Application Body As Filed of PCT
`
`Application No. PCT/US12/53814 (Ex. 1006); File History of U.S. Provisional
`
`Application No. 61/531,615 (Ex. 1007); U.S. Patent No. 6,940,308 (“Wong”) (Ex.
`
`1008); PCT Publication No. WO 2008/109756 A1 (“the Konda ’756 PCT”),
`
`published September 12, 2008 (Ex. 1009); As-Filed Disclosure of U.S. Provisional
`
`Application 60/984,724 (Ex. 1010); U.S. Patent No. 8,270,400, issued on
`
`September 18, 2012 (Ex. 1011); PCT Application No. PCTUS0856064 (Ex. 1012);
`
`File History of U.S. Provisional Application No. 60/905,526 (Ex. 1013); File
`
`History of U.S. Provisional Application. No. 60/940,383 (Ex. 1014); U.S. Pat. No.
`
`8,170,040, issued May 1, 2012 (Ex. 1015); PCT Application No. PCT/US08/64603
`
`(Ex. 1016); File History of U.S. Provisional Application No. 60/940,387 (Ex.
`
`1017); File History of U.S. Provisional Application No. 60/940,390 (Ex. 1018);
`
`
`
`
`
`5
`
`
`
`Page 9 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`U.S. Pat. No. 8,363,649 (Ex. 1019); PCT Application No. PCT/U08/64604 (Ex.
`
`1020); File History of U.S. Provisional Application No. 60/940,389 (Ex. 1021);
`
`File History of U.S. Provisional Application No. 60/940,391 (Ex. 1022); File
`
`History of U.S. Provisional Application No. 60/940,392 (Ex. 1023); U.S. Pat. No.
`
`8,269,523, issued September 18, 2012 (Ex. 1024); PCT Application No.
`
`PCT/US08/64605 (Ex. 1025); File History of U.S. Provisional Application No.
`
`60/940,394 (Ex. 1026); U.S. Pat. No. 8,898,611, issued Nov. 25, 2014 (Ex. 1027);
`
`PCT Application No. PCT/US10/52984 (Ex. 1028); File History of U.S.
`
`Provisional Application No. 61/252,603 (Ex. 1029); File History of U.S.
`
`Provisional Application No. 61/252,609 (Ex. 1030); File History of U.S.
`
`Application No. 14/329,876 (Ex. 1031); U.S. Patent No. 9,509,634, issued on Nov.
`
`29, 2016 (Ex. 1032); File History of U.S. Provisional Application No.
`
`61/846,083 (Ex. 1033); File History of U.S. Patent Application No. 12/601,275
`
`(issued as U.S. Patent 8,269,523 submitted as Ex. 1024) (Ex. 1034); U.S. Patent
`
`No. 9,374,322, issued June 21, 2016 (issued from U.S. Application No. 14/199,168
`
`submitted as Ex. 1005) (Ex. 1035); File History of U.S. Provisional Application
`
`No. 60/984,724 (Ex. 1039); U.S. Patent No. 3,358,269 (Ex. 1040); and any other
`
`materials I refer to in this Declaration in support of my opinions.
`
`
`
`
`
`6
`
`
`
`Page 10 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`16. All of the opinions contained in this declaration are based on the
`
`documents I reviewed and my knowledge and professional judgment. My opinions
`
`have also been guided by my appreciation of how a person of ordinary skill in the
`
`art would have understood the claims and the specification of the ’553 patent at the
`
`time of the alleged invention, which I have been asked to initially consider was the
`
`early-to-mid 2010s timeframe (including September 7, 2011, the filing date of U.S.
`
`Provisional Patent Application No. 61/531,615, which I understand is the earliest
`
`possible priority date for the ’553 patent.). My opinions reflect how one of
`
`ordinary skill in the art would have understood the ’553 patent, the prior art to the
`
`patent, and the state of the art at the time of the alleged invention.
`
`17. Based on my experience and expertise, it is my opinion that certain
`
`references disclose or suggest the features recited in claims 1-7, 9-15, and 17-19 of
`
`the ’553 patent.
`
`IV. PERSON OF ORDINARY SKILL IN THE ART
`18.
`I am familiar with the level of ordinary skill in the art with respect to
`
`the alleged inventions of the ’553 patent as of what I understand is the earliest
`
`possible priority date of September 7, 2011, which is the filing date of U.S.
`
`Provisional Patent Application No. 61/531,615 to which the ’553 patent claims
`
`priority. Specifically, based on my review of the ’553 patent, the technology, the
`
`
`
`
`
`7
`
`
`
`Page 11 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`educational level and experience of active workers in the field, the types of
`
`problems faced by workers in the field, the solutions found to those problems, the
`
`sophistication of the technology in the field, and drawing on my own experience, I
`
`believe a person of ordinary skill in the art would have had would have had a
`
`master’s degree in electrical engineering or a similar field, and at least two to three
`
`years of experience with integrated circuits and networks. More education can
`
`supplement practical experience and vice versa. Depending on the engineering
`
`background and level of education of a person, it would have taken a few years for
`
`the person to become familiar with the problems encountered in the art and to
`
`become familiar with the prior and current solutions to those problems.
`
`19. All of my opinions in this declaration are from the perspective of one
`
`of ordinary skill in the art, as I have defined it here, during the relevant timeframe,
`
`i.e., early-to-mid 2010s.
`
`V. TECHNICAL BACKGROUND
`20.
`In this section, I present a brief overview of certain aspects of
`
`switching networks and FPGAs at the time of the alleged invention that will assist
`
`in better understanding the ’553 patent and the prior art that I discuss in this
`
`declaration. For example, the prior art I discuss in this declaration and the ’553
`
`patent generally relates to switching networks that can be used to route signals
`
`
`
`
`
`8
`
`
`
`Page 12 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`between logic blocks included on an integrated circuit device. Below, I begin with
`
`a description of some fundamental aspects of FPGAs such as those described in the
`
`’553 patent and/or prior art references cited in this declaration.
`
`A.
`Field-Programmable Gate Arrays (FPGAs)
`21. Wong (Ex. 1008), which issued on September 6, 2005, provides a
`
`good overview of FPGAs and example networks used in FPGAs. FPGAs are
`
`integrated circuits that are designed to allow a user to configure the circuitry of the
`
`FPGA to perform a desired function after the FPGA integrated circuit has already
`
`been manufactured. (Ex. 1008 at 1:18-21.) As the name implies, FPGAs include
`
`an array or arrays of programmable logic blocks (e.g., gates), where the
`
`connections between the logic blocks can be set up after manufacturing and
`
`therefore are considered to be “field-programmable.” In other words, once
`
`manufacturing is complete, the FPGA integrated circuit device includes logic and a
`
`network interconnecting the logic, where the user can configure the logic and
`
`interconnection network such that the FPGA performs a desired processing
`
`function. The interconnection network on the FPGA is used to provide the
`
`configurable connections between the programmable logic blocks. (Id. at 1:22-25.)
`
`22.
`
`In FPGAs such as those discussed in Wong, the interconnection
`
`network that connects the logic blocks includes links between programmable
`
`
`
`
`
`9
`
`
`
`Page 13 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`switches, where the links provide connections between the switches and also
`
`provide connections from the switches to the logic blocks in the FPGA. As such,
`
`the links are the inputs to, and outputs from, the switches. Within each switch, the
`
`inputs to the switch are programmably routed to particular outputs of the switch.
`
`(Id. at 1:61-2:6.) For example, figure 3D of Wong below illustrates an
`
`interconnection network that includes a plurality of switches 20 (shown as square
`
`boxes) that can be used to route any of the inputs to the network on the left to any
`
`of the outputs of the network on the right. (Id. at 4:18-26, FIG. 3D.) The arrows
`
`between the switches correspond to the “links” in the network. According to
`
`Wong, the particular network illustrated in figure 3D is an 8x8 Benes network that
`
`has eight inputs and eight outputs. (Id. at 2:36-37.)
`
`(Id. at FIG. 3D.)
`
`
`
`
`
`10
`
`
`
`
`
`Page 14 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`23. Each of the switches 20 shown in the network of figure 3D above is a
`
`2x2 switch that has two inputs and two outputs. (Id. at 2:31-37, 5:4-6.) As shown
`
`in figures 2A and 2B of Wong below, each switch can be set up in either a “pass”
`
`configuration where the inputs are passed straight through to the outputs or set up
`
`in a “cross” configuration where the upper input is routed to the lower output and
`
`vice-versa. (Id. at 2:27-29, 5:6-13.)
`
`
`
`(Id. at FIGs. 2A, 2B.)
`
`24. A controlling configuration bit is used to determine how the inputs to
`
`the switch are routed to the outputs of the switch (e.g., whether the switch is in a
`
`“pass” or “cross” configuration). (Id. at 3:48-50.) For example, figure 2C of
`
`Wong, replicated below, shows how multiplexers are used to implement a 2x2
`
`switch with the functionality of the switches shown in figures 2A and 2B. The
`
`multiplexers are controlled by a configuration bit or control bit that is used to
`
`determine which outputs are connected to which inputs of the switch.
`
`
`
`
`
`11
`
`
`
`Page 15 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`
`
`(Ex. 1008 at FIG. 2C (annotated).)
`
`25. By controlling the individual switches in the network, the routing of
`
`the inputs to the network to selected outputs can be controlled. By placing some of
`
`the switches in the “pass” configuration and others in the “cross” configuration, the
`
`network of switches can be used to route any of the eight inputs to any of the eight
`
`outputs. (Id. at 5:65-67.) For example, as shown in figure 3E of Wong below, a
`
`particular configuration of the switches reverses the ordering of input signals at the
`
`output terminals of the network. (Id. at 2:38-40, 5:67-6:5.) For example, by
`
`setting each of the switches to be either “pass” or “cross” as shown below in figure
`
`
`
`
`
`12
`
`
`
`Page 16 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`3E, the top-most input on the left (“000”) is routed such that it comes out at the
`
`bottom-most output on the right, whereas the bottom-most input on the left (“111”)
`
`is routed to the top-most output on the right. In traversing the network, each of the
`
`inputs to the network passes through five switches in the network.
`
`
`
`(Id. at FIG. 3E.)
`
`26. As demonstrated by Wong, it was well known long before the time of
`
`the alleged invention in the ’553 patent to use networks, such as, for example, the
`
`one depicted above in figure 3E of Wong, in FPGA devices. Moreover, it was also
`
`well known to modify such networks in order to make them more efficient as the
`
`interconnection network for an FPGA. For example, because the logic cells used
`
`in the FPGA include both inputs and outputs, the network can be folded in half in
`
`
`
`
`
`13
`
`
`
`Page 17 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`order to put both the inputs to the network and the outputs from the network
`
`adjacent to each other for easy connection to the inputs and outputs of the logic
`
`cells. (Id. at 6:52-61.) Such folding is illustrated by figure 4A of Wong, where the
`
`folding is done along the dotted line 31. (Id. at 6:65-67.)
`
`
`
`(Id. at FIG. 4A.)
`
`27. The resulting folded network is shown in figures 4B and 4C of Wong
`
`below, where figure 4C has rearranged the connections between the switches in the
`
`network so that the shorter connections are closer to the logic cells, which are
`
`placed on the left hand side of the network. (Id. at 7:6-21.) As can be seen in
`
`figures 4B and 4C, folding the network puts switches 1.1 and 5.1 together and
`
`switches 2.1 and 4.1 together.
`
`
`
`
`
`14
`
`
`
`Page 18 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`
`
`(Id. at FIGs. 4B, 4C.)
`
`28. A physical layout of the network shown in figure 4C with the
`
`accompanying logic cells for an FPGA is shown below in figure 13A of Wong.
`
`The physical layout shown in Figure 13A includes the network of switches 82 and
`
`associated logic cells 81. (Id. at 13:12-26.)
`
`
`
`
`
`15
`
`
`
`Page 19 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`
`
`(Id. at FIG. 13A.)
`
`29. A person of ordinary skill in the art would have understood that the
`
`physical layout corresponds to how the circuitry is physically arranged on the
`
`integrated circuit device. In other words, in the integrated circuit FPGA that
`
`includes the network shown in figure 13A above, the logic cells 81 would be
`
`arranged vertically in a column, and the switches 82 would be arrayed in rows and
`
`
`
`
`
`16
`
`
`
`Page 20 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`columns with appropriate connections corresponding to the illustrated links
`
`provided on the integrated circuit. The arrows on the right-hand side of figure 13A
`
`correspond to the top level connections between the network and primary
`
`input/output (I/O) of the FPGA. (Id. at 13:42-43.) A person of ordinary skill in the
`
`art would have understood that the signals provided to the FPGA, which the logic
`
`cells 81 are used to process, are provided on the primary inputs of the FPGA,
`
`whereas the results generated by that processing are provided on the primary
`
`outputs of the FPGA.
`
`30. As depicted in figure 13A of Wong, logic cells 81 are included in the
`
`FPGA along with switch cells 82. (Id. at 13:22-23 (“There are two logic cells 81
`
`per switch cell 82….”).) The logic cells in an FPGA are used to process the inputs
`
`provided to the FPGA. The processing functions performed by the logic cells are
`
`often configurable by the user. As such, not only the connections between the
`
`logic cells are configurable, but the actual processing functions performed by the
`
`logic cells are also configurable by the user after manufacturing is complete.
`
`VI. OVERVIEW OF THE ’553 PATENT
`31. The ’553 patent is entitled “Optimization of Multi-Stage Hierarchical
`
`Networks for Practical Routing Applications.” (Ex. 1001 at Title.) The ’553
`
`patent acknowledges that multi-stage hierarchical networks were known and used
`
`
`
`
`
`17
`
`
`
`Page 21 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`in many applications at the time of the alleged invention. (Ex. 1001 at 2:66-3:1
`
`(“Multi-stage interconnection networks such as Benes networks and butterfly fat
`
`tree networks are widely useful in telecommunications, parallel and distributed
`
`computing.”).) Practical applications where the multi-stage hierarchical networks
`
`can be used include “FPGA routing of hardware designs.” (Id. at 4:47-48.)
`
`32. The ’553 patent recognizes that VLSI (very large scale integration)
`
`layouts for integrated circuits with such networks were known, but states that such
`
`layouts are “inefficient and complicated.” (Id. at 3:2-4.) For example, the ’553
`
`patent acknowledges that Wong (Ex. 1008) discloses a layout of a Benes network.2
`
`(Ex. 1001 at 3:30-36). However the ’553 patent contends that prior art network
`
`layouts “require large area to implement the switches on the chip, large number of
`
`wires, longer wires, with increased power consumption, increased latency of the
`
`signal which effect the maximum clock speed of operation.” (Id. at 3:43-48.)
`
`33. Evidently in an attempt to address these issues, the ’553 patent alleges
`
`to disclose “[s]ignificantly optimized multi-stage networks, useful in wide target
`
`applications” where the “optimized multi-stage networks in each block employ
`
`
`2 Benes networks were originally developed by Vaclav E. Benes at Bell Labs in the
`
`mid-1960s. (See, e.g., Ex.1040 at Cover.)
`
`
`
`
`
`18
`
`
`
`Page 22 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`several rings of stages of switches with inlet and outlet links.” (Ex. 1001 at 3:58-
`
`67 (emphasis added).) Notably, each of figures 1-15 of the ’553 patent illustrates,
`
`describes, or relates to the use of “rings” in a “multi-stage hierarchical network.”
`
`(Id. at FIGs. 1-15, 4:42-6:22, (explicitly referring to a “multi-stage hierarchical
`
`network” where the inclusion of a “ring” is provided in the description of each of
`
`figures 1-15 or in the drawing itself); see also id. at 8:56-9:3 (description of rings
`
`110 and 120 in figures 1A-1B), 33:26-48 (discussion of rings with respect to
`
`figures 7-8).) However, as discussed below in this section, “rings,” which the ’553
`
`patent describes as an important aspect of the alleged optimizations to the prior art
`
`multi-stage hierarchical networks, are not recited in the claims of the ’553 patent.
`
`34.
`
`I understand that the ’553 patent issued June 19, 2018 from U.S.
`
`Patent Application No. 15/140,470 (“the ’470 application”) (Ex. 1004), which was
`
`filed April 28, 2016. (Ex. 1001 at Cover; Ex. 1004 at 203-204.) While the ’553
`
`patent states that it is a continuation application that claims priority to U.S. Patent
`
`Application 14/199,168 (“the ’168 application”) (Ex. 1001 at 1:8-13), I understand
`
`that the ’553 patent issued without properly claiming priority to any earlier filed
`
`patents or applications. (Ex. 1001 at cover page (showing no related patent data or
`
`priority information); Ex. 1004 at 149.)
`
`
`
`
`
`19
`
`
`
`Page 23 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`35. However, I understand that a certificate of correction was issued on
`
`February 19, 2019 (Ex. 1004 at 1), where the certificate states that the ’553 patent
`
`claims priority to the ’168 application (Ex. 1005), which in turn claims priority to
`
`PCT/US12/53814 (“the ’814 PCT application”) (Ex. 1006) filed September 6,
`
`2012 and U.S. provisional application 61/531,615 (“the ’615 provisional
`
`application”) (Ex. 1007), filed September 7, 2011. The ’168 Application issued as
`
`U.S. Patent 9,374,322 (“the ’322 patent”) (Ex. 1035) on June 21, 2016. (Ex. 1035,
`
`Cover.) I also have been informed that U.S. Patent Application 15/984,408 is
`
`currently pending and claims priority to the ’470 application. I have created the
`
`demonstrative below to help visualize the purported priority chain for the ’553
`
`patent.
`
`
`
`
`
`20
`
`
`
`Page 24 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`
`
`
`36. As noted above, the ’470 application purports to be a continuation
`
`application with respect to the ’168 application (Ex. 1004 at 7-8, Ex. 1001 at 1:8-
`
`14), and the ’168 application purports to be a continuation of the ’814 PCT
`
`application, which in turn describes itself as a “Continuation in Part Application
`
`to” the ’615 provisional. (Ex. 1005 at 10; Ex. 1006 at 1:6-10.) Below, I
`
`sometimes refer to the collection of the ’168 application, the ’814 PCT application,
`
`
`
`
`
`21
`
`
`
`Page 25 of 142
`
`

`

`
`
`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 10,003,553
`
`
`and the ’615 provisional application as the “alleged priority applications of the
`
`’553 patent.”
`
`37. The ’553 patent incorporates the ’168 Application, the ’814 PCT
`
`application, and the ’615 provisional application by reference. (Ex. 1001 at 1:8-
`
`25.) Numerous additional patents and applications are also incorporated by
`
`reference in the ’553 patent. (See, e.g., Ex. 1001 at 1:26-2:62.) I have reviewed
`
`the alleged priority applications of the ’553 patent as well as the additional patents
`
`and applications that are incorporated by reference in columns 1 and 2 of the ’553
`
`patent, which I understand are being submitted as Exhibits 1011-1034. After
`
`reviewing the claims that issued in the ’553 patent in view of the claims included
`
`in the alleged priority applications of the ’553 patent, it is evident that the claims of
`
`the ’553 patent are directed to subject matter that is very different than the subject
`
`matter to which the