`
`Electronic Acknowledgement Receipt
`
`a|_
`
`_epteasonnumpes
`
`
`
`International Application Number: PCT/US08/64605
`
`Confirmation Number:
`
`5423
`
`Title of Invention:
`
`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED
`NETWORKS
`
`Customer Number:
`
`38139
`
`CorrespondenceAddress:
`
`Venkat Konda
`
`Konda Technologies Inc.
`
`6278 Grand Oak Way
`
`San Jose
`
`US
`
`408-472-3273
`
`venkat@kondatech.com
`
`eeie
`
`
`
`ReceiptDate: 22-MAY-2008
`
`Filing Date:
`
`Time Stamp:
`
`23:51:33
`
`Application Type:
`
`International Application for filing in the US receiving office
`
`Paymentinformation:
`
`Page 1 of 127
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`FLEX LOGIX EXHIBIT 1025
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`Page 1 of 127
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`FLEX LOGIX EXHIBIT 1025
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`S-0045PCT-RO-101.pdf
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`PCT-Transmittal Letter
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`New Applications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary componentsfora filing date (see
`37 CFR 1.53(b)-(d) and MPEP 506), a Filing Receipt (37 CFR 1.54) will be issued in due course and the date
`shownonthis AcknowledgementReceiptwill establish the filing date of the application.
`
`National Stage of an International Application under 35 U.S.C. 371
`If a timely submission to enter the national stage of an international application is compliant with the conditions
`of 35 U.S.C. 371 and other applicable requirements a Form PCT/DO/EO/903 indicating acceptanceof the
`application as a national stage submission under 35 U.S.C. 371 will be issued in addition to the Filing Receipt,
`in due course.
`
`This AcknowledgementReceipt evidences receipt on the noted date by the USPTOofthe indicated documents,
`characterized by the applicant, and including page counts, where applicable.
`It serves as evidenceof receipt
`similar to a Post Card, as described in MPEP 503.
`
`Receipt will establish the international filing date of the application.
`
`New International Application Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary
`componentsfor an internationalfiling date (see PCT Article 11 and MPEP 1810), a Notification of the
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`course, subject to prescriptions concerning national security, and the date shown on this Acknowledgement
`
`Page 3 of 127
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`Page 3 of 127
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`

`

`$-0045 PCT
`
`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS
`
`Venkat Konda
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is Continuation In Part PCT Application to and incorporates by
`
`reference in its entirety the U.S. Provisional Patent Application Serial No. 60/940, 394
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED NETWORKS"
`
`by Venkat Kondaassigned to the same assignee as the current application, filed May 25,
`
`10
`
`2007.
`
`This application is related to and incorporates by reference in its entirety the PCT
`
`Application Serial No. PCT /US08/56064 entitled "FULLY CONNECTED
`
`GENERALIZED MULTI-STAGE NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed March 6, 2008, the U.S. Provisional Patent
`
`15
`
`Application Serial No. 60/905,526 entitled "LARGE SCALE CROSSPOINT
`
`REDUCTION WITH NONBLOCKING UNICAST & MULTICAST IN
`
`ARBITRARILY LARGE MULTI-STAGE NETWORKS"by Venkat Kondaassigned to
`
`the same assignee as the current application, filed March 6, 2007, and the U.S.
`
`Provisional Patent Application Serial No. 60/940, 383 entitled "FULLY CONNECTED
`
`20
`
`GENERALIZED MULTI-STAGE NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed May 25, 2007.
`
`This application is related to and incorporates by reference in its entirety the PCT
`
`Application Docket No. S-0038PCT entitled "FULLY CONNECTED GENERALIZED
`
`BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassigned to the same
`
`25
`
`assignee as the current application, filed concurrently, the U.S. Provisional Patent
`
`Application Serial No. 60/940, 387 entitled "FULLY CONNECTED GENERALIZED
`
`BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassigned to the same
`
`-1-
`
`Page 4 of 127
`
`Page 4 of 127
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`

`

`$-0045 PCT
`
`assignee as the current application, filed May 25, 2007, and the U.S. Provisional Patent
`
`Application Serial No. 60/940, 390 entitled "FULLY CONNECTED GENERALIZED
`
`MULTI-LINK BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassigned to
`
`the same assignee as the current application, filed May 25, 2007
`
`This application is related to and incorporates by referencein its entirety the PCT
`
`Application Docket No. S-0039PCTentitled "FULLY CONNECTED GENERALIZED
`
`MULTI-LINK MULTI-STAGE NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed concurrently, the U.S. Provisional Patent
`
`Application Serial No. 60/940, 389 entitled "FULLY CONNECTED GENERALIZED
`
`10
`
`REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS"
`
`by Venkat Kondaassigned to the same assigneeas the current application, filed May 25,
`
`2007, the U.S. Provisional Patent Application Serial No. 60/940, 391 entitled "FULLY
`
`CONNECTED GENERALIZED FOLDED MULTI-STAGE NETWORKS"by Venkat
`
`Konda assigned to the same assignee as the current application, filed May 25, 2007 and
`
`15
`
`the U.S. Provisional Patent Application Serial No. 60/940, 392 entitled "FULLY
`
`CONNECTED GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTI-
`
`STAGE NETWORKS"by Venkat Konda assigned to the same assignee as the current
`
`application, filed May 25, 2007.
`
`This application is related to and incorporates by referencein its entirety the U.S.
`
`20
`
`Provisional Patent Application Serial No. 60/984, 724 entitled "VLSI LAYOUTS OF
`
`FULLY CONNECTED NETWORKS WITH LOCALITY EXPLOITATION"by Venkat
`
`Konda assigned to the same assignee as the current application, filed November 2, 2007.
`
`This application is related to and incorporates by referencein its entirety the U.S.
`
`Provisional Patent Application Serial No. 61/018, 494 entitled "VLSI LAYOUTS OF
`
`25
`
`FULLY CONNECTED GENERALIZED AND PYRAMID NETWORKS"by Venkat
`
`Konda assigned to the same assignee as the current application, filed January 1, 2008.
`
`Page 5 of 127
`
`Page 5 of 127
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`

`

`$-0045 PCT
`
`BACKGROUNDOF INVENTION
`
`Multi-stage interconnection networks such as Benes networksandbutterfly fat
`
`tree networks are widely useful in telecommunications, parallel and distributed
`
`computing. However VLSIlayouts, knownin the prior art, of these interconnection
`
`networks in an integrated circuit are inefficient and complicated.
`
`Other multi-stage interconnection networks including butterfly fat tree networks,
`
`Banyan networks, Batcher-Banyan networks, Baseline networks, Delta networks, Omega
`
`networks and Flip networks have been widely studied particularly for self routing packet
`
`switching applications. Also Benes Networks with radix of two have been widely studied
`
`10
`
`and it is known that Benes Networksof radix two are shownto be built with back to back
`
`baseline networks which are rearrangeably nonblocking for unicast connections.
`
`The most commonly used VLSI layout in an integrated circuit is based on a two-
`
`dimensional grid model comprising only horizontal and vertical tracks. An intuitive
`
`interconnection network that utilizes two-dimensional grid model is 2D Mesh Network
`
`15
`
`and its variations such as segmented mesh networks. Hence routing networks used in
`
`VLSIlayouts are typically 2D mesh networksandits variations. However Mesh
`
`Networks require large scale cross points typically with a growth rate of O(N*) where N
`
`is the number of computing elements, ports, or logic elements depending on the
`
`application.
`
`20
`
`Multi-stage interconnection with a growth rate of O(N xlog N) requires
`
`significantly small numberof cross points, U.S. Patent 6,185,220 entitled “Grid Layouts
`
`of Switching and Sorting Networks” granted to Muthukrishnanet al. describes a VLSI
`
`layout using existing VLSI grid model for Benes and Butterfly networks. U.S. Patent
`
`6,940,308 entitled “Interconnection Network for a Field Programmable Gate Array”
`
`25
`
`granted to Wong describes a VLSI layout where switches belonging to lower stage of
`
`Benes Networkare layed out close to the logic cells and switches belonging to higher
`
`stages are layed out towards the center of the layout.
`
`Page 6 of 127
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`

`

`$-0045 PCT
`
`Dueto the inefficient and in some cases impractical VLSI layout of Benes and
`
`butterfly fat tree networks on a semiconductor chip, today mesh networks and segmented
`
`mesh networksare widely used in the practical applications such as field programmable
`
`gate arrays (FPGAs), programmable logic devices (PLDs), and parallel computing
`
`interconnects. The prior art VLSI layouts of Benes and butterfly fat tree networks and
`
`VLSI layouts of mesh networks and segmented mesh networksrequire large area to
`
`implement the switches on the chip, large numberof wires, longer wires, with increased
`
`power consumption, increased latency of the signals which effect the maximum clock
`
`speed of operation. Some networks may not even be implemented practically on a chip
`
`10
`
`due to the lack of efficient layouts.
`
`SUMMARYOF INVENTION
`
`Whenlarge scale sub-integrated circuit blocks with inlet and outlet links are layed
`
`out in an integrated circuit device in a two-dimensional grid arrangement, (for example in
`
`15
`
`an FPGA where the sub-integrated circuit blocks are Lookup Tables) the most intuitive
`
`routing network is a network that uses horizontal and vertical links only (the most often
`
`used such a network is one of the variations of a 2D Mesh network). A direct embedding
`
`of a generalized multi-stage network on to a 2D Mesh network is neither simple nor
`
`efficient.
`
`20
`
`Tn accordance with the invention, VLSI layouts of generalized multi-stage
`
`networks for broadcast, unicast and multicast connections are presented using only
`
`horizontal and vertical links. The VLSI layouts employ shuffle exchange links where
`
`outlet links of cross links from switches in a stage in one sub-integrated circuit block are
`
`connected to inlet links of switches in the succeeding stage in another sub-integrated
`
`25
`
`circuit block so that said cross links are either vertical links or horizontal and vice versa.
`
`In one embodimentthe sub-integrated circuit blocks are arranged in a hypercube
`
`arrangementin a two-dimensional plane. The VLSI layouts exploit the benefits of
`
`significantly lower cross points, lower signal latency, lower powerand full connectivity
`
`with significantly fast compilation.
`
`Page 7 of 127
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`

`

`$-0045 PCT
`
`The VLSI layouts presented are applicable to generalized multi-stage networks
`
`V(N,,N,,d,s), generalized folded multi-stage networks V,.,(N,,N,,d,s), generalized
`
`butterfly fat tree networks V,,(N,,N,,d,5), generalized multi-link multi-stage networks
`
`Vtine (N,N>.,d,5), generalized folded multi-link multi-stage networks
`
`Vfold-miinr (N,,N,.d,5), generalized multi-link butterfly fat tree networks
`
`Rr
`V, ink-og (N,N>,d,5), and generalized hypercube networks V,,
`
`cube
`
`(N,.N,,d,5) fors=
`
`1,2,3 or any numberin general. The embodiments of VLSI layouts are useful in wide
`
`target applications such as FPGAs, CPLDs, pSoCs, ASIC placementandroute tools,
`
`networking applications, parallel & distributed computing, and reconfigurable computing.
`
`10
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1A is a diagram 100A of an exemplary symmetrical multi-link multi-stage
`
`network Vii4ming (N,d,5) having inverse Benes connection topology of nine stages with
`
`N = 32, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`15
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG. 1B is a diagram 100B of the equivalent symmetrical folded multi-link multi-
`
`stage network Vigmine (N»d,5) of the network 100A shownin FIG, 1A, having inverse
`
`Benes connection topology of five stages with N = 32, d= 2 and s=2,strictly nonblocking
`
`20
`
`network for unicast connections and rearrangeably nonblocking networkforarbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`FIG. 1C is a diagram 100C layout of the network V,0.td_mtine Nd, 5) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
`
`Page 8 of 127
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`

`

`$-0045 PCT
`
`FIG. 1D is a diagram 100D layout of the network V,jold-miine(Nd,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 64] and
`
`ML(8,i) for i = [1,64].
`
`01
`FIG, 1E is a diagram 100E layoutof the network V,
`
`ta_mtine (NV ,d,5) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 64] and
`
`ML(7,1) for 1 = [1,64].
`
`FIG. 1F is a diagram 100F layoutof the network Vpining (Nd, 5) shown in FIG.
`
`1B, in one embodiment, ilustrating the connection links ML(@,i) for 1 = [1, 64] and
`
`ML(6,1) for i = [1,64].
`
`10
`
`FIG. 1G is a diagram 100G layout of the network V,old—mlink (N,d,s) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links ML(4,1) for i = [1, 64] and
`
`ML(5,i) for i = [1,64].
`
`FIG, 1H is a diagram 100H layout of a network V,fold—mlink (N,d,s) where N = 128,
`
`d= 2, and s = 2, in one embodiment, illustrating the connection links belonging with in
`
`15
`
`each block only.
`
`FIG. 11 is a diagram 100I detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 100C is implementing V(N,d,s) or V,,,,(N,d,5).
`
`FIG. 1J is a diagram 100J detailed connections of BLOCK 1_2 in the network
`
`20
`
`layout 100C in one embodiment,illustrating the connection links going in and coming
`
`out when the layout 100C is implementing V(N,d,s) or Viota (N,d,s).
`
`FIG. 1K is a diagram 100K detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming
`
`out when the layout 100C is implementing V(N,d,s) or V,.,(N,d,s).
`
`Page 9 of 127
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`Page 9 of 127
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`

`

`$-0045 PCT
`
`FIG, 1K1 is a diagram 100M1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out when the layout 100C is implementing V(N,d,s) or V,,,,(N,d,s) fors = 1.
`
`FIG. 1L is a diagram 100L detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming
`
`out whenthe layout 100C is implementing V(N,d,s) or V;,,(N,d,5).
`
`FIG, 1L1 is a diagram 100L1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 100C is implementing V(N,d,s) or V,,,(N.d,s) fors=1.
`
`networkV514-mins(N,d,5) having inverse Benes connection topology of one stage with N
`
`FIG, 2A1 is a diagram 200A1 of an exemplary symmetrical multi-link multi-stage
`
`= 2, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2A2 is a diagram 200A2 of the equivalent
`
`15
`
`symmetrical folded multi-link multi-stage network Voinin (N,d,5) of the network
`
`200A1 shown in FIG. 2A1, having inverse Benes connection topology of one stage with
`
`N = 2, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2A3 is a diagram 200A3 layout of the network
`
`20
`
`Vfola—miink (Nd, 8) shown in FIG, 2A2, in one embodiment, illustrating all the connection
`
`links.
`
`FIG. 2B1 is a diagram 200B1 of an exemplary symmetrical multi-link multi-stage
`
`network Viii4-ming (N,d,5) having inverse Benes connection topology of one stage with N
`
`= 4, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and
`
`25
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2B2 is a diagram 200B2 of the equivalent
`
`symmetrical folded multi-link multi-stage network Vj.)4 (N.d,s) of the network
`
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`

`

`$-0045 PCT
`
`200B1 shown in FIG, 2B1, having inverse Benes connection topology of one stage with
`
`N = 4, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2B3 is a diagram 200B3 layout of the network
`
`Vinta_mink(N,d,s) shown in FIG, 2B2, in one embodiment, illustrating the connection
`
`links belonging with in each block only. FIG. 2B4 is a diagram 200B4 layout of the
`
`network Voimine (N,d,5)
`
`shown in FIG. 2B2,
`
`in one embodiment,
`
`illustrating the
`
`connection links ML(1,i) for i= [1, 8] and ML(2,1) for 1 = [1,8].
`
`FIG, 2C11 is a diagram 200C11 of an exemplary symmetrical multi-link multi-
`
`stage network V,oid_mins (N.d,5) having inverse Benes connection topology of one stage
`
`with N = 8, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention. FIG. 2C12 is a diagram 200C12 of the equivalent
`
`symmetrical folded multi-link multi-stage network V,otd_mtine©, 4,5) Of the network
`
`15
`
`200C11 shown in FIG. 2C11, having inverse Benes connection topology of one stage
`
`with N = 8, d = 2 and s=2,strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG, 2C21 is a diagram 200C21 layout of the network V,old_mling AY» 4,5) shown in
`
`FIG, 2C12, in one embodiment, illustrating the connection links belonging with in each
`
`block only. FIG. 2C22 is a diagram 200C22 layout of the network Vyigputing (N>d,5)
`
`shown in FIG. 2C12, in one embodiment,illustrating the connection links ML(1,i) for i =
`
`[1, 16] and ML(4,i) for i = [1,16]. FIG. 2C23 is a diagram 200C23 layout of the network
`
`Vin
`
`tinting (N>2,5) shown in FIG. 2C12, in one embodiment, illustrating the connection
`
`25
`
`links ML(2,i) for i = [1, 16] and ML(3,i) for i = [1,16].
`
`FIG. 2D1 is a diagram 200D1 of an exemplary symmetrical multi-link multi-stage
`
`network Vimink (N,d,5) having inverse Benes connection topology of one stage with N
`
`= 16, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`-8-
`
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`Page 11 of 127
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`

`

`$-0045 PCT
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG, 2D2 is a diagram 200D2 of the equivalent symmetrical folded multi-link
`
`multi-stage network V,»id—min V,d,5) Of the network 200D1 shown in FIG. 2D1, having
`
`inverse Benes connection topology of one stage with N = 16, d = 2 and s=2, strictly
`
`nonblocking network for unicast connections and rearrangeably nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG, 2D3 is a diagram 200D3 layout of the network Vg.4juin (N.d,5) shown in
`
`FIG, 2D2, in one embodiment, illustrating the connection links belonging with in each
`
`10
`
`block only.
`
`FIG, 2D4 is a diagram 200D4 layout of the network Vygiiutin (N.d,5) shown in
`
`FIG. 2D2, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 32] and
`
`ML(6,1) for i = [1,32].
`
`FIG, 2D5 is a diagram 200D5 layout of the network Vagigjuin (N.d,5) shown in
`
`15
`
`FIG, 2D2, in one embodiment,illustrating the connection links ML(2,1) for i = [1, 32] and
`
`ML(5,1) for i = [1,32].
`
`v0.
`FIG. 2D6 is a diagram 200D6 layout of the network V,,
`
`tinting (Nd, 8) shown in
`
`FIG, 2D2, in one embodiment, illustrating the connection links ML(3,1) for i = [1, 32] and
`
`ML(4,1) for i = [1,32].
`
`20
`
`FIG, 3A is a diagram 300A of an exemplary symmetrical multi-link multi-stage
`
`network V,__,.(NV,d,s) having inverse Benes connection topology of nine stages with N =
`
`32, d=2and s=2, strictly nonblocking network for unicast connections and rearrangeably
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`invention.
`
`FIG. 3B is a diagram 300B of the equivalent symmetrical folded multi-link multi-
`
`cube
`stage network V,_,.(N.d,s) of the network 300A shown in FIG. 3A, having inverse
`
`-9-
`
`Page 12 of 127
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`Page 12 of 127
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`

`

`$-0045 PCT
`
`Benes connection topologyof five stages with N = 32, d= 2 and s=2, strictly nonblocking
`
`network for unicast connections and rearrangeably nonblocking network forarbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`cube
`FIG. 3C is a diagram 300C layout of the network V,_,.(N.d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
`
`cube
`FIG. 3D is a diagram 100D layout of the network V,,,.(N.d.s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(1,1) for i = [1, 64] and
`
`ML(8,1) for i = [1,64].
`
`10
`
`cube
`FIG, 3E is a diagram 300E layout of the network V,_,.(N,d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(2,i) for 1 = [1, 64] and
`
`ML(7,1) for 1 = [1,64].
`
`cube
`FIG. 3F is a diagram 300F layout of the network V,_,,(V,d,s) shown in FIG, 3B,
`
`in one embodiment, illustrating the connection links ML(3,1) for 1 = [1, 64] and ML(6,i)
`
`15
`
`for i= [1,64].
`
`cube
`FIG. 3G is a diagram 300G layout of the network V,,_,,,(N,d,s) shown in FIG.
`
`3B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`ML(5,i) for i = [1,64].
`
`cube
`FIG. 3H is a diagram 300Hlayoutof a network V,_,,(NV,d,5) where N = 128, d=
`
`20
`
`2, and s = 2, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
`
`FIG. 4A is a diagram 400A layout of the network Vigigjuine(N.d,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
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`-10-
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`$-0045 PCT
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`FIG.4B is a diagram 400B layoutof the network Viiining (N.d,5) shownin FIG.
`
`1B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 64] and
`
`ML(8,i) for i = [1,64].
`
`‘0.
`FIG. 4C is a diagram 400C layoutof the network V,
`
`amine (NV d,8) shown in FIG.
`
`4C, in one embodiment, illustrating the connection links ML(2,1) for i = [1, 64] and
`
`ML(7,i) for i = [1,64].
`
`FIG. 4D is a diagram 400D layout of the network Vijigimine (N.d,s) shown in
`
`FIG, 4D,in one embodiment, illustrating the connection links ML(3,1) for 1 = [1, 64] and
`
`ML(6,1) for i = [1,64].
`
`10
`
`FIG.4E is a diagram 400E layoutof the network Vj.4-mine (N.d,5) Shownin FIG,
`
`4E, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`ML(5,i) for i = [1,64].
`
`FIG. 4C1 is a diagram 400C1 layout of the network V,oid-mtine (N,d,5) shown in
`
`FIG. 1B, in one embodiment, illustrating the connection links belonging with in each
`
`15
`
`block only.
`
`FIG. 5A1 is a diagram 500A1 of an exemplary prior art implementation of a two
`
`by two switch; FIG. 5A2 is a diagram 500A2 for programmable integrated circuit prior
`
`art implementation of the diagram 500A1 of FIG. 5A1; FIG. 5A3 is a diagram 500A3 for
`
`one-time programmable integrated circuit prior art implementation of the diagram 500A1
`
`20
`
`of FIG. 5A1; FIG. 5A4 is a diagram 500A4 for integrated circuit placement and route
`
`implementation of the diagram 500A1 of FIG. 5A1.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`The present invention is concerned with the VLSI layouts of arbitrarily large
`
`switching networks for broadcast, unicast and multicast connections. Particularly
`
`switching networks considered in the current invention include: generalized multi-stage
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`-11-
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`$-0045 PCT
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`networks V(N,,N,,d,s5), generalized folded multi-stage networks Vrota (N,,N,.d,5),
`
`generalized butterfly fat tree networks Vig (N,,N,,d,5), generalized multi-link multi-
`
`stage networks V,_,,, (V,,N>,d,8) . generalized folded multi-link multi-stage networks
`
`VV.fold-miinr (N,,N,d,8), generalized multi-link butterfly fat tree networks
`
`7H
`V tinkbfé (N,,N,,d,s), and generalized hypercube networks V,
`
`acube
`
`(N,,.N,.d,s5) fors=
`
`1,2,3 or any numberin general.
`
`Efficient VLSI layout of networks on a semiconductor chip are very important
`
`and greatly influence many important design parameters such as the area taken up by the
`
`network on the chip, total numberof wires, length of the wires, latency of the signals,
`
`10
`
`capacitance and hence the maximum clock speed of operation. Some networks may not
`
`even be implemented practically on a chip dueto the lack of efficient layouts, The
`
`different varieties of multi-stage networks described above have not been implemented
`
`previously on the semiconductorchips efficiently. For example in Field Programmable
`
`Gate Array (FPGA) designs, multi-stage networks described in the current invention have
`
`15
`
`not been successfully implemented primarily due to the lack of efficient VLSI layouts.
`
`Current commercial FPGA products such as Xilinx Vertex, Altera’s Stratix implement
`
`island-style architecture using mesh and segmented meshrouting interconnects using
`
`either full crossbars or sparse crossbars. These routing interconnects consumelarge
`
`silicon area for crosspoints, long wires, large signal propagation delay and hence
`
`20
`
`consumelot of power.
`
`The current invention discloses the VLSI layouts of numerous types of multi-
`
`stage networks whichare very efficient. Moreover they can be embedded on to mesh and
`
`segmented meshrouting interconnects of current commercial FPGA products. The VLSI
`
`layouts disclosed in the current invention are applicable to including the numerous
`
`25
`
`generalized multi-stage networks disclosed in the following patent applications, filed
`
`concurrently:
`
`1) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized multi-stage networks V(N,,N.,,d,s) with numerous connection
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`-12-
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`$-0045 PCT
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`topologies and the scheduling methods are described in detail in the PCT Application
`
`Serial No. PCT /US08/56064 that is incorporated by reference above.
`
`2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized butterfly fat tree networks V,,(N,,N,,d,s) with numerous
`
`connection topologies and the scheduling methods are described in detail in U.S.
`
`Provisional Patent Application Serial No. 60/940, 387 that is incorporated by reference
`
`above.
`
`3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and
`
`strictly nonblocking for unicast for generalized multi-link multi-stage networks
`
`10
`
`Ving (N1»N>,d,5) and generalized folded multi-link multi-stage networks
`
`Vvfold—mink (N,,N,,d,8) with numerous connection topologies and the scheduling methods
`
`are described in detail in U.S. Provisional Patent Application Serial No. 60/940, 389 that
`
`is incorporated by reference above.
`
`4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`15
`
`unicast for generalized multi-link butterfly fat tree networks V,jin.44 (N,.N..d,5) with
`
`numerous connection topologies and the scheduling methods are described in detail in
`
`U.S. Provisional Patent Application Serial No. 60/940, 390 that is incorporated by
`
`reference above.
`
`5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`20
`
`unicast for generalized folded multi-stage networks V,,,,(NV,,N,,d,5) with numerous
`
`connection topologies and the scheduling methods are described in detail in U.S.
`
`Provisional Patent Application Serial No. 60/940, 391 that is incorporated by reference
`
`above.
`
`6) Strictly nonblocking for arbitrary fan-out multicast for generalized multi-link
`
`25
`
`multi-stage networks V,,,,,.(N,,N,,d,s) and generalized folded multi-link multi-stage
`
`networks Viigmting (Ni, N,,d, 5) with numerous connection topologies and the scheduling
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`-13-
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`$-0045 PCT
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`methodsare described in detail in U.S. Provisional Patent Application Serial No. 60/940,
`
`392 that is incorporated by reference above.
`
`7) VLSI layouts of numerous types of multi-stage networks with locality
`
`exploitation are described in U.S. Provisional Patent Application Serial No. 60/984, 724
`
`that is incorporated by reference above.
`
`8) VLSI layouts of numeroustypes of multistage pyramid networksare described
`
`in U.S. Provisional Patent Application Serial No. 61/018, 494 that is incorporated by
`
`reference above.
`
`In addition the layouts of the current invention are also applicable to generalized
`
`10
`
`multi-stage pyramid networks V,(N,,N,,d,s) , generalized folded multi-stage pyramid
`
`networks V,.,,_,(N,,N,,d,5), generalized butterfly fat pyramid networks
`
`Vig (N,,N,,d,5), generalized multi-link multi-stage pyramid networks
`
`Vntin-p (N1,N,,d, 5), generalized folded multi-link multi-stage pyramid networks
`
`Vjott—miine_p (N1,N>,d,8), generalized multi-link butterfly fat pyramid networks
`
`15
`
`ciit
`V tink—bfp (N,,N,,d,s), and generalized hypercube networks V,
`
`cube
`
`(N,,N,,d,5) fors=
`
`1,2,3 or any numberin general.
`
`Symmetric RNB generalized multi-link multi-stage network V,,,,,(N,,N>,d,5):
`
`Referring to diagram 100A in FIG. 1A, in one embodiment, an exemplary
`
`20
`
`generalized multi-link multi-stage network V,,,,,,(N,,N,,d,s) where N; = No =32; d=
`
`2; and s = 2 with nine stages of one hundred and forty four switches for satisfying
`
`communication requests, such as setting up a telephone call or a data call, or a connection
`
`between configurable logic blocks, between an input stage 110 and outputstage 120 via
`
`middle stages 130, 140, 150, 160, 170, 180 and 190 is shown where input stage 110
`
`25
`
`consists of sixteen, two by four switches IS1-IS16 and output stage 120 consists of
`
`sixteen, four by two switches OS1-OS16. Andall the middle stages namely the middle
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`14
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`$-0045 PCT
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`stage 130 consists of sixteen, four by four switches MS(1,1) - MS(1,16), middle stage
`
`140 consists of sixteen, four by four switches MS(2,1) - MS(2,16), middle stage 150
`
`consists of sixteen, four by four switches MS(3,1) - MS(3,16), middle stage 160 consists
`
`of sixteen, four by four switches MS(4,1) - MS(4,16), middle stage 170 consists of
`
`sixteen, four by four switches MS(5,1) - MS(5,16), middle stage 180 consists of sixteen,
`
`four by four switches MS(6,1) - MS(6,16), and middle stage 190 consists of sixteen, four
`
`by four switches MS(7,1) - MS(7,16).
`
`Asdisclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is
`
`incorporated by reference above, such a network can be operated in rearrangeably non-
`
`10
`
`blocking mannerfor arbitrary fan-out multicast connections and also can be operated in
`
`strictly non-blocking mannerfor unicast connections.
`
`In one embodimentof this network each of the input switches IS1-IS4 and output
`
`switches O$1-OS4 are crossbar switches. The number of switches of input stage 110 and
`
`of output stage 120 can be denoted in general with the variable = , where N is the total
`
`15
`
`numberofinletlinks or outlet links. The number of middle switches in each middle stage
`
`is denoted by ; . The size ofeach input switch IS1-IS4 can be denoted in general with
`
`the notation d*2d and each output switch OS1-O54 can be denoted in general with the
`
`notation 2d *d. Likewise, the size of each switch in any of the middle stages can be
`
`denoted as 2d *2d . A switch as used herein can be either a crossbar switch, or a
`
`20
`
`network of switches each of which in turn maybe a crossbar switch or a network of
`
`switches. A symmetric multi-stage network can be represented with the notation
`
`Vwine (N»d,S), where N represents the total numberof inletlinks of all input switches
`
`(for example the links IL1-IL32), d represents the inlet links of each input switch or
`
`outlet links of each output switch, and s is the ratio of number of outgoing links from
`
`25
`
`each input switch to the inlet l