Electronic Patent Application Fee Transmittal
`
`En
`
`Filing Date:
`
`Title of Invention:
`
`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID
`NETWORKS WITH LOCALITY EXPLOITATION
`
`First Named Inventor/Applicant Name:
`
`Venkat Konda
`
`Attorney Docket Number:
`
`$-0048PCT
`
`International Application for filing in the US receiving office Filing Fees
`
`Basic Filing:
`
`240
`240
`1
`Transmittal fee
`
`
`PCT Search Fee- no prior US appl filed
`
`Intl Filing Fee (1st-30 Pgs.) PCT Easy
`
`Suppl. Intl Filing Fee (each page > 30)
`
`1701
`
`1703
`
`1061
`
`13
`
`136
`
`1061
`
`1768
`
`
`
`Miscellaneous-Filing:
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`Page 1 of 191
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`FLEX LOGIX EXHIBIT 1028
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`Page 1 of 191
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`FLEX LOGIX EXHIBIT 1028
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`

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`as
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`.
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`Sub-Total in
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`Post-Allowance-and-Post-Issuance:
`
`Extension-of-Time:
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`Miscellaneous:
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`Patent-Appeals-and-Interference:
`
`5149
`
`Total in USD ($)
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`Page 2 of 191
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`Electronic AcknowledgementReceipt
`
`
`
`International Application Number: PCT/US10/52984
`
`Confirmation Number:
`
`9436
`
`Title of Invention:
`
`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID
`NETWORKS WITH LOCALITY EXPLOITATION
`
`
`
`First Named Inventor/Applicant Name:
`
`Venkat Konda
`
`Customer Number:
`
`38139
`
`Venkat Konda
`
`6278 Grand Oak Way
`
`- S
`
`an Jose
`
`US
`
`408-472-3273
`
`venkat@kondatech.com
`
`Correspondence Address:
`
`Attorney Docket Number:
`
`S-0048PCT
`
`
`
`Receipt Date: 16-OCT-2010
`
`Filing Date:
`
`Time Stamp:
`
`21:36:04
`
`Application Type:
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`International Application forfiling in the US receiving office
`
`Paymentinformation:
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`1 ch6f9bOSeedc6f238af76dffc0b7661d5b1
`b6a4-
`
`Information:
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`Drawings-only black and white line
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`drawings
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`S-0048PCT-FIGs.pdf
`
`ef26f82fdcb30966f97325075 1 5dfa32e289
`
`589606
`
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`44471167033e3752d87dfab60d26U67559)
`6a89f
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`RO/101 - Request form for new IA -
`Conventional
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`Fee Worksheet (PTO-875)
`
`fee-info.pdf
`
`b1ce3be06201899840bf897a90c0fb4125a
`a57le
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`the application.
`
`NewInternational Application Filed with the USPTO as a Receiving Office
`If a new international application is being filed and the international application includes the necessary componentsfor
`an international filing date (see PCT Article 11 and MPEP 1810), a Notification of the International Application Number
`and of the International Filing Date (Form PCT/RO/105)will be issued in due course, subject to prescriptions concerning
`national security, and the date shownon this AcknowledgementReceiptwill establish the international filing date of
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`New Applications Under 35 U.S.C. 111
`If a new application is being filed and the application includes the necessary componentsfor a filing date (see 37 CFR
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`$-0048 PCT
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`VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND PYRAMID
`
`NETWORKS WITH LOCALITY EXPLOITATION
`
`Venkat Konda
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is Continuation In Part PCT Application to and incorporates by
`
`referencein its entirety the U.S. Provisional Patent Application Serial No. 61/252, 603
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED NETWORKSWITH LOCALITY
`
`EXPLOITATION"by Venkat Konda assigned to the same assignee as the current
`
`10
`
`application, filed October 16, 2009.
`
`This application is Continuation In Part PCT Application to and incorporates by
`
`referencein its entirety the U.S. Provisional Patent Application Serial No. 61/252, 609
`
`entitled "VLSI LAYOUTS OF FULLY CONNECTED GENERALIZED AND
`
`PYRAMID NETWORKS"by Venkat Kondaassigned to the same assignee as the current
`
`15
`
`application, filed October 16, 2009.
`
`This application is related to and incorporates by referencein its entirety the US
`
`Application Serial No. 12/530,207 entitled "FULLY CONNECTED GENERALIZED
`
`MULTI-STAGE NETWORKS"by Venkat Konda assigned to the same assignee as the
`
`current application, filed September6, 2009, the U.S. Provisional Patent Application
`
`Serial No. 60/905,526 entitled "LARGE SCALE CROSSPOINT REDUCTION WITH
`
`NONBLOCKING UNICAST & MULTICAST IN ARBITRARILY LARGE MULITI-
`
`STAGE NETWORKS"by Venkat Konda assigned to the same assignee as the current
`
`application, filed March 6, 2007, and the U.S. Provisional Patent Application Serial No.
`
`60/940, 383 entitled "FULLY CONNECTED GENERALIZED MULTLSTAGE
`
`25
`
`NETWORKS"by Venkat Kondaassigned to the same assignee as the current application,
`
`filed May 25, 2007.
`
`Page 5 of 191
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`$-0048 PCT
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`This application is related to and incorporates by referencein its entirety the US
`
`Application Serial No. 12/601,273 entitled "FULLY CONNECTED GENERALIZED
`
`BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassignedto the same
`
`assignee as the current application, filed November 22, 2009, the U.S. Provisional Patent
`
`Application Serial No. 60/940, 387 entitled "FULLY CONNECTED GENERALIZED
`
`BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed May 25, 2007, and the U.S. Provisional Patent
`
`Application Serial No. 60/940, 390 entitled "FULLY CONNECTED GENERALIZED
`
`MULTI-LINK BUTTERFLY FAT TREE NETWORKS"by Venkat Kondaassigned to
`
`10
`
`the sameassignee as the current application, filed May 25, 2007
`
`This application is related to and incorporates by referencein its entirety the US
`
`Application Serial No. 12/601,274 entitled "FULLY CONNECTED GENERALIZED
`
`MULTI-LINK MULTI-STAGE NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed November 22, 2009, the U.S. Provisional Patent
`
`15
`
`Application Serial No. 60/940, 389 entitled "FULLY CONNECTED GENERALIZED
`
`REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-STAGE NETWORKS"
`
`by Venkat Konda assigned to the same assignee as the current application, filed May 25,
`
`2007, the U.S. Provisional Patent Application Serial No. 60/940, 391 entitled "FULLY
`
`CONNECTED GENERALIZED FOLDED MULTI-STAGE NETWORKS"by Venkat
`
`20
`
`Konda assigned to the same assigneeas the current application, filed May 25, 2007 and
`
`the U.S. Provisional Patent Application Serial No. 60/940, 392 entitled "FULLY
`
`CONNECTED GENERALIZED STRICTLY NONBLOCKING MULTI-LINK MULTI-
`
`STAGE NETWORKS"by Venkat Konda assigned to the same assigneeas the current
`
`application, filed May 25, 2007.
`
`25
`
`This applicationis related to and incorporates by referencein its entirety the US
`
`Application Serial No. 12/601,275 entitled "VLSI LAYOUTS OF FULLY
`
`CONNECTED GENERALIZED NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed November 22, 2009, and the U.S. Provisional
`
`Patent Application Serial No. 60/940, 394 entitled "VLSI LAYOUTS OF FULLY
`
`Page 6 of 191
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`$-0048 PCT
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`CONNECTED GENERALIZED NETWORKS"by Venkat Kondaassigned to the same
`
`assignee as the current application, filed May 25, 2007.
`
`BACKGROUNDOF INVENTION
`
`Multi-stage interconnection networks such as Benes networksand butterfly fat
`
`tree networks are widely useful in telecommunications, parallel and distributed
`
`computing. However VLSI layouts, known in the prior art, of these interconnection
`
`networks in an integrated circuit are inefficient and complicated.
`
`Other multi-stage interconnection networks including butterfly fat tree networks,
`
`10
`
`Banyan networks, Batcher-Banyan networks, Baseline networks, Delta networks, Omega
`
`networks and Flip networks have been widely studied particularly for self routing packet
`
`switching applications. Also Benes Networks with radix of two have been widely studied
`
`and it is known that Benes Networks of radix two are shown to be built with back to back
`
`baseline networks whichare rearrangeably nonblocking for unicast connections.
`
`15
`
`The most commonly used VLSI layout in an integrated circuit is based on a two-
`
`dimensional grid model comprising only horizontal and vertical tracks. An intuitive
`
`interconnection network that utilizes two-dimensional grid model is 2D Mesh Network
`
`and its variations such as segmented mesh networks. Hence routing networks used in
`
`VLSI layouts are typically 2D mesh networks and its variations. However Mesh
`
`20
`
`Networks require large scale cross points typically with a growth rate of O(N*) where N
`
`is the number of computing elements, ports, or logic elements depending on the
`
`application.
`
`Mullti-stage interconnection network with a growth rate of OLN xlog N) requires
`
`significantly small numberofcross points. U.S. Patent 6,185,220 entitled “Grid Layouts
`
`25
`
`of Switching and Sorting Networks” granted to Muthukrishnanet al. describes a VLSI
`
`layout using existing VLSI grid model for Benes and Butterfly networks. U.S. Patent
`
`6,940,308 entitled “Interconnection Network for a Field Programmable Gate Array”
`
`granted to Wong describes a VLSI layout where switches belonging to lower stage of
`
`3-
`
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`$-0048 PCT
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`Benes Network are layed out close to the logic cells and switches belonging to higher
`
`stages are layed out towards the center of the layout.
`
`Dueto the inefficient and in somecases impractical VLSI layout of Benes and
`
`butterfly fat tree networks on a semiconductor chip, today mesh networks and segmented
`
`mesh networks are widely used in the practical applications such as field programmable
`
`gate arrays (MPGAs), programmable logic devices (PLDs), and parallel computing
`
`interconnects. The prior art VLSI layouts of Benes and butterfly fat tree networks and
`
`VLSI layouts of mesh networks and segmented mesh networks require large arca to
`
`implement the switches on the chip, large numberof wires, longer wires, with increased
`
`10
`
`power consumption,increased latency of the signals which effect the maximum clock
`
`speed of operation. Some networks may not even be implemented practically on a chip
`
`due to the lack of efficient layouts.
`
`SUMMARYOF INVENTION
`
`15
`
`Whenlarge scale sub-integrated circuit blocks with inlet and outlet links are layed
`
`out in an integrated circuit device in a two-dimensional grid arrangement, (for example in
`
`an FPGA where the sub-integrated circuit blocks are Lookup Tables) the most intuitive
`
`routing networkis a network that uses horizontal and vertical links only (the most often
`
`used such a network is one of the variations of a 2D Mesh network). A direct embedding
`
`20
`
`of a generalized multi-stage network on to a 2D Mesh network is neither simple nor
`
`efficient.
`
`In accordance with the invention, VLSI layouts of generalized multi-stage and
`
`pyramid networks for broadcast, unicast and multicast connections are presented using
`
`only horizontal and vertical links with spacial locality exploitation. The VLSI layouts
`
`25
`
`employ shuffle exchange links where outlet links of cross links from switches in a stage
`
`in one sub-integrated circuit block are connectedto inlet links of switches in the
`
`succeeding stage in another sub-integrated circuit block so that said cross links are either
`
`vertical links or horizontal and vice versa. Furthermore the shuffle exchangelinks are
`
`employed between different sub-integrated circuit blocks so that spacially nearer sub-
`
`4.
`
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`$-0048 PCT
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`integrated circuit blocks are connected with shorter links compared to the shuffle
`
`exchange links between spacially farther sub-integrated circuit blocks. In one
`
`embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in
`
`a two-dimensional plane. The VISIT layouts exploit the benefits of significantly lower
`
`cross points, lower signal latency, lower power and full connectivity with significantly
`
`fast compilation.
`
`The VLSI layouts with spacial locality exploitation presented are applicable to
`
`generalized multi-stage and pyramid networks V(N,,N.,d,s) & V,(N,,N,,d,5),
`
`generalized folded multi-stage and pyramid networks V,,,,(N,,N,,d,5) &
`
`10
`
`Vioap (N,,N>,d,5), generalized butterfly fat tree and butterfly fat pyramid networks
`
`Vig(N,N,,d,5) & V,.(N,,N,,d,8), generalized multi-link multi-stage and pyramid
`
`networks V_,,,,(N,,N,,d,s) & V,,
`
`fink—p
`
`(N,,N,,d,5), generalized folded multi-link multi-
`
`stage and pyramid networks Vig ming Ni>N05455) & Vio mine p(Ni»N>.d,5),
`
`generalized multi-link butterfly fat tree and butterfly fat pyramid networks
`
`15
`
`Vtink—bje (N,,N,,d,5) & Vnlink—bfp (N,.N,,d,5), generalized hypercube networks
`
`Vicuve(N,,N,,d,8), and generalized cube connected cycles networks V,...(N,,N,,d,5)
`
`for s = 1,2,3 or any numberin general. The embodiments of VLSI layouts are useful in
`
`wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placementand route
`
`tools, networking applications, parallel & distributed computing, and reconfigurable
`
`20
`
`computing.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1A is a diagram 100A of an exemplary symmetrical multi-link multi-stage
`
`network Viimine(N,d,5) having a variation of inverse Benes connection topology of
`
`25
`
`nine stages with N = 32, d = 2 and s=2, strictly nonblocking network for unicast
`
`connections and rearrangeably nonblocking network for arbitrary fan-out multicast
`
`connections, in accordance with the invention.
`
`5.
`
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`$-0048 PCT
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`FIG. 1B is a diagram 100B ofthe equivalent symmetrical folded multi-link multi-
`
`stage network Veeijutine(N,d,s) of the network 100A shown in FIG. 1A, having a
`
`variation of inverse Benes connection topology of five stages with N = 32, d= 2 and s=2,
`
`striclly nonblocking network [for unicast connecuons and rearrangeably nonblocking
`
`networkforarbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG, 1C is a diagram 100C layoutof the network Vjoining (N@,5) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
`
`FIG. 1D is a diagram 100D layout of the network V,jold—milink (N, d, s) shown in
`
`10
`
`FIG, 1B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 64] and
`
`ML(8,i) for 1 = [1,64].
`
`PIG. 1H is a diagram 100E layout of the network V
`
`fold
`
`.,,_jig. N.d,8) shown in FIG.
`
`1B, in one embodiment, illustrating the connection links ML(2,i) for 1 = [1, 64] and
`
`ML(7,1) for 1 = [1,64].
`
`15
`
`FIG, 1F is a diagram 100F layoutof the network Vp14miing(N»d,8) shown in FIG,
`
`1B, in one embodiment, illustrating the connection links ML(@,i) for i = [1, 64] and
`
`ML(6,i) for i = [1,64].
`
`FIG. 1G is a diagram 100G layout of the network V,jold-mine (N,d,8) shown in
`
`FIG, 1B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`20
`
`ML(5,i) for i = [1,64].
`
`FIG. 1H is a diagram 100H layout of a network Vpi)inion (N.d,8) where N = 128,
`
`d= 2, and s = 2, in one embodiment,illustrating the connection links belonging with in
`
`each block only.
`
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`$-0048 PCT
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`FIG, 11 is a diagram 100I detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out when the layout 100C is implementing V,,,(N.d,5) OF Vegamine (N> 4,5) «
`
`FIG. 1J is a diagram 100J detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 100C is implementing Vj,Ȣ(N.d,5)
`
`FIG. 1K is a diagram 100K detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`out when the layout 100C is implementing V(N,d,s) or Vfold (N,d,s).
`
`FIG. 1K1 is a diagram 100M1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`out when the layout 100C is implementing V(N,d,s) or V,(aia (N.d,s) fors=1.
`
`FIG. 1L is a diagram 100L detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment, illustrating the connection links going in and coming
`
`15
`
`out whenthe layout 100C is implementing Vig (N,d,8).
`
`T'IG. 1L1 is a diagram 100L1 detailed connections of BLOCK 1_2 in the network
`
`layout 100C in one embodiment,illustrating the connection links going in and coming
`
`out whenthe layout 100C is implementing V,,(N,d,s) fors = 1.
`
`FIG, 2A is a diagram 200A of an exemplary symmetrical multi-link multi-stage
`
`20
`
`network Vii¢-ming(N,d,5) having inverse Benes connection topology of nine stages with
`
`N = 24, d = 2 and s=2, strictly nonblocking network for unicast connections and
`
`rearrangeably nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
`
`FIG, 2B is a diagram 200B of the equivalent symmetrical folded multi-link multi-
`
`stage network Vjot-mink (Nd, 8) of the network 200A shownin FIG. 2A,having inverse
`
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`$-0048 PCT
`
`Benes connection topologyoffive stages with N = 24, d=2and s=2, strictly nonblocking
`
`network for unicast connections and rearrangeably nonblocking network forarbitrary fan-
`
`out multicast connections, in accordance with the invention.
`
`FIG, 2C is a diagram 200C layoutof the network V,14nine (N.d@,5) shownin FIG.
`
`2B, in one embodiment, illustrating the connection links belonging with in each block
`
`only.
`
`FIG. 2D is a diagram 200D layout of the network V,jold—miink (N,d,s) shown in
`
`FIG. 2B, in one embodiment, illustrating the connection links ML(1,i) fori = [1, 48] and
`
`ML(8,i) for 1 = [1,48].
`
`10
`
`FIG. 2E is a diagram 200E layout of the network Viginiing (N»@,5) shown in FIG,
`
`2B, in one embodiment, illustrating the connection links ML(2,i) for i = [1, 32] and
`
`ML(7,i) for i = [1,32].
`
`FIG, 2F is a diagram 200F layout of the networkVping(Nd@,5) shown in FIG.
`
`2B, in one embodiment, illustrating the connection links ML(@,i) for 1 = [1, 64] and
`
`15
`
`ML(6,1) for 1 = [1,64].
`
`FIG. 2G is a diagram 200G layout of the network V,jfold—miink (N,d,s) shown in
`
`T'IG, 2B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`ML(5,1i) for 1 = [1,64].
`
`FIG. 3A is a diagram 300A layout of the topmost
`
`row of the network
`
`Vfold—minr (N,d,8) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`provisioning of 2’s BW.
`
`FIG. 3B is a diagram 300B layout of the topmost
`
`row of the network
`
`Vfold—miink (Nd, 8) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`provisioning of 4’s BW.
`
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`$-0048 PCT
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`FIG. 3C is a diagram 300C layout of the topmost
`row of the network
`Ve0.ia-miink(N>d,5) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`provisioning of 8’s BW with nearest neighbor connectivityfirst.
`
`FIG. 3D is a diagram 300D layout of the topmost
`row of the network
`Vi0.ta-mine N,d,5) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`provisioning of 8’s BW with nearest neighbor connectivity recursively.
`
`FIG. 4A is a diagram 400A layout of the lopmost
`
`row of the network
`
`Vfola—miink (N,d,8) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`provisioning of 2’s BW infirst stage.
`
`FIG. 4B is a diagram 400B layout of the topmost
`
`row of the network
`
`Vvfola—mink (Nd, 8) with N = 512, d = 2 and s=2, in one embodiment,
`
`illustrating the
`
`remaining nearest neighbor connectivity in the second stage by provisioning 4’s BW, 8’s
`
`BW etc.
`
`FIG. 4C is a diagram 400C layout of the topmost
`
`row of the network
`
`15
`
`Vota-mine (Nd, 5) with N = 512, d= 2 and s=2, in one embodiment,illustrating the third
`
`stage, by provisioning 4’s and 8’s BW.
`
`TlG.
`
`5
`
`is
`
`a diagram 500 layout of
`
`the topmost
`
`row of
`
`the network
`
`Vietaming Nd, 5) with N = 512, d = 2 and s = 2, in one embodiment, illustrating the
`
`provisioning of 8’s BW and 16’s BW in Partial & Tapered Connectivity (Bandwidth) in a
`
`20
`
`stage.
`
`FIG.
`
`6 is
`
`a diagram 600 layout of
`
`the topmost
`
`row of
`
`the network
`
`Viotd—miink (N»@,5) with N = 2048, d = 2 and s = 2, in one embodiment, illustrating the
`
`provisioning of 8’s BW, 16’s BW and 32’s BW in Partial & Tapered Connectivity
`
`(Bandwidth)in a stage.
`
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`$-0048 PCT
`
`FIG.
`
`7 is
`
`a diagram 700 layout of
`
`the topmost
`
`row of
`
`the network
`
`Vvota—mtinn (Nd, 5) with N = 2048, d = 2 and s = 2, in one embodiment,illustrating the
`
`provisioning of 8's BW, 16’s BW and 32’s BW in Partial & Tapered Connectivity
`
`(Bandwidth) in a stage with equal length wires.
`
`FIG. 8A is a diagram 800A of an exemplary symmetrical multi-link multi-stage
`
`pyramid network V,,
`
`link—p
`
`(N,d,s) having inverse Benes connection topology of nine
`
`stages with N = 32, d = 2 and s=2,strictly nonblocking network for unicast connections
`
`and rearrangeably nonblocking network for arbitrary fan-out multicast connections, in
`
`accordance with the invention.
`
`10
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`T'IG. 8B is a diagram 800B of the equivalent symmetrical folded multi-link multi-
`
`stage pyramid network Vagusmutinep(N.d@,8) of the network 800A shown in FIG. 8A,
`
`having inverse Benes connection topology of five stages with N = 32, d = 2 and s=2,
`
`strictly nonblocking network for unicast connections and rearrangeably nonblocking
`
`networkfor arbitrary fan-out multicast connections, in accordance with the invention.
`
`15
`
`FIG. 8C is a diagram 800C layout of the network Viiningp N»d.8) shown in
`
`FIG. 8B, in one embodiment, illustrating the connection links belonging with in each
`
`block only.
`
`FIG. 8D is a diagram 800D layout of the network Vfold—mlink—p (N,d,s) shown in
`
`FIG. 8B, in one embodiment, illustrating the connection links ML(1,i) for i = [1, 64] and
`
`20
`
`ML(8,1) for i = [1,64].
`
`FIG. 8E is a diagram 800E layout of the network V,fold —mlink—p (N,d,s) shown in
`
`FIG. 8B, in one embodiment, illustrating the connection links ML(,1) fori = [1, 64] and
`
`ML(7,1) for 1 = [1,64].
`
`FIG. 8F is a diagram 800F layout of the network Vgi1jnin._p(N.d.5) shown in
`
`25
`
`FIG, 8B, in one embodiment, illustrating the connection links ML(3,i) for i = [1, 64] and
`
`ML(6,1) for 1 = [1,64].
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`-10-
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`FIG. 8G is a diagram 800G layout of the network Vold—mlint—p (N,d,s) shown in
`
`FIG. 8B, in one embodiment, illustrating the connection links ML(4,i) for i = [1, 64] and
`
`ML(5,1) for i = [1,64].
`
`FIG. 8H is a diagram 800H layout of a network Vii)ntine_p (N>d,8) where N =
`
`128, d= 2, ands = 2, in one embodiment, illustrating the connection links belonging with
`
`in each block only.
`
`FIG, 81 is a diagram 800I detailed connections of BLOCK 1_2 in the network
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 800C is implementing V,,
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`link—p
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`
`
`(N.d,s) or V,old—mlink—p
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`(N,d,s).
`
`FIG. 8J is a diagram 800J detailed connections of BILOCK 1_2 in the network
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 800C is implementing V,,,,,9, (N.d, 5).
`
`FIG. 8K is a diagram 800K detailed connections of BLOCK 1_2 in the network
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`15
`
`out whenthe layout 800C is implementing V, (NV,d,s) or Viig_)(N.d,5) .
`
`T'lG. 8K1 is a diagram 800M1 detailed connections of BLOCK 1_2in the network
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 800C is implementing V, (NV,d,s) or V,,,_,(N,d,5) fors = 1.
`fold—p
`
`FIG. 8L is a diagram 800L detailed connections of BLOCK 1_2 in the network
`
`20
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`out whenthe layout 800C is implementing V,, (Nd, 5).
`
`FIG. 8L1 is a diagram 800L1 detailed connections of BLOCK 1_2 in the network
`
`layout 800C in one embodiment, illustrating the connection links going in and coming
`
`out when the layout 800C is implementing V,, (Nd, s) fors = 1.
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`FIG. 9A is high-level flowchart of a scheduling method 900 according to the
`
`invention, used to set up the multicast connections in the generalized multi-stage pyramid
`
`network and the generalized multi-link multi-stage pyramid network disclosed in this
`
`invention.
`
`FIG. 10A is high-level flowchart of a scheduling method 1000 according to the
`
`invention, used to set up the multicast connections in the generalized butterfly fat
`
`pyramid network and the generalized multi-link butterfly fat pyramid network disclosed
`
`in this invention.
`
`FIG. 11A1 is a diagram 1100A1 of an exemplary prior art implementation ofa
`
`10
`
`two by two switch; FIG. 11A2 is a diagram 1100A2 for programmable integrated circuit
`
`prior art implementation of the diagram 1100A1 of FIG. 11A1; FIG. 11A3 is a diagram
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`1100A3 for one-time programmable integrated circuit prior art implementation of the
`
`diagram 1100A1 of FIG. 11A1; FIG. 11A4 is a diagram 1100A4 for integrated circuit
`
`placement and route implementation of the diagram 1100A1 of FIG. 11A1.
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`15
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`The present invention is concerned with the VLSIlayouts of arbitrarily large
`
`switching networks for broadcast, unicast and multicast connections. Particularly
`
`switching networks consideredin the current invention include: generalized multi-stage
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`20
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`networks V(N,,N,,d,5), generalized folded multi-stage networks V,,,,(N,,N,.d,5),
`
`generalized butterfly fat tree networks Vig (N,,N,,d,5), generalized multi-link multi-
`
`stage networksV,,,,,,(N,,N,,d,8), generalized folded multi-link multi-stage networks
`
`Vfold—miink (N,,N,.d,8), generalized multi-link butterfly fat tree networks
`
`Mn
`V linkbj (N,,N,,d,5), generalized hypercube networks V,,
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`cube
`
`(N,,N,,d,s), and
`
`eee
`generalized cube connected cycles networks V...(N,,N,,d,s) for s = 1,2,3 or any
`
`numberin general.
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`-12-
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`Efficient VLSI layout of networks on a semiconductor chip are very important
`
`and greatly influence many important design parameters such as the area taken up by the
`
`network on the chip, total number of wires, length of the wires, latency of the signals,
`
`capacitance and hence the maximum clock speed of operation. Some networks may not
`
`even be implemented practically on a chip dueto the lack ofefficient layouts. The
`
`different varieties of multi-stage networks described above have not been implemented
`
`previously on the semiconductor chipsefficiently. For example in Field Programmable
`
`Gate Array (FPGA) designs, multi-stage networks described in the current invention have
`
`not been successfully implemented primarily due to the lack of efficient VLSI layouts.
`
`10
`
`Current commercial FPGA products such as Xilinx Vertex, Altera’s Stratix implement
`
`island-style architecture using mesh and segmented meshrouting interconnects using
`
`either full crossbars or sparse crossbars. These routing interconnects consumelarge
`
`silicon area for crosspoints, long wires, large signal propagation delay and hence
`
`consumelot of power.
`
`15
`
`‘The current invention discloses the VLSI layouts of numeroustypes of multi-
`
`stage and pyramid networks whichare very efficient and exploit spacial locality in the
`
`connectivity. Moreover they can be embedded on to mesh and segmented mesh routing
`
`interconnects of current commercial FPGA products. The VLSI layouts disclosed in the
`
`current invention are applicable to including the numerous generalized multi-stage
`
`20
`
`networksdisclosed in the following patent applications:
`
`1) Strictly and rearrangeably nonblocking forarbitrary fan-out multicast and
`
`unicast for generalized multi-stage networks V(N,,N.,,d,s) with numerous connection
`
`topologies and the scheduling methods are described in detail in the US Application
`
`Serial No. 12/530,207 that is incorporated by reference above.
`
`25
`
`2) Strictly and rearrangeably nonblockingfor arbitrary fan-out multicast and
`
`unicast for generalized butterfly fat tree networks Vo (N,,N,.d,5) with numerous
`
`connection topologies and the scheduling methods are described in detail in the US
`
`Application Serial No. 12/601,273 that is incorporated by reference above.
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`3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and
`
`strictly nonblocking for unicast for generalized multi-link multi-stage networks
`
`Vine (N1»N>,d,5) and generalized folded multi-link multi-stage networks
`
`Vfold—mink (N,,N,,d,8) with numerous connection topologies and the scheduling methods
`
`are described in detail in the US Application Serial No. 12/601,274 that is incorporated
`
`by reference above.
`
`4) Strictly and rearrangeably nonblockingfor arbitrary fan-out multicast and
`
`unicast for generalized multi-link butterfly fat tree networks V,ing_o¢(N,.N.,d,5) with
`
`numerous connection topologies and the scheduling methods are described in detail in the
`
`10
`
`US Application Serial No. 12/601,273that is incorporated by reference above.
`
`5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized folded multi-stage networks V,,,,(N,,N,,d,5) with numerous
`
`connection topologies and the scheduling methods are described in detail in the US
`
`Application Serial No. 12/601,274 that is incorporated by reference above.
`
`15
`
`6) Strictly nonblocking for arbitrary fan-out multicast and unicast for generalized
`
`multi-link multi-stage networksV,,/,,,(N,,N,,d,8) and generalized folded multi-link
`
`multi-stage networks Vpi4ting (N,N>,d,8) with numerous connection topologies and
`
`the scheduling methodsare described in detail in the US Application Serial No.
`
`12/601,274 that is incorporated byreference above.
`
`20
`
`7) VLSI layouts of numerous types of multi-stage networks are described in the
`
`US Application Serial No. 12/601,275 entitled "VLSI LAYOUTS OF FULLY
`
`CONNECTED NETWORKS"that is incorporated by reference above.
`
`In addition the layouts of the current invention are also applicable to generalized
`
`multi-stage pyramid networks V,,(N,,N,,d,8), generalized folded multi-stage pyramid
`
`25
`
`networks Vi.4_, (N,,N,,d,5), generalized butterfly fat pyramid networks
`
`Vi, (N,,N.,d,5), generalized multi-link multi-stage pyramid networks
`
`14
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`Vnlink—p (N,.N,,d,s), generalized folded multi-link multi-stage pyramid networks
`
`Vfold—mink-p (N,,N,,d,5), generalized multi-link butterfly fat pyramid networks
`
`m
`cube
`V tino (N1»N>,d,8), generalized hypercube networks V,,,,.(N,,N,,d,5) and
`
`generalized cube connected cycles networks V.¢¢(N,,N,,d,8) for s = 1,2,3 or any
`
`numberin general.
`
`Symmetric RNB generalized multi-link multi-stage network V,,,,,(N,.N,,d,5),
`
`Connection Topology: Nearest Neighbor connectivity and with Full Bandwidth:
`
`Referring to diagram 100A in FIG. 1A, in one embodiment, an exemplary
`
`10
`
`generalized multi-link multi-stage network V,,,,,,(N,,N,,d,5) where Ny = N2 = 32; d=
`
`2; and s = 2 with nine stages of one hundred andforty four switches for satisfying
`
`communication requests, such as selling up a telephone call or a data call, or a connection
`
`between configurable logic blocks, between an input stage 110 and output stage 120 via
`
`middle stages 130, 140, 150, 160, 170, 180 and 190 is shown where input stage 110
`
`15
`
`consists of sixteen, two by four switches IS1-IS16 and output stage 120 consists of
`
`sixteen, four by two switches OS1-OS16. Andall the middle stages namely the middle
`
`stage 130 consists of sixteen, four by four switches MS(1,1) - MS(1,16), middle stage
`
`140 consists of sixteen, four by four switches MS(2,1) - MS(@,16), middle stage 150
`
`consists of sixteen, four by four switches MS(3,1) - MS(3,16), middle stage 160 consists
`
`of sixteen, four by four switches MS(4,1) - MS(4,16), middle stage 170 consists of
`
`sixteen, four by four switches MS(5,1) - MS(G,16), middle stage 180 consists of sixteen,
`
`four by four switches MS(6,1) - MS(6,16), and middle stage 190 consists of sixteen, four
`
`by four switches MS(7,1) - MS(7,16).
`
`Asdisclosed in U.S. Provisional Patent Application Serial No. 60/940,389 that is
`
`25
`
`incorporated by reference above, such a network can be operated in rearrangeably non-
`
`blocking mannerforarbitrary fan-out mu