M—0042 US
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`FULLY CONNECTED GENERALIZED STRICTLY NONBLOCKING
`
`MULTI-LINK MULTI-STAGE NETWORKS
`
`Venkat Konda
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is related to and incorporates by reference in its entirety the US.
`
`Provisional Patent Application Docket No. M-0037US entitled "FULLY CONNECTED
`
`GENERALIZED MULTI-STAGE NETWORKS" by Venkat Konda assigned to the same
`
`10
`
`assignee as the current application, filed concurrently.
`
`This application is related to and incorporates by reference in its entirety the US.
`
`Provisional Patent Application Docket No. M-003 SUS entitled "FULLY CONNECTED
`
`GENERALIZED BUTTERFLY FAT TREE NETWORKS" by Venkat Konda assigned
`
`to the same assignee as the current application, filed concurrently.
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`15
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`This application is related to and incorporates by reference in its entirety the US.
`
`Provisional Patent Application Docket No. M-0039US entitled "FULLY CONNECTED
`
`GENERALIZED REARRANGEABLY NONBLOCKING MULTI-LINK MULTI-
`
`STAGE NETWORKS" by Venkat Konda assigned to the same assignee as the current
`
`application, filed concurrently.
`
`This application is related to and incorporates by reference in its entirety the US.
`
`Provisional Patent Application Docket No. M-0040US entitled "FULLY CONNECTED
`
`GENERALIZED MULTI-LINK BUTTERFLY FAT TREE NETWORKS" by Venkat
`
`Konda assigned to the same assignee as the current application, filed concurrently.
`
`This application is related to and incorporates by reference in its entirety the US.
`
`Provisional Patent Application Docket No. M-0041US entitled "FULLY CONNECTED
`
`GENERALIZED FOLDED MULTI—STAGE NETWORKS" by Venkat Konda assigned
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`to the same assignee as the current application, filed concurrently.
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`FLEX LOGIX EXHIBIT 1023
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`FLEX LOGIX EXHIBIT 1023
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`M—0042 US
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`This application is related to and incorporates by reference in its entirety the US
`
`Provisional Patent Application Docket No. M-0045US entitled ”VLSI LAYOUTS OF
`
`FULLY CONNECTED GENERALIZED NETWORKS" by Venkat Konda assigned to
`
`the same assignee as the current application, filed concurrently.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1A is a diagram 100A of an exemplary symmetrical multi-link multi-stage
`
`network thnk (N ,d , 5) having inverse Benes connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
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`10
`
`FIG. 1B is a diagram 100B of an exemplary symmetrical multi—link multi—stage
`
`network Vmlin
`
`k(N,d,s) (having a connection topology built using back-to-back Omega
`
`Networks) of five stages with N = 8, d = 2 and s=3, strictly nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1C is a diagram 100C of an exemplary symmetrical multi-link multi-stage
`
`15
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`network Vmlink
`
`(N, (1,5) having an exemplary connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
`
`FIG. 1D is a diagram 100D of an exemplary symmetrical multi-link multi-stage
`network Vmlink (N, (1,5) having an exemplary connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
`
`FIG. 1E is a diagram 100E of an exemplary symmetrical multi-link multi-stage
`
`network Vmlink (N, d, 5) (having a connection topology called flip network and also known
`
`as inverse shuffle exchange network) of five stages with N = 8, d = 2 and s=3, strictly
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`invention.
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`FIG. 1F is a diagram 100F of an exemplary symmetrical multi-link multi-stage
`
`network thnk (N ,d , s) having Baseline connection topology of five stages with N = 8, d
`
`= 9 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections, in
`
`accordance with the invention.
`
`FIG. 1G is a diagram 100G of an exemplary symmetrical multi-link multi-stage
`
`network leink (N, d,s) having an exemplary connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
`
`FIG. 1H is a diagram 100H of an exemplary symmetrical multi-link multi-stage
`
`network leink (N, (1,5) having an exemplary connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
`
`FIG. 11 is a diagram 1001 of an exemplary symmetrical multi—link multi—stage
`
`network thnk (N ,d ,5)
`
`(having a connection topology built using back-to-back Banyan
`
`Networks or back-to-back Delta Networks or equivalently back-to-back Butterfly
`
`networks) of five stages with N = 8, d = 2 and s=3, strictly nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1] is a diagram 100] of an exemplary symmetrical multi-link multi-stage
`
`network leink (N, (1,5) having an exemplary connection topology of five stages with N =
`
`8, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in accordance with the invention.
`
`FIG. 1K is a diagram 100K of a general symmetrical multi-link multi-stage
`network Vmlink (N,d,s) with (2xlogd N)—1
`
`strictly nonblocking
`
`stages with s=3,
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1A1 is a diagram 100A1 of an exemplary asymmetrical multi-link multi-
`
`stage network leink(N1,N2,d,s) having inverse Benes connection topology of five
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`stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1B1 is a diagram 100B1 of an exemplary asymmetrical multi-link
`
`multi-stage network thnk (N1,N2,d ,5) (having a connection topology built using back-
`
`to-back Omega Networks) of five stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2
`
`and s=3, strictly nonblocking network for arbitrary fan-out multicast connections.
`
`FIG. 1C1 is a diagram 100C1 of an exemplary asymmetrical multi-link multi-
`
`m
`stage network V
`
`link(N1,N2,d,s) having an exemplary connection topology of five
`
`stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1D1 is a diagram 100D1 of an exemplary asymmetrical multi-link multi-
`
`stage network lemk (N1,N2,d , 5) having an exemplary connection topology of five stages
`
`with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking network
`
`for arbitrary fan—out multicast connections, in accordance with the invention.
`
`FIG.
`
`IE] is a diagram 100E] of an exemplary asymmetrical multi-link multi-
`
`stage network lemk (N1,N2 ,d, 5) (having a connection topology called flip network and
`
`also known as inverse shuffle exchange network) of five stages with N1 = 8, N2 = p* N1
`
`= 24 where p = 3, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out
`
`multicast connections, in accordance with the invention.
`
`FIG. 1F1 is a diagram 100F1 of an exemplary asymmetrical multi-link multi-stage
`
`network leink (N1 , N2 , d , 5) having Baseline connection topology of five stages with N1 =
`
`8, N2 = p1< N1 = 24 where p = 3, d = 2 and 323, strictly nonblocking network for arbitrary
`
`fan-out multicast connections, in accordance with the invention.
`
`FIG. 1G1 is a diagram 100G1 of an exemplary asymmetrical multi-link multi-
`
`stage network thnk (N1,N2,d,s) having an exemplary connection topology of five
`
`stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
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`FIG. 1H1 is a diagram 100H1 of an exemplary asymmetrical multi-link multi-
`
`stage network thnk (N1,N2,d,s) having an exemplary connection topology of five
`
`stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 111 is a diagram 10011 of an exemplary asymmetrical multi-link multi-stage
`
`network leink (N1, N2,d , s)
`
`(having a connection topology built using back—to—back
`
`Banyan Networks or back-to-back Delta Networks or equivalently back-to-back Butterfly
`
`networks) of five stages with N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`10
`
`invention.
`
`FIG. 1J1 is a diagram 100J1 of an exemplary asymmetrical multi-link multi-stage
`
`network thnk (N1 ,N2,al , 5) having an exemplary connection topology of five stages with
`
`N1 = 8, N2 = p* N1 = 24 where p = 3, d = 2 and s=3, strictly nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1K1 is a diagram 100K1 of a general asymmetrical multi-link multi-stage
`
`network leink(N1,N2,d, s) with (2Xlogd N)—1 stages with N1 = p* N2 and s=3, strictly
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`invention.
`
`FIG. 1A2 is a diagram 100A2 of an exemplary asymmetrical multi—link multi—
`
`stage network leink (N1,N2,d,s) having inverse Benes connection topology of five
`
`stages with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1B2 is a diagram 100B2 of an exemplary asymmetrical multi-link multi-
`
`stage network thnk (N1 , N2 , d , 5) (having a connection topology built using back-to-back
`
`Omega Networks) of five stages with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and
`
`s=3,
`
`strictly nonblocking network for arbitrary fan-out multicast connections,
`
`in
`
`accordance with the invention.
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`FIG. 1C2 is a diagram 100C2 of an exemplary asymmetrical multi-link multi-
`
`stage network thnk (N1,N2,d,s) having an exemplary connection topology of five
`
`stages with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and 523, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1D2 is a diagram 100D2 of an exemplary asymmetrical multi-link multi-
`
`stage network leink (N1,N2,al , 5) having an exemplary connection topology of five stages
`
`with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking network
`
`for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1E2 is a diagram 100E2 of an exemplary asymmetrical multi-link multi-
`
`stage network leink(N1,N2,d, 5) (having a connection topology called flip network and
`
`also known as inverse shuffle exchange network) of five stages with N2 = 8, N1 = p* N2
`
`= 24, where p = 3, d = 2 and s=3, strictly nonblocking network for arbitrary fan-out
`
`multicast connections, in accordance with the invention.
`
`FIG. 1F2 is a diagram 100F2 of an exemplary asymmetrical multi—link multi—stage
`
`network leink (N1 , N2 , d , 5) having Baseline connection topology of five stages with N2 =
`
`8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1G2 is a diagram 100G2 of an exemplary asymmetrical multi-link multi-
`
`stage network leink (N],N2,d,s) having an exemplary connection topology of five
`
`stages with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking
`
`network for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1H2 is a diagram 100H2 of an exemplary asymmetrical multi-link multi-
`
`stage network leink (N1,N2,d , 5) having an exemplary connection topology of five stages
`
`with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking network
`
`for arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 112 is a diagram 10012 of an exemplary asymmetrical multi-link multi-stage
`
`network Vmlink
`
`(N1,N2,d,s)
`
`(having a connection topology built using back-to-back
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`Banyan Networks or back-to-back Delta Networks or equivalently back-to-back Butterfly
`
`networks) of five stages with N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3,
`
`strictly nonblocking network for arbitrary fan-out multicast connections, in accordance
`
`with the invention.
`
`FIG. 1J2 is a diagram 10012 of an exemplary asymmetrical multi-link multi-stage
`
`network lemk (N1,N2,d,s) having an exemplary connection topology of five stages with
`
`N2 = 8, N1 = p* N2 = 24, where p = 3, d = 2 and s=3, strictly nonblocking network for
`
`arbitrary fan-out multicast connections, in accordance with the invention.
`
`FIG. 1K2 is a diagram 100K2 of a general asymmetrical multi-link multi-stage
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`10
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`network thnk(N1,N2,d, s) with (2xlogd N)—1 stages with N2 = p* N and s=3, strictly
`
`nonblocking network for arbitrary fan-out multicast connections, in accordance with the
`
`invention.
`
`FIG. 2A is high-level
`
`flowchart of a scheduling method according to the
`
`invention, used to set up the multicast connections in all the networks disclosed in this
`
`15
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`invention.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`The present invention is concerned with the design and operation of large scale
`
`crosspoint reduction using arbitrarily large multi-link multi-stage switching networks for
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`20
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`broadcast, unicast and multicast connections. Particularly multi-link multi-stage networks
`
`with stages more than three and radices greater than or equal to two offer large scale
`
`crosspoint reduction when configured with optimal links as disclosed in this invention.
`
`When a transmitting device simultaneously sends information to more than one
`
`receiving device, the one-to-many connection required between the transmitting device
`
`and the receiving devices is called a multicast connection. A set of multicast connections
`
`is referred to as a multicast assignment. When a transmitting device sends information to
`
`one receiving device, the one-to-one connection required between the transmitting device
`
`and the receiving device is called unicast connection. When a transmitting device
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`simultaneously sends information to all the available receiving devices, the one-to-all
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`connection required between the transmitting device and the receiving devices is called a
`
`broadcast connection.
`
`In general, a multicast connection is meant to be one-to-many connection, which
`
`includes unicast and broadcast connections. A multicast assignment in a switching
`
`network is nonblocking if any of the available inlet links can always be connected to any
`
`of the available outlet links.
`
`In certain multi-link multi-stage networks of the type described herein, any
`
`connection request of arbitrary fan-out, i.e. from an inlet link to an outlet link or to a set
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`10
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`of outlet links of the network, can be satisfied without blocking if necessary by
`
`rearranging some of the previous connection requests. In certain other multi-link multi-
`
`stage networks of the type described herein, any connection request of arbitrary fan-out,
`
`i.e. from an inlet link to an outlet link or to a set of outlet links of the network, can be
`
`satisfied without blocking with never needing to rearrange any of the previous connection
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`requests.
`
`In certain multi-link multi-stage networks of the type described herein, any
`
`connection request of unicast from an inlet link to an outlet link of the network, can be
`
`satisfied without blocking if necessary by rearranging some of the previous connection
`
`requests. In certain other multi-link multi-stage networks of the type described herein,
`
`any connection request of unicast from an inlet link to an outlet link of the network, can
`
`be satisfied without blocking with never needing to rearrange any of the previous
`
`connection requests.
`
`Nonblocking configurations for other types of networks with numerous
`
`connection topologies and scheduling methods are disclosed as follows:
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`1) Strictly and rearrangeably nonblocking for arbitrary fan—out multicast and
`
`unicast for generalized multi-stage networks V(N1 , N2 , d , s) with numerous connection
`
`topologies and the scheduling methods are described in detail in US. Provisional Patent
`
`Application, Attorney Docket No. M-0037 US that is incorporated by reference above.
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`2) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized butterfly fat tree networks Vbfl (N1 , N2 , d , s) with numerous
`
`connection topologies and the scheduling methods are described in detail in U.S.
`
`Provisional Patent Application, Attorney Docket No. M-0038 US that is incorporated by
`
`reference above.
`
`3) Rearrangeably nonblocking for arbitrary fan-out multicast and unicast, and
`
`strictly nonblocking for unicast for generalized multi-link multi-stage networks
`
`leink (N1 , N2 , d , s) and generalized folded multi—link multi—stage networks
`
`Vfoldwlmk (N1 , N2 , d , s) with numerous connection topologies and the scheduling methods
`
`are described in detail in US. Provisional Patent Application, Attorney Docket No. M-
`
`0039 US that is incorporated by reference above.
`
`4) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized multi-link butterfly fat tree networks lemk_bfl (N1 , N2 , d , s) with
`
`numerous connection topologies and the scheduling methods are described in detail in
`
`U.S. Provisional Patent Application, Attorney Docket No. M-0040 US that is
`
`incorporated by reference above.
`
`5) Strictly and rearrangeably nonblocking for arbitrary fan-out multicast and
`
`unicast for generalized folded multi—stage networks Vfold (N1 , N2 , d , s) with numerous
`
`connection topologies and the scheduling methods are described in detail in US.
`
`Provisional Patent Application, Attorney Docket No. M-0041 US that is incorporated by
`
`reference above.
`
`6) VLSI layouts of generalized multi-stage networks V(N1 ,N2,d, s) , generalized
`
`folded multi-stage networks VMd (N1 , N2 , d , s) , generalized butterfly fat tree networks
`
`Vbfi (N1, N2 , d , s) , generalized multi-link rnulti-stage networks lemk (N1 , N2 , d , s) ,
`
`generalized folded multi—link multi—stage networks Vfoldwhnk (N1 , N2 , d , s) , generalized
`
`multi-link butterfly fat tree networks lemk_bfi (N1 , N2 , d, s) , and generalized hypercube
`
`networks thube (N1, N2,d ,s) for s = 1,2,3 or any number in general, are described in
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`detail in US. Provisional Patent Application, Attorney Docket No. M-0045 US that is
`
`incorporated by reference above.
`
`Symmetric SNB Embodiments:
`
`Referring to FIG. 1A, in one embodiment, an exemplary symmetrical multi-link
`
`multi-stage network 100A with five stages of twenty switches for satisfying
`
`communication requests, such as setting up a telephone call or a data call, or a connection
`
`between configurable logic blocks, between an input stage 110 and output stage 120 via
`
`middle stages 130, 140, and 150 is shown where input stage 110 consists of four, two by
`
`six switches 131-134 and output stage 120 consists of four, six by two switches OSl-OS4.
`
`And all the middle stages namely middle stage 130 consists of four, six by six switches
`
`MS(l,l) - MS(1,4), middle stage 140 consists of four, six by six switches MS(2,1) -
`
`MS(2,4), and middle stage 150 consists of four, six by six switches MS(3,1) - MS(3,4).
`
`Such a network can be operated in strictly non-blocking manner for multicast
`
`connections, because the switches in the input stage 110 are of size two by six, the
`
`switches in output stage 120 are of size six by two, and there are four switches in each of
`
`middle stage 130, middle stage 140 and middle stage 150.
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`In one embodiment of this network each of the input switches 131-184 and output
`
`switches OSl-OS4 are crossbar switches. The number of switches of input stage 110 and
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`of output stage 120 can be denoted in general with the variable % , where N is the total
`
`number of inlet links or outlet links. The number of middle switches in each middle stage
`
`is denoted by E . The size of each input switch ISl-IS4 can be denoted in general with
`d
`
`the notation d * 3d and each output switch OSl-OS4 can be denoted in general with the
`
`notation 3d * d . Likewise, the size of each switch in any of the middle stages can be
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`denoted as 3d * 3d . A switch as used herein can be either a crossbar switch, or a network
`
`of switches each of which in turn may be a crossbar switch or a network of switches. A
`
`symmetric multi—link multi—stage network can be represented with the notation
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`leink (N, d , s) , where N represents the total number of inlet links of all input switches
`
`(for example the links ILl-ILS), d represents the inlet links of each input switch or outlet
`
`links of each output switch, and s is the ratio of number of outgoing links from each
`
`input switch to the inlet links of each input switch. Although it is not necessary that there
`
`be the same number of inlet links IL1-IL8 as there are outlet links OL1-OL8, in a
`
`symmetrical network they are the same.
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`Each of the % input switches ISl , 134 are connected to exactly 3X d switches
`
`in middle stage 130 through 3 X (1 links (for example input switch 131 is connected to
`
`middle switch MS(1,1) through the links ML(l,l), ML(1,2), and ML(1,3); and also to
`
`middle switch MS(1,2) through the links ML(1,4), ML(1,5), and ML(1,6)).
`
`Each of the E middle switches MS(1,1) , MS(1,4) in the middle stage 130 are
`d
`
`connected from exactly d input switches through 3Xd links (for example the links
`
`ML(l,l), ML(1,2), and ML(1,3) are connected to the middle switch MS(1,1) from input
`
`switch 131, and the links ML(l,lO), ML(1,11), and ML(1,12) are connected to the middle
`
`switch MS(1, 1) from input switch 132) and also are connected to exactly d switches in
`
`middle stage 140 through 3X d links (for example the links ML(2,1), ML(2,2), and
`
`ML(2,3) are connected from middle switch MS(1,1) to middle switch MS(2,1), and the
`
`links ML(2,4), ML(2,5), and ML(2,6) are connected from middle switch MS(1,1) to
`
`middle switch MS(2,3)).
`
`Similarly each of the E middle switches MS(2,1) — MS(2,4) in the middle stage
`d
`
`140 are connected from exactly d switches in middle stage 130 through 3X d links (for
`
`example the links ML(2,1), ML(2,2), and ML(2,3) are connected to the middle switch
`
`MS(2,1) from middle switch MS(1,1), and the links ML(2,16), ML(2,17), and ML(2,18)
`
`are connected to the middle switch MS(2,1) from middle switch MS(1,3)) and also are
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`connected to exactly d switches in middle stage 150 through 3 X d links (for example the
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`links ML(3,1), ML(3,2), and ML(3,3) are connected from middle switch MS(2,1) to
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`middle switch MS(3,1), and the links ML(3,4), ML(3,5), and ML(3,6) are connected from
`
`middle switch MS(2,1) to middle switch MS(3,3)).
`
`Similarly each of the E middle switches MS(3,1) — MS(3,4) in the middle stage
`d
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`150 are connected from exactly d switches in middle stage 140 through 3X d links (for
`
`example the links ML(3,1), ML(3,2), and ML(3,3) are connected to the middle switch
`
`MS(3,1) from middle switch MS(2,1), and the links ML(3,16), ML(3,17), and ML(3,18)
`
`are connected to the middle switch MS(3,1) from middle switch MS(2,3)) and also are
`
`connected to exactly (1, output switches in output stage 120 through 3X (1 links (for
`
`example the links ML(4,1), ML(4,2), and ML(4,3) are connected to output switch 031
`
`from Middle switch MS(3,1), and the links ML(4,10), ML(4,11), and ML(4,12) are
`
`connected to output switch 032 from middle switch MS(3,1)).
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`Each of the % output switches OSl — 034 are connected from exactly 3X (1
`
`switches in middle stage 150 through 3 X Li links (for example output switch 031 is
`
`connected from middle switch MS(3,1) through the links ML(4,1), ML(4,2), and
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`ML(4,3), and output switch OS1 is also connected from middle switch MS(3,2) through
`
`the links ML(4,10), ML(4,11) and ML(4,12)).
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`Finally the connection topology of the network 100A shown in FIG. 1A is known
`
`to be back to back inverse Benes connection topology.
`
`Referring to FIG. 1B, in another embodiment of network lemk (N, d, s) , an
`
`exemplary symmetrical multi-link multi-stage network 100B with five stages of twenty
`
`switches for satisfying communication requests, such as setting up a telephone call or a
`
`data call, or a connection between configurable logic blocks, between an input stage 110
`
`and output stage 120 Via middle stages 130, 140, and 150 is shown where input stage 110
`
`consists of four, two by six switches 131—184 and output stage 120 consists of four, six by
`
`two switches OSl—OS4. And all the middle stages namely middle stage 130 consists of
`
`four, six by six switches MS(1,1) — MS(1,4), middle stage 140 consists of four, six by six
`
`switches MS(2,1) - MS(2,4), and middle stage 150 consists of four, six by six switches
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`MS(3,1) - MS(3,4).
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`Such a network can be operated in strictly non-blocking manner for multicast
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`connections, because the switches in the input stage 110 are of size two by six, the
`
`switches in output stage 120 are of size six by two, and there are four switches in each of
`
`middle stage 130, middle stage 140 and middle stage 150.
`
`In one embodiment of this network each of the input switches ISl-IS4 and output
`
`switches OSl-OS4 are crossbar switches. The number of switches of input stage 110 and
`
`of output stage 120 can be denoted in general with the variable % , where N is the total
`
`number of inlet links or outlet links. The number of middle switches in each middle stage
`
`is denoted by E . The size of each input switch ISl-IS4 can be denoted in general with
`d
`
`10
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`15
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`the notation d >|< 3d and each output switch OSl—OS4 can be denoted in general with the
`
`notation 3d * d . Likewise, the size of each switch in any of the middle stages can be
`
`denoted as 3d >|< 3d . A switch as used herein can be either a crossbar switch, or a network
`
`of switches each of which in turn may be a crossbar switch or a network of switches. The
`
`symmetric multi-link multi-stage network of FIG. 1B is also the network of the type
`
`leink (N, d, s) , where N represents the total number of inlet links of all input switches
`
`(for example the links ILl-ILS), d represents the inlet links of each input switch or outlet
`
`links of each output switch, and s is the ratio of number of outgoing links from each
`
`input switch to the inlet links of each input switch. Although it is not necessary that there
`
`be the same number of inlet links ILl-IL8 as there are outlet links OLl-OLS, in a
`
`20
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`symmetrical network they are the same.
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`Each of the % input switches ISl — 134 are connected to exactly 3X d switches
`
`in middle stage 130 through 3 X (Z links (for example input switch 131 is connected to
`
`middle switch MS(l,l) through the links ML(l,1), ML(1,2), and ML(1,3); and also to
`
`middle switch MS(1,2) through the links ML(l,4), ML(1,5), and ML(1,6)).
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`25
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`Each of the E middle switches MS(l,l) — MS(1,4) in the middle stage 130 are
`d
`
`connected from exactly d input switches through 3 X d links (for example the links
`
`ML(l,1), ML(1,2), and ML(l ,3) are connected to the middle switch MS(l,l) from input
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`switch 181, and the links ML(1,13), ML(1,14), and ML(1,15) are connected to the middle
`
`switch MS(1, 1) from input switch 183) and also are connected to exactly d switches in
`
`middle stage 140 through 3X (1 links (for example the links ML(2,1), ML(2,2), and
`
`ML(2,3) are connected from middle switch MS(1,1) to middle switch MS(2, 1); and the
`
`links ML(2,4), ML(2,5), and ML(2,6) are connected from middle switch MS(1 ,1) to
`
`middle switch MS(2,2)).
`
`Similarly each of the E middle switches MS(2,1) — MS(2,4) in the middle stage
`d
`
`140 are connected from exactly (I switches in middle stage 130 through 3X (1 links (for
`
`example the links ML(2,1), ML(2,2), and ML(2,3) are connected to the middle switch
`
`10
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`MS(2,1) from middle switch MS(1,1), and the links ML(2,13), ML(2,14), and ML(2,15)
`
`are connected to the middle switch MS(2,1) from middle switch MS(1,3)) and also are
`
`connected to exactly d switches in middle stage 150 through 3 X d links (for example the
`
`links ML(3,1), ML(3,2), and ML(3,3) are connected from middle switch MS(2,1) to
`
`middle switch MS(3,1), and the links ML(3,4), ML(3,5) and ML(3,6) are connected from
`
`15
`
`middle switch MS(2,1) to middle switch MS(3,2)).
`
`Similarly each of the E middle switches MS(3,1) — MS(3,4) in the middle stage
`(1
`
`150 are connected from exactly d switches in middle stage 140 through 3X d links (for
`
`example the links ML(3,1), ML(3,2), and ML(3,3) are connected to the middle switch
`
`MS(3,1) from middle switch MS(2,1), and the links ML(3,13), ML(3,14), and ML(3,15)
`
`are connected to the middle switch MS(3,1) from middle switch MS(2,3)) and also are
`
`connected to exactly d output switches in output stage 120 through 3X d links (for
`
`example the links ML(4,1), ML(4,2), and ML(4,3) are connected to output switch 031
`
`from Middle switch MS(3,1), and the links ML(4,4), ML(4.5), and ML(4,6) are
`
`connected to output switch 032 from middle switch MS(3,1)).
`
`Each of the % output switches OSl , 034 are connected from exactly 3X (1
`
`switches in middle stage 150 through 3 X d links (for example output switch 031 is
`
`connected from middle switch MS(3,1) through the links ML(4,1), ML(4,2), and
`
`20
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`25
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`10
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`15
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`20
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`ML(4,3), and output switch 081 is also connected from middle switch MS(3,3) through
`
`the links ML(4,13), ML(4,14), and ML(4,15)).
`
`Finally the connection topology of the network 100B shown in FIG. 1B is known
`
`to be back to back Omega connection topology.
`
`Referring to FIG. 1C, in another embodiment of network lemk (N, d, s) , an
`
`exemplary symmetrical multi-link multi-stage network 100C with five stages of twenty
`
`switches for satisfying communication requests, such as setting up a telephone call or a
`
`data call, or a connection between configurable logic blocks, between an input stage 110
`
`and output stage 120 via middle stages 130, 140, and 150 is shown where input stage 110
`
`consists of four, two by six switches 131-134 and output stage 120 consists of four, six by
`
`two switches OSl-OS4. And all the middle stages namely middle stage 130 consists of
`
`four, six by six switches MS(1,1) - MS(1,4), middle stage 140 consists of four, six by six
`
`switches MS(2,1) - MS(2,4), and middle stage 150 consists of four, six by six switches
`
`MS(3,1) - MS(3,4).
`
`Such a network can be operated in strictly non-blocking manner for multicast
`
`connections, because the switches in the input stage 110 are of size two by six, the
`
`switches in output stage 120 are of size six by two, and there are four switches in each of
`
`middle stage 130, middle stage 140 and middle stage 150.
`
`In one embodiment of this network each of the input switches 131-184 and output
`
`switches OSl-OS4 are crossbar switches. The number of switches of input stage 110 and
`
`of output stage 120 can be denoted in general with the variable % , where N is the total
`
`number of inlet links or outlet links. The number of middle switches in each middle stage
`
`is denoted by E . The size of each input switch IS ’l-IS4 can be denoted in general with
`d
`
`the notation d >|< 3d and each output switch OSl-OS4 can be denoted in general with the
`
`notation 3d * d . Likewise, the size of each switch in any of the middle stages can be
`
`denoted as 3d >|< 3d . A switch as used herein can be either a crossbar switch, or a network
`
`of switches each of which in turn may be a crossbar switch or a network of switches. The
`
`symmetric multi-link multi-stage network of FIG. 1C is also the network of the type
`
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`thnk (N, d , s) , where N represents the total number of inlet links of all input switches
`
`(for example the links ILl-ILS), d represents the inlet links of each input switch or outlet
`
`links of each output switch, and s is the ratio of number of outgoing links from each
`
`i