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`
`WINNER OF THE
`
`THIRD EDITION
`
`Circuit Design, Layout, and Simulation
`
`R. JACOB BAKER
`
`
`
`
`
`
`
`
`IEEE Series on Microelectronic Systems
`
`WM! ILEM214 PG’WWMWDA EXHIBgegiEEESE
`
`Page 1 of 1214 PGR2019-00042
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`Multipliers
`Symbol
`T
`G
`M (MEG in SPICE)
`k
`m
`H (or u)
`n
`P
`f
`a (not used in SPICE)
`
`Value
`1012
`109
`106
`103
`io-3
`10 6
`10 9
`1012
`io~15
`10'8
`
`Name
`terra
`giga
`mega
`kilo
`milli
`micro
`nano
`pico
`femto
`atto
`
`Physical Constants
`Value/Units
`Name
`Symbol
`Vacuum dielectric
`8.85 aF/|am
`constant
`Silicon dielectric
`constant
`Si02 dielectric
`constant
`SiN, dielectric
`constant
`Boltzmann's constant
`Electronic charge
`Temperature
`Thermal voltage
`
`£<»
`
`esi
`
`s,„
`
`^Ni
`
`k
`q
`T
`vT
`
`11.7s,,
`
`3.97£0
`
`16e0
`
`1.38 x 10"23J/K
`1.6 x 10'19C
`Kelvin
`kT/q = 26 mV @ 300K
`
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`

`CMOS
`CMOS
`
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`IEEE Press
`445 Hoes Lane
`Piscataway, NJ 08854
`
`IEEE Press Editorial Board
`Lajos Hanzo, Editor in Chief
`
`R. Abari
`J. Anderson
`F. Canavero
`T. G. Croda
`
`M. El-Hawary
`B. M. Hammerli
`M. Lanzerotti
`O. Malik
`
`S. Nahavandi
`W. Reeve
`T. Samad
`G. Zobrist
`
`Kenneth Moore, Director of IEEE Book and Information Services (BIS)
`
`IEEE Solid-State Circuits Society, Sponsor
`
`Page 5 of 1214 PGR2019-00042
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`

`

`CMOS
`Circuit Design, Layout, and Simulation
`
`Third Edition
`
`R. Jacob Baker
`
`IEEE Press Series on Microelectronic Systems
`Stuart K. Tewksbury and Joe E. Brewer, Series Editors
`
`IEEE PRESS
`
`»WILEY
`
`A JOHN WILEY & SONS, INC., PUBLICATION
`
`Page 6 of 1214 PGR2019-00042
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`Copyright © 2010 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
`
`Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
`Published simultaneously in Canada.
`
`No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
`by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as
`permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior
`written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to
`the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax
`(978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should
`be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ
`07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission.
`
`Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in
`preparing this book, they make no representations or warranties with respect to the accuracy or
`completeness of the contents of this book and specifically disclaim any implied warranties of
`merchantability or fitness for a particular purpose. No warranty may be created or extended by sales
`representatives or written sales materials. The advice and strategies contained herein may not be suitable
`for your situation. You should consult with a professional where appropriate. Neither the publisher nor
`author shall be liable for any loss of profit or any other commercial damages, including but not limited
`to special, incidental, consequential, or other damages.
`
`For general information on our other products and services or for technical support, please contact our
`Customer Care Department within the United States at (800) 762-2974, outside the United States at
`(317) 572-3993 or fax (317) 572-4002.
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`Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may
`not be available in electronic format. For information about Wiley products, visit our web site at
`www.wiley.com.
`
`Library of Congress Cataloging-in-Publication Data:
`
`Baker, R. Jacob, 1964-
`CMOS : circuit design, layout, and simulation / Jake Baker. — 3rd ed.
`p. cm.
`Summary: "The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM model, data converter architectures, and much
`more. The 3rd edition completes the revised 2nd edition by adding one more chapter (chapter 30) at the
`end, which describes on implementing the data converter topologies discussed in Chapter 29. This addi-
`tional, practical information should make the book even more useful as an academic text and companion
`for the working design engineer. Images, data presented throughout the book were updated, and more
`practical examples, problems are presented in this new edition to enhance the practicality of the book"—
`Provided by publisher.
`Summary: "The third edition of CMOS: Circuit Design, Layout, and Simulation continues to cover the
`practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a
`wide range of analog/digital circuit blocks, the BSIM
`model, data converter architectures, and much more"— Provided by publisher.
`ISBN 978-0-470-88132-3 (hardback)
`1. Metal oxide semiconductors, Complementary—Design and construction. 2. Integrated circuits—
`Design and construction. 3. Metal oxide semiconductor field-effect transistors. I. Title.
`TK7871.99.M44B35 2010
`621.39732—dc22
`
`2010016630
`
`Printed in the United States of America.
`
`10 9 8 7 6 5 4 3 21
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`To my wife Julie
`
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`Brief Contents
`Chapter 1 Introduction to CMOS Design
`Chapter 2 The Well
`Chapter 3 The Metal Layers
`Chapter 4 The Active and Poly Layers
`Chapter 5 Resistors, Capacitors, MOSFETs
`Chapter 6 MOSFET Operation
`Chapter 7 CMOS Fabrication by Jeff Jessing
`Chapter 8 Electrical Noise: An Overview
`Chapter 9 Models for Analog Design
`Chapter 10 Models for Digital Design
`Chapter 11 The Inverter
`Chapter 12 Static Logic Gates
`Chapter 13 Clocked Circuits
`Chapter 14 Dynamic Logic Gates
`Chapter 15 VLSI Layout Examples
`Chapter 16 Memory Circuits
`Chapter 17 Sensing Using AE Modulation
`Chapter 18 Special Purpose CMOS Circuits
`Chapter 19 Digital Phase-Locked Loops
`Chapter 20 Current Mirrors
`Chapter 21 Amplifiers
`Chapter 22 Differential Amplifiers
`Chapter 23 Voltage References
`Chapter 24 Operational Amplifiers I
`Chapter 25 Dynamic Analog Circuits
`Chapter 26 Operational Amplifiers II
`Chapter 27 Nonlinear Analog Circuits
`Chapter 28 Data Converter Fundamentals by Harry Li
`Chapter 29 Data Converter Architectures by Harry Li
`Chapter 30 Implementing Data Converters
`Chapter 31 Feedback Amplifiers with Harry Li
`
`1
`31
`59
`83
`105
`131
`161
`213
`269
`311
`331
`353
`375
`397
`411
`433
`483
`523
`551
`613
`657
`711
`745
`773
`829
`863
`909
`931
`965
`1023
`1099
`
`VI
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`Contents
`
`Preface
`
`xxxi
`
`Chapter 1 Introduction to CMOS Design
`1.1 The CMOS IC Design Process
`1.1.1 Fabrication
`Layout and Cross-Sectional Views
`1.2 CMOS Background
`The CMOS Acronym
`CMOS Inverter
`The First CMOS Circuits
`Analog Design in CMOS
`1.3 An Introduction to SPICE
`Generating a Netlist File
`Operating Point
`Transfer Function Analysis
`The Voltage-Controlled Voltage Source
`An Ideal Op-Amp
`The Subcircuit
`DC Analysis
`Plotting IV Curves
`Dual Loop DC Analysis
`Transient Analysis
`The SIN Source
`An RC Circuit Example
`Another RC Circuit Example
`AC Analysis
`Decades and Octaves
`Decibels
`
`1
`1
`3
`4
`6
`6
`7
`7
`8
`8
`8
`9
`10
`11
`12
`13
`13
`14
`15
`15
`16
`17
`18
`19
`20
`20
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`vii
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`Pulse Statement
`Finite Pulse Rise time
`Step Response
`Delay and Rise time in RC Circuits
`Piece-Wise Linear (PWL) Source
`Simulating Switches
`Initial Conditions on a Capacitor
`Initial Conditions in an Inductor
`Q of an LC Tank
`Frequency Response of an Ideal Integrator
`Unity-Gain Frequency
`Time-Domain Behavior of the Integrator
`Convergence
`Some Common Mistakes and Helpful Techniques
`Chapter 2 The Well
`The Substrate (The Unprocessed Wafer)
`A Parasitic Diode
`Using the N-well as a Resistor
`2.1 Patterning
`2.1.1 Patterning the N-well
`2.2 Laying Out the N-well
`2.2.1 Design Rules for the N-well
`2.3 Resistance Calculation
`Layout of Corners
`2.3.1 The N-well Resistor
`2.4 The N-well/Substrate Diode
`2.4.1 A Brief Introduction to PN Junction Physics
`Carrier Concentrations
`Fermi Energy Level
`2.4.2 Depletion Layer Capacitance
`2.4.3 Storage or Diffusion Capacitance
`2.4.4 SPICE Modeling
`2.5 The RC Delay through the N-well
`RC Circuit Review
`Distributed RC Delay
`Distributed RC Rise Time
`2.6 Twin Well Processes
`
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`24
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`26
`27
`28
`29
`31
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`31
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`32
`35
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`Contents
`
`ix
`
`Design Rules for the Well
`SEM Views of Wells
`Chapter 3 The Metal Layers
`3.1 The Bonding Pad
`3.1.1 Laying Out the Pad I
`Capacitance of Metal-to-Substrate
`Passivation
`An Important Note
`3.2 Design and Layout Using the Metal Layers
`3.2.1 Metalland Vial
`An Example Layout
`3.2.2 Parasitics Associated with the Metal Layers
`Intrinsic Propagation Delay
`3.2.3 Current-Carrying Limitations
`3.2.4 Design Rules for the Metal Layers
`Layout of Two Shapes or a Single Shape
`A Layout Trick for the Metal Layers
`3.2.5 Contact Resistance
`3.3 Crosstalk and Ground Bounce
`3.3.1 Crosstalk
`3.3.2 Ground Bounce
`DC Problems
`AC Problems
`A Final Comment
`3.4 Layout Examples
`3.4.1 Laying Out the Pad II
`3.4.2 Laying Out Metal Test Structures
`SEM View of Metal
`Chapter 4 The Active and Poly Layers
`4.1 Layout Using the Active and Poly Layers
`The Active Layer
`The P- and N-Select Layers
`The Poly Layer
`Self-Aligned Gate
`The Poly Wire
`Suicide Block
`4.1.1 Process Flow
`
`53
`55
`59
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`60
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`Damascene Process Steps
`4.2 Connecting Wires to Poly and Active
`Connecting the P-Substrate to Ground
`Layout of an N-Well Resistor
`Layout of an NMOS Device
`Layout of a PMOS Device
`A Comment Concerning MOSFET Symbols
`Standard Cell Frame
`Design Rules
`4.3 Electrostatic Discharge (ESD) Protection
`Layout of the Diodes
`Chapter 5 Resistors, Capacitors, MOSFETs
`5.1 Resistors
`Temperature Coefficient (Temp Co)
`Polarity of the Temp Co
`Voltage Coefficient
`Using Unit Elements
`Guard Rings
`Interdigitated Layout
`Common-Centroid Layout
`Dummy Elements
`5.2 Capacitors
`Layout of the Poly-Poly Capacitor
`Parasitics
`Temperature Coefficient (Temp Co)
`Voltage Coefficient
`5.3 MOSFETs
`Lateral Diffusion
`Oxide Encroachment
`Source/Drain Depletion Capacitance
`Source/Drain Parasitic Resistance
`Layout of Long-Length MOSFETs
`Layout of Large-Width MOSFETs
`A Qualitative Description of MOSFET Capacitances
`5.4 Layout Examples
`Metal Capacitors
`Polysilicon Resistors
`
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`Chapter 6 MOSFET Operation
`6.1 MOSFET Capacitance Overview/Review
`Case I: Accumulation
`Case II: Depletion
`Case III: Strong Inversion
`Summary
`6.2 The Threshold Voltage
`Contact Potentials
`Threshold Voltage Adjust
`6.3 IV Characteristics of MOSFETs
`6.3.1 MOSFET Operation in the Triode Region
`6.3.2 The Saturation Region
`Cgs Calculation in the Saturation Region
`6.4 SPICE Modeling of the MOSFET
`Model Parameters Related to VTHN
`Long-Channel MOSFET Models
`Model Parameters Related to the Drain Current
`SPICE Modeling of the Source and Drain Implants
`Summary
`6.4.1 Some SPICE Simulation Examples
`Threshold Voltage and Body Effect
`6.4.2 The Subthreshold Current
`6.5 Short-Channel MOSFETs
`Hot Carriers
`Lightly Doped Drain (LDD)
`6.5.1 MOSFET Scaling
`6.5.2 Short-Channel Effects
`Negative Bias Temperature Instability (NBTI)
`Oxide Breakdown
`Drain-Induced Barrier Lowering
`Gate-Induced Drain Leakage
`Gate Tunnel Current
`6.5.3 SPICE Models for Our Short-Channel CMOS
`Process
`BSIM4 Model Listing (NMOS)
`BSIM4 Model Listing (PMOS)
`Simulation Results
`
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`Xll
`
`Contents
`
`Chapter 7 CMOS Fabrication by Jeff Jessing
`7.1 CMOS Unit Processes
`7.1.1 Wafer Manufacture
`Metallurgical Grade Silicon (MGS)
`Electronic Grade Silicon (EGS)
`Czochralski (CZ) Growth and Wafer Formation
`7.1.2 Thermal Oxidation
`7.1.3 Doping Processes
`Ion Implantation
`Solid State Diffusion
`7.1.4 Photolithography
`Resolution
`Depth of Focus
`Aligning Masks
`7.1.5 Thin Film Removal
`Thin Film Etching
`Wet Etching
`Dry Etching
`Chemical Mechanical Polishing
`7.1.6 Thin Film Deposition
`Physical Vapor Deposition (PVD)
`Chemical Vapor Depositon (CVD)
`7.2 CMOS Process Integration
`FEOL
`BEOL
`CMOS Process Description
`7.2.1 Frontend-of-the-Line Integration
`Shallow Trench Isolation Module
`Twin Tub Module
`Gate Module
`Source/Drain Module
`7.2.2 Backend-of-the-Line Integration
`Self-Aligned Silicide (Salicide) Module
`Pre-Metal Dielectric
`Contact Module
`Metallization 1
`Intra-Metal Dielectric 1 Deposition
`
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`162
`162
`162
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`165
`166
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`168
`170
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`Contents
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`xiii
`
`Via 1 Module
`Metallization 2
`Additional Metal/Dieletric Layers
`Final Passivation
`7.3 Backend Processes
`Wafer Probe
`Die Separation
`Packaging
`Final Test and Burn-In
`7.4 Summary
`Chapter 8 Electrical Noise: An Overview
`8.1 Signals
`8.1.1 Power and Energy
`Comments
`8.1.2 Power Spectral Density
`Spectrum Analyzers
`8.2 Circuit Noise
`8.2.1 Calculating and Modeling Circuit Noise
`Input-Referred Noise I
`Noise Equivalent Bandwidth
`Input-Referred Noise in Cascaded Amplifiers
`Calculating VonoiseRMS from a Spectrum: A Summary
`8.2.2 Thermal Noise
`8.2.3 Signal-to-Noise Ratio
`Input-Referred Noise II
`Noise Figure
`An Important Limitation of the Noise Figure
`Optimum Source Resistance
`Simulating Noiseless Resistors
`Noise Temperature
`Averaging White Noise
`8.2.4 Shot Noise
`8.2.5 Flicker Noise
`8.2.6 Other Noise Sources
`Random Telegraph Signal Noise
`Excess Noise (Flicker Noise)
`Avalanche Noise
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`211
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`8.3 Discussion
`8.3.1 Correlation
`Correlation of Input-Referred Noise Sources
`Complex Input Impedance
`8.3.2 Noise and Feedback
`Op-Amp Noise Modeling
`8.3.3 Some Final Notes Concerning Notation
`Chapter 9 Models for Analog Design
`9.1 Long-Channel MOSFETs
`9.1.1 The Square-Law Equations
`PMOS Square-Law Equations
`Qualitative Discussion
`Threshold Voltage and Body Effect
`Qualitative Discussion
`The Triode Region
`The Cutoff and Subthreshold Regions
`9.1.2 Small Signal Models
`Transconductance
`AC Analysis
`Transient Analysis
`Body Effect Transconductance, gmb
`Output Resistance
`MOSFET Transition Frequency, fT
`General Device Sizes for Analog Design
`Subthreshold gm and VTHN
`9.1.3 Temperature Effects
`Threshold Variation and Temperature
`Mobility Variation with Temperature
`Drain Current Change with Temperature
`9.2 Short-Channel MOSFETs
`9.2.1 General Design (A Starting Point)
`Output Resistance
`Forward Transconductance
`Transition Frequency
`9.2.2 Specific Design (A Discussion)
`9.3 MOSFET Noise Modeling
`Drain Current Noise Model
`
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`256
`259
`259
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`276
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`279
`280
`285
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`. . . . 2 97
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`302
`302
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`Contents
`
`xv
`
`Chapter 10 Models for Digital Design
`Miller Capacitance
`10.1 The Digital MOSFET Model
`Effective Switching Resistance
`Short-Channel MOSFET Effective Switching
`Resistance
`10.1.1 Capacitive Effects
`10.1.2 Process Characteristic Time Constant
`10.1.3 Delay and Transition Times
`10.1.4 General Digital Design
`10.2 The MOSFET Pass Gate
`The PMOS Pass Gate
`10.2.1 Delay through a Pass Gate
`The Transmission Gate (The TG)
`10.2.2 Delay through Series-Connected PGs
`10.3 A Final Comment Concerning Measurements
`Chapter 11 The Inverter
`11.1 DC Characteristics
`Noise Margins
`Inverter Switching Point
`Ideal Inverter VTC and Noise Margins
`11.2 Switching Characteristics
`The Ring Oscillator
`Dynamic Power Dissipation
`11.3 Layout of the Inverter
`Latch-Up
`11.4 Sizing for Large Capacitive Loads
`Buffer Topology
`Distributed Drivers
`Driving Long Lines
`11.5 Other Inverter Configurations
`NMOS-Only Output Drivers
`Inverters with Tri-State Outputs
`Additional Examples
`Chapter 12 Static Logic Gates
`12.1 DC Characteristics of the NAND and NOR Gates
`12.1.1 DC Characteristics of the NAND Gate
`
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`311
`312
`312
`314
`
`315
`316
`317
`320
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`12.1.2 DC Characteristics of the NOR Gate
`A Practical Note Concerning VSP and Pass Gates
`12.2 Layout of the NAND and NOR Gates
`12.3 Switching Characteristics
`Parallel Connection of MOSFETs
`Series Connection of MOSFETs
`12.3.1 NAND Gate
`Quick Estimate of Delays
`12.3.2 Number of Inputs
`12.4 Complex CMOS Logic Gates
`Cascode Voltage Switch Logic
`Differential Split-Level Logic
`Tri-State Outputs
`Additional Examples
`Chapter 13 Clocked Circuits
`13.1 The CMOS TG
`Series Connection of TGs
`13.2 Applications of the Transmission Gate
`Path Selector
`Static Circuits
`13.3 Latches and Flip-Flops
`Basic Latches
`An Arbiter
`Flip-Flops and Flow-through Latches
`An Edge-Triggered D-FF
`Flip-Flop Timing
`13.4 Examples
`Chapter 14 Dynamic Logic Gates
`14.1 Fundamentals of Dynamic Logic
`14.1.1 Charge Leakage
`14.1.2 Simulating Dynamic Circuits
`14.1.3 Nonoverlapping Clock Generation
`14.1.4 CMOS TG in Dynamic Circuits
`14.2 Clocked CMOS Logic
`Clocked CMOS Latch
`An Important Note
`PE Logic
`
`356
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`Contents
`
`Domino Logic
`NP Logic (Zipper Logic)
`Pipelining
`Chapter 15 VLSI Layout Examples
`15.1 Chip Layout
`Regularity
`Standard Cell Examples
`Power and Ground Considerations
`An Adder Example
`A 4-to-1 MUX/DEMUX
`15.2 Layout Steps by Dean Moriarty
`Planning and Stick Diagrams
`Device Placement
`Polish
`Standard Cells Versus Full-Custom Layout
`Chapter 16 Memory Circuits
`16.1 Array Architectures
`16.1.1 Sensing Basics
`NMOS Sense Amplifier (NSA)
`The Open Array Architecture
`PMOS Sense Amplifier (PSA)
`Refresh Operation
`16.1.2 The Folded Array
`Layout of the DRAM Memory Bit (Mbit)
`16.1.3 Chip Organization
`16.2 Peripheral Circuits
`16.2.1 Sense Amplifier Design
`Kickback Noise and Clock Feedthrough
`Memory
`Current Draw
`Contention Current (Switching Current)
`Removing Sense Amplifier Memory
`Creating an Imbalance and Reducing Kickback Noise
`Increasing the Input Range
`Simulation Examples
`16.2.2 Row/Column Decoders
`Global and Local Decoders
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`422
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`Reducing Decoder Layout Area
`16.2.3 Row Drivers
`16.3 Memory Cells
`16.3.1 The SRAM Cell
`16.3.2 Read-Only Memory (ROM)
`16.3.3 Floating Gate Memory
`The Threshold Voltage
`Erasable Programmable Read-Only Memory
`Two Important Notes
`Flash Memory
`Chapter 17 Sensing Using AX Modulation
`17.1 Qualitative Discussion
`17.1.1 Examples of DSM
`The Counter
`Cup Size
`Another Example
`17.1.2 Using DSM for Sensing in Flash Memory
`The Basic Idea
`The Feedback Signal
`Incomplete Settling
`17.2 Sensing Resistive Memory
`The Bit Line Voltage
`Adding an Offset to the Comparator
`Schematic and Design Values
`A Couple of Comments
`17.3 Sensing in CMOS Imagers
`Resetting the Pixel
`The Intensity Level
`Sampling the Reference and Intensity Signals
`Noise Issues
`Subtracting VR from Vs
`Sensing Circuit Mismatches
`Chapter 18 Special Purpose CMOS Circuits
`18.1 The Schmitt Trigger
`18.1.1 Design of the Schmitt Trigger
`Switching Characteristics
`18.1.2 Applications of the Schmitt Trigger
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`18.2 Multivibrator Circuits
`18.2.1 The Monostable Multivibrator
`18.2.2 The Astable Multivibrator
`18.3 Input Buffers
`18.3.1 Basic Circuits
`Skew in Logic Gates
`18.3.2 Differential Circuits
`Transient Response
`18.3.3 DC Reference
`18.3.4 Reducing Buffer Input Resistance
`18.4 Charge Pumps (Voltage Generators)
`Negative Voltages
`Using MOSFETs for the Capacitors
`18.4.1 Increasing the Output Voltage
`18.4.2 Generating Higher Voltages: The Dickson Charge
`Pump
`Clock Driver with a Pumped Output Voltage
`NMOS Clock Driver
`18.4.3 Example
`Chapter 19 Digital Phase-Locked Loops
`19.1 The Phase Detector
`19.1.1 The XOR Phase Detector
`19.1.2 The Phase Frequency Detector
`19.2 The Voltage-Controlled Oscillator
`19.2.1 The Current-Starved VCO
`Linearizing the VCO's Gain
`19.2.2 Source-Coupled VCOs
`19.3 The Loop Filter
`19.3.1 XOR DPLL
`Active-PI Loop Filter
`19.3.2 PFD DPLL
`Tri-State Output
`Implementing the PFD in CMOS
`PFD with a Charge Pump Output
`Practical Implementation of the Charge Pump
`Discussion
`19.4 System Concerns
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`19.4.1 Clock Recovery from NRZ Data
`The Hogge Phase Detector
`Jitter
`19.5 Delay-Locked Loops
`Delay Elements
`Practical VCO and VCDL Design
`19.6 Some Examples
`19.6.1 A 2 GHz DLL
`19.6.2 A 1 Gbit/s Clock-Recovery Circuit
`Chapter 20 Current Mirrors
`20.1 The Basic Current Mirror
`20.1.1 Long-Channel Design
`20.1.2 Matching Currents in the Mirror
`Threshold Voltage Mismatch
`Transconductance Parameter Mismatch
`Drain-to-Source Voltage and Lambda
`Layout Techniques to Improve Matching
`Layout of the Mirror with Different Widths
`20.1.3 Biasing the Current Mirror
`Using a MOSFET-Only Reference Circuit
`Supply Independent Biasing
`20.1.4 Short-Channel Design
`An Important Note
`20.1.5 Temperature Behavior
`Resistor-MOSFET Reference Circuit
`MOSFET-Only Reference Circuit
`Temperature Behavior of the Beta-Multiplier
`Voltage Reference Using the Beta-Multiplier
`20.1.6 Biasing in the Subthreshold Region
`20.2 Cascoding the Current Mirror
`20.2.1 The Simple Cascode
`DC Operation
`Cascode Output Resistance
`20.2.2 Low-Voltage (Wide-Swing) Cascode
`An Important Practical Note
`Layout Concerns
`20.2.3 Wide-Swing, Short-Channel Design
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`20.2.4 Regulated Drain Current Mirror
`20.3 Biasing Circuits
`20.3.1 Long-Channel Biasing Circuits
`Basic Cascode Biasing
`The Folded-Cascode Structure
`20.3.2 Short-Channel Biasing Circuits
`Floating Current Sources
`20.3.3 A Final Comment
`Chapter 21 Amplifiers
`21.1 Gate-Drain Connected Loads
`21.1.1 Common-Source (CS) Amplifiers
`Miller's Theorem
`Frequency Response
`The Right-Hand Plane Zero
`A Common-Source Current Amplifier
`Common-Source Amplifier with Source Degeneration
`Noise Performance of the CS Amplifier with
`Gate-Drain Load
`21.1.2 The Source Follower (Common-Drain Amplifier)
`21.1.3 Common Gate Amplifier
`21.2 Current Source Loads
`21.2.1 Common-Source Amplifier
`Class A Operation
`Small-Signal Gain
`Open Circuit Gain
`High-Impedance and Low-Impedance Nodes
`Frequency Response
`Pole Splitting
`Pole Splitting Summary
`Canceling the RHP Zero
`Noise Performance of the CS Amplifier with Current
`Source Load
`21.2.2 The Cascode Amplifier
`Frequency Response
`Class A Operation
`Noise Performance of the Cascode Amplifier
`Operation as a Transimpedance Amplifier
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`21.2.3 The Common-Gate Amplifier
`21.2.4 The Source Follower (Common-Drain Amplifier)
`Body Effect and Gain
`Level Shifting
`Input Capacitance
`Noise Performance of the SF Amplifier
`Frequency Behavior
`SF as an Output Buffer
`A Class AB Output Buffer Using SFs
`21.3 The Push-Pull Amplifier
`21.3.1 DC Operation and Biasing
`Power Conversion Efficiency
`21.3.2 Small-Signal Analysis
`21.3.3 Distortion
`Modeling Distortion with SPICE
`Chapter 22 Differential Amplifiers
`22.1 The Source-Coupled Pair
`22.1.1 DC Operation
`Maximum and Minimum Differential Input Voltage
`Maximum and Minimum Common-Mode Input
`Voltage
`Current Mirror Load
`Biasing from the Current Mirror Load
`Minimum Power Supply Voltage
`22.1.2 AC Operation
`AC Gain with a Current Mirror Load
`22.1.3 Common-Mode Rejection Ratio
`Input-Referred Offset from Finite CMRR
`22.1.4 Matching Considerations
`Input-Referred Offset with a Current Mirror Load
`22.1.5 Noise Performance
`22.1.6 Slew-Rate Limitations
`22.2 The Source Cross-Coupled Pair
`Operation of the Diff-Amp
`Input Signal Range
`22.2.1 Current Source Load
`Input Signal Range
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`22.3 Cascode Loads (The Telescopic Diff-Amp)
`22.4 Wide-Swing Differential Amplifiers
`22.4.1 Current Differential Amplifier
`22.4.2 Constant Transconductance Diff-Amp
`Discussion
`Chapter 23 Voltage References
`23.1 MOSFET-Resistor Voltage References
`23.1.1 The Resistor-MOSFET Divider
`23.1.2 The MOSFET-Only Voltage Divider
`23.1.3 Self-Biased Voltage References
`Forcing the Same Current through Each Side of the
`Reference
`An Alternate Topology
`23.2 Parasitic Diode-Based References
`Diode Behavior
`The Bandgap Energy of Silicon
`Lower Voltage Reference Design
`23.2.1 Long-Channel BGR Design
`Diode-Referenced Self-Biasing (CTAT)
`Thermal Voltage-Referenced Self-Biasing (PTAT)
`Bandgap Reference Design
`Alternative BGR Topologies
`23.2.2 Short-Channel BGR Design
`The Added Amplifier
`Lower Voltage Operation
`Chapter 24 Operational Amplifiers I
`24.1 The Two-Stage Op-Amp
`Low-Frequency, Open Loop Gain, A0LDC
`Input Common-Mode Range
`Power Dissipation
`Output Swing and Current Source/Sinking Capability
`Offsets
`Compensating the Op-Amp
`Gain and Phase Margins
`Removing the Zero
`Compensation for High-Speed Operation
`Slew-Rate Limitations
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`Common-Mode Rejection Ratio (CMRR)
`Power Supply Rejection Ratio (PSRR)
`Increasing the Input Common-Mode Voltage Range
`Estimating Bandwidth in Op-Amps Circuits
`24.2 An Op-Amp with Output Buffer
`Compensating the Op-Amp
`24.3 The Operational Transconductance Amplifier (OTA)
`Unity-Gain Frequency, fu„
`Increasing the OTA Output Resistance
`An Important Note
`OTA with an Output Buffer (An Op-Amp)
`The Folded-Cascode OTA and Op-Amp
`24.4 Gain-Enhancement
`Bandwidth of the Added GE Amplifiers
`Compensating the Added GE Amplifiers
`24.5 Some Examples and Discussions
`A Voltage Regulator
`Bad Output Stage Design
`Three-Stage Op-Amp Design
`Chapter 25 Dynamic Analog Circuits
`25.1 The MOSFET Switch
`Charge Injection
`Capacitive Feedthrough
`Reduction of Charge Injection and Clock Feedthrough
`kT/C Noise
`25.1.1 Sample-and-Hold Circuits
`25.2 Fully-Differential Circuits
`Gain
`Common-Mode Feedback
`Coupled Noise Rejection
`Other Benefits of Fully-Differential Op-Amps
`25.2.1 A Fully-Differential Sample-and-Hold
`Connecting the Inputs to the Bottom (Polyl) Plate
`Bottom Plate Sampling
`SPICE Simulation
`25.3 Switched-Capacitor Circuits
`25.3.1 Switched-Capacitor Integrator
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`Parasitic Insensitive
`Other Integrator Configurations
`Exact Frequency Response of a Switched-Capacitor
`Integrator
`Capacitor Layout
`Op-Amp Settling Time
`25.4 Circuits
`Reducing Offset Voltage of an Op-Amp
`Dynamic Comparator
`Dynamic Current Mirrors
`Dynamic Amplifiers
`Chapter 26 Operational Amplifiers II
`26.1 Biasing for Power and Speed
`26.1.1 Device Characteristics
`26.1.2 Biasing Circuit
`Layout of Differential Op-Amps
`Self-Biased Reference
`26.2 Basic Concepts
`Modeling Offset
`A Diff-Amp
`A Single Bias Input Diff-Amp
`The Diff-Amp's Tail Current Source
`Using a CMFB Amplifier
`Compensating the CMFB Loop
`Extending the CMFB Amplifier Input Range
`Dynamic CMFB
`26.3 Basic Op-Amp Design
`The Differential Amplifier
`Adding a Second Stage (Making an Op-Amp)
`Step Response
`Adding CMFB
`CMFB Amplifier
`The Two-Stage Op-Amp with CMFB
`Origin of the Problem
`Simulation Results
`Using MOSFETs Operating in the Triode Region
`Start-up Problems
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`Lowering Input Capacitance
`Making the Op-Amp More Practical
`Increasing the Op-Amp's Open-Loop Gain
`Offsets
`Op-Amp Offset Effects on Outputs
`Single-Ended to Differential Conversion
`CMFB Settling Time
`CMFB in the Output Buffer (Fig. 26.43) or the
`Diff-Amp (Fig. 26.40)?
`26.4 Op-Amp Design Using Switched-Capacitor CMFB
`Clock Signals
`Switched-Capacitor CMFB
`The Op-Amp's First Stage
`The Output Buffer
`An Application of the Op-Amp
`Simulation Results
`A Final Note Concerning Biasing
`Chapter 27 Nonlinear Analog Circuits
`27.1 Basic CMOS Comparator Design
`Preamplification
`Decision Circuit
`Output Buffer
`27.1.1 Characterizing the Comparator
`Comparator DC Performance
`Transient Response
`Propagation Delay
`Minimum Input Slew Rate
`27.1.2 Clocked Comparators
`27.1.3 Input Buffers Revisited
`27.2 Adaptive Biasing
`27.3 Analog Multipliers
`27.3.1 The Multiplying Quad
`Simulating the Operation of the Multiplier
`27.3.2 Multiplier Design Using Squaring Circuits
`Chapter 28 Data Converter Fundamentals by Harry Li
`28.1 Analog Versus Discrete Time Signals
`28.2 Converting Analog Signals to Digital Signals
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`28.3 Sample-and-Hol