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`JNDAM ENTALS
`
`LAUNCHING INITIAL WWE AND TRANSMISSION LINE REFLECTIONS
`
`23
`
`Vtsource)
`.25
`
`2 v
`ire
`
`TD :- ljfl Es
`
`Zo
`
`Varied)
`
`Assume 23:75 ohms
`20:50 ohms
`VS=0-2 VURS
`”m ”“372... “(2)175 +50 is“
`
`_
`75 _5
`:0le “- ZF ZO :
`0 =0'2
`ZI' +20
`75 +50
`
`20
`
`
`50
`
`, z: —20 L c«~50 =1
`“W z.r+z.;.w oo+so
`
`Response from lattice diagram
`
`Time V(sourt:c
`D
`
`250 [35 as»
`
`l Tfiv
`
`500 135
`
`1’50 135
`
`1000 ps
`
`1250 ps
`
`
`
`I)
`
`aso
`
`I50
`500
`111119. pa
`
`Tom
`
`1250
`
`a transmission
`
`u'ssion Line.
`transmission
`
`governed by
`e impedance
`ignal, 0.8 V,
`11ar case, the
`:ntly, the en-
`the incident
`
`ignal seen at
`then propa—
`s the source,
`nagnitude of
`teen the line
`the value re-
`
`flected signal
`ll give a total
`veling to the
`State value of
`
`FIGURE 2.13 Example 2.2: Lattice diagram used to calculate multiple reflections for
`an underdriven transmission line.
`
`The response of the lattice diagram is shown in the lower corner of Fig—
`ure 2.13. A computer simulation of the response is shown in Figure 2.14 for
`comparison. Notice how the reflections give the waveform a “stair—step” ap-
`pearance at the receiver, even though the unloaded output of the voltage source
`is a square wave. This effect occurs when the source impedance Z! is larger
`than the line impedance 2'0 and is referred to as an underdriven transmission
`line.
`
`Example 2.3: Multiple Reflections or an Over-driven Transmission Line.
`When the line impedance is greater
`an the source impedance, the reflection
`coefficient looking into the source will be negative, which will produce a
`“ringing” effect. This is known as an overdriven transmission line. The lattice
`diagram for an overdriven transmission line is shown in Figure 2.15. Figure
`2.16 is a SPICE simulation showing the response of the system depicted in
`Figure 2.15.
`Next, consider the transmission line structure depicted in Figure 2.17. The
`structure consists of two segments of transmission line cascaded in series. The
`first section is of length X and has a characteristic impedance of ZoI ohms. The
`second section is also of length X and has an impedance of 202 ohms. Finally,
`the structure is terminated with a value of R,. When the signal encounters the
`201/292 impedance junction, part of the signal will be reflected, as governed
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`
`
`\LS
`
`
`
`«LA-
`
`iuctor
`
`.ave a
`min-
`)ed to
`
`mpact
`e sys-
`before
`er, for
`3'. pI'0*
`traces
`.s usuw
`
`d with
`
`onally,
`se first
`es to a
`
`LAUNGHING INlTIAL WAVE AND TRANSMISSION LINE REFLECTiONS
`
`33
`
`point where the reflections won‘t reach steady state in one period. The third
`method is to terminate the transmission line with an impedance equal to the
`characteristic impedance of the line at either end of the transmission line and
`eliminate the reflections.
`
`When the source end of the transmission line is designed to match the
`characteristic impedance of the transmission line, the bus is said to be source
`terminated. When a bus is source terminated, any reflections produced by
`a large impedance discontinuity at the far end of the line (such as an open
`circuit) are eliminated when they reach the source because the reflection
`coefficient will be zero. When a terminating resistor is placed at the far
`end of the line, the bus is said to be parallel, or load terminated. Multiple
`reflections will be eliminated at
`the load because the reflection coeffi-
`
`the load is zero. There are several different ways to implement
`cient at
`these termination methodologies. There are advantages and disadvantages
`to each technique. Several techniques are summarized in the following secw
`dons
`
`Gin-Die Source Termination. On-die source termination requires that the
`I—V curve of the output buffer be very linear over the operating range and
`yield an I—V curve with an impedance very close to the transmission line
`impedance. Ideally, this is an optimum solution because it does not require
`any additional components that increase cost and consume area on the board.
`However, since there are numerous variables that drastically affect the out-
`put impedance of a buffer, it is difficult to achieve a good match between
`the buffer impedance and the line impedance. Some of the variables that
`affect the buffer impedance are silicon fabrication process variations, volt—
`age, temperature, power delivery factors, and simultaneous switching noise.
`These variations will make it difficult to guarantee that the buffer impe-
`dance will match the line impedance. Figure 2.26 depicts this termination
`method.
`
`Series Source Termination. Series source termination requires that a resis-
`tor be added in series with the output bu er. Figure 2.27 depicts the imple-
`mentation of a series source termination,
`'s type of termination requires
`that the sum of the buffer impedance and the value of the resistor be equal
`to the characteristic impedance of the line. This is usually best achieved by
`designing the I—V curve of the output buffer to yield a very low impedance
`such that the bulk of the impedance looking into the source will be contained
`in the resistor. Since precision resistors can be chosen. the effect of the on-die
`impedance variation due to process and environmental variations on the sili-
`con that make on-die source termination difficult can be minimized. The total
`variation in impedance will be small because the resistor, rather than the out—
`put buffer itself, will comprise the built of the impedance. The disadvantages
`of this technique are that the resistors add cost to the board, and it consumes
`significant board area.
`
`
`
`
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`

`

`34
`
`IDEAL manswssrorq LINE FUNDAMENTALS
`
`on diei on PCB
`
`
`
`v“ Steady state voltage: Vs
`
`Source (buffer) impedance
`matched to line impedance
`
`FIGURE 2.26 Orr—die source termination.
`
`i,
`
`
`
`
`
`
`
`_‘n_"l‘: - NFC“: N
`
`
`
`
`
`
`
`on die I on PCB
`
`K
`
`Steady state voltage: V:
`
`
`
`Source impedance 1- R
`
`matched to line impedance
`
`
`
`
`
`
`
`
`
`
`FIGURE 2.27 Series source termination.
`
`
`
`termination
`Load Termination with a Resistive Load. Load or parallel
`
`with a resistive load eliminates the unknown variables associated with the
`
`buffer impedance because a precision resistor can be used. The reflections
`are eliminated at the load and low-impedance output buffers may be used.
`
`The disadvantage is that a large portion of the dc current will be shunted to
`ground, which exacerbates power delivery and thermal problems. The steady-
`
`state voltage will also be determined from the voltage divider between the
`
`source resistance and the load resistance, which creates the need for stronger
`
`buffers. Power delivery is a difficult problem to solve in modern comput-
`ers. Laptops, for example, need very efficient power delivery systems since
`
`they require the use of batteries over prolonged periods of time. As power
`consumption increases, cost also increases, because more elaborate cooling
`
`mechanisms must be introduced to dissipate the excess heat. Figure 2.28 de-
`
`picts this termination scheme.
`
`
`
`
`
`
`
`
`
`
`
`
`AC Load Termination. Ac load termination uses a series capacitor and re-
`sistor at the load end of a transmission line to eliminate the reflections. The
`
`resistor R should be equal to the characteristic impedance of the transmission
`line, and the capacitor CL should be chosen such that the RC time constant at
`
`the load is approximately equal to one or two rise times. It is advised that sim—
`
`ulations be performed to choose the optimum capacitor value for the specific
`
`
`
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`

`TALS
`
`=Vs
`
`9: Vs
`
`ation
`1 the
`Lions
`used.
`ed to
`
`:ady-
`n the
`
`mger
`npute
`Since
`lower
`
`ruling
`8 de-
`
`1d rc-
`'.. The
`ission
`am at
`t sim—
`Iecific
`
`LAUNCHING INiTIAL WAVE AND TRANSMISSION UNE REFLECTIONS
`
`35
`
`
`
`on die
`
`on PCB
`
`23 +R
`
`Steady state voltage =Vs
`«If
`
`FIGURE 2.28 Load termination.
`
`Load impedance matched
`to line impedance
`
`_
`
`I
`
`/ R:30A/
`onPCB
`0:!die
`
`
`
`Steady state voltage =Vs
`load impedance matched
`
`to line impedance
`
`FIGURE 2.29 Ac load termination.
`
`design. The premise behind this termination scheme is that the capacitor will
`initially act like a short circuit and the line will be terminated in its character-
`istic impedance by the resistor R for the duration of the rising or falling edge.
`The capacitor will then charge up and the steady-state voltage of the source,
`lg, will be reached. The advantage of this technique is that the reflections are
`eliminated at the load with no dc power dissipation. The disadvantages are
`that the capacitive loading will increase the signal delay by slowing dowu
`the rising or falling times at the load. Furthermore, the additional resistors
`and capacitors consume board area and increase cost. Figure 2.29 depicts this
`A
`termination scheme.
`
`Common Termination Problems. One of the common obstacles encounter-
`ed during bus design is that the characteristic impedance of the trace tends to
`vary significantly, due to PCB production variations. The PCB variation affects
`all the termination methods; however, it tends to have a bigger impact on
`source termination. Typical, lowicost PCB boards, for example, usually vary as
`much as $1596 from the target impedance over process. This means that if an
`engineer specifies a 654? impedance for the lines on a PCB board, the vendor
`will guarantee that the impedance will be within 55.25 £2 (65 fl — 15%) and
`74.75 52 {65 Q + 15%). Finally, crosstalk will introduce additional variations in
`the impedance. The impact of the crosstalk—induced variations will depend on
`trace-to—trace spacing, the dielectric constant, and the cross-sectional geometry.
`Crosstalk is discussed thoroughly in Chapter 3.
`
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`

`

`L
`
`36
`
`IDEAL TRANSMISSION LINE FUNDAMENTALS
`
`For short lines, when the minimum digital pulse width is long compared to
`the time delay (TD) of the transmission line, source termination is desirable
`since it eliminates the need to shunt a portion of the driver current to ground.
`For long lines, where the width of the digital pulse is smaller than the time
`delay (TD) of the line, load temnination is preferable. In the latter case, there
`will be multiple signals traveling down the transmission line at any given time
`(this is known as pipeline mode). Since reflections off the load will reflect
`back toward the source and interfere with the signals propagating down the
`line, the reflections must be eliminated at the load.
`
`{’
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`2.5. ADDITIONAL EXAMPLES
`
`2.5.1. Problem
`
`
`Assume that two components, U1 and U2, need to communicate with each
`
`
`other via a high—speed digital bus. The components are mounted on a standard
`four-layer motherboard with the stackup shown in Figure 2.30. The driving
`buffers on component U1 have an impedance of 30 $2, an edge rate of 100 ps,
`
`
`and a swing of O to 2 V. The traces on the PCB are required to be 50 £2 and 5 in.
`long. The relative dielectric constant of the board (5,} is 4.0, the transmission
`
`
`line is assumed to be a perfect conductor, and the receiver capacitance is small
`
`
`enough to be ignored. Figure 2.31 depicts the Circuit topology.
`
`
`
`2.5.2. Goals
`
`
`
`
`1. Determine the correct cross~sectional geometry of the PCB shown in
`Figure 2.30 that will yield an impedance of 500.
`
`
`
`2. Calculate the time it takes for the signal to travel from the driver, Ul , to
`the receiver, U2.
`
`
`
`
`
`Ml (Signal layer)
`
`M2 (Ground plane)
`
`memo-a
`
`—"
`]
`D
`
`I
`Ede: a
`04:9,; 3
`‘
`
`3. D
`4 C
`
`2‘5‘3 '
`Sine: tl
`bet“
`are ‘3, 6
`“fin; 'r
`:‘me of
`rad is
`913311“:
`3 6 she
`
`35‘3”
`
`The St:
`on the
`and for
`
`Subset]
`'ffnri
`-.-_1.3_'.
`|.
`
`1} in
`
`33:7 id
`
`
`
`
`M4 (Signal layer)
`
`M3 {DC Power plane)
`
`FIGURE 2.30 Standard four layer motherboard stackup.
`
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`NDUCTANCE AND CAPACITANCE MATRIX
`
`of this noise is calculated as
`
`d] -
`Kaiser.“ = Lm Eire:
`
`(3-1)
`
`Since the induced noise is proportional to the rate of change, mutual induc-
`tance becomes very significant in high-speed digital applications.
`Mutual capacitance is the other mechanism that causes crosstalk. Mutual
`capacitance is simply the coupling of two conductors via the electric field.
`The coupling due to the electric field is represented in the circuit model by a
`mutual capacitor. Mutual capacitance Cm will inject a current onto the victim
`line proportional to the rate in change of voltage on the driven line:
`
`dV -
`Inoiscfi'fl. = Cut—3.1:?
`
`(3‘2)
`
`Again, since the induced noise is proportional to the rate of change, mu-
`tual capacitance also becomes very significant in high-speed digital applica-
`tions.
`
`It should be noted that equations (3.1) and (3.2) are only simple approxima—
`tions used to explain the mechanisms of the coupled noise. Complete crosstalk
`formulas are presented later in the chapter.
`
`LN]
`
`3.2. INDUCTANCE AND CAPACITANCE MATRIX
`
`In systems Where significant coupling occurs between transmission lines, it
`is no longer adequate to represent the electrical characteristics of the line
`with just an inductance and a capacitance, as could be done with the single-
`transmissionvline case presented in Cha ter 2. It becomes necessary to con-
`sider the mutual capacitance and mutualgnductance to fully evaluate the elec»
`tricai performance of a transmission line in a multiconductor system. Equa-
`tions (3.3) and (3.4) depict the typical method of representing the parasitics
`that govern the electrical performance of a coupled transmission line system.
`The inductance and capacitance matrices are knowu collectively as the trans-
`mission line matrices. The example shown is for an N—conductor system and
`is representative of what is usually reported by a field simulator (see Section
`3.3), which is a tool used to calculate the inductance and capacitance matrices
`of a transmission line system.
`
`Inductance matrix =
`
`L11
`
`L21
`
`LIZ
`
`[’22
`
`Luv
`
`— _.——___._.—
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`4a
`
`CROSSTALK
`
`lugut Waveform
`
`Vfinput)
`
`
`a
`Tr;
`
`Case 1
`V(inpul]
`:11: X
`V(near]
`WEN)
`iv
`A
`NE
`
`T
`a
`0‘
`B m...
`
`V(Ww}[&_+§;}
`35_VL”$JE&1—Si]
`Azatc
`C
`
`thw)
`V63!)
`xfi
`
`
`
`
`..,.
`
`2x
`
`'
`LC
`
`Case 1
`
`.
`1.4m th 2 X
`meut]
`++——5—v—b
`
`“=30
`
`2°
`23
`
`R:
`
`Vlnw)
`
`R=Zn
`
`was
`
`
`
` Case 3 Vlgwul]
`Length 2 x
`
`“=20
`1°
`Rem
`
` [n_a]cJ[&-Et]
` __V{mpufliEE
`
`
`
`
` TD = foc
`
`(3.10)
`
`
`FIGURE 3.4 Digital crosstalk noise as a function of victim termination.
`
`—
`
`21'}
`
`L
`
`c
`
`4
`
`The equations in Figure 3.4 assume that the line delay TD is at least twice
`the rise time:
`
`ii
`
`when
`
`lllll
`
`t l
`
`31Fill
`
`Hilll].
`
`E
`
`“l
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`where X is the line length and L and C are the selfwinductance and capacitance
`of the transmission line per unit length. Note that if T, > 2X \/L—C (i.e., the
`edge rate is greater than twice the line delay), the near-end crosstalk will fail
`to achieve its maximum amplitude. To calculate the correct crosstalk voltages
`when '1'; > 2X«1—6:, simply multiply the near-end crosstalk by ZXx/E/Tr. The
`far-end crosstalk equations do not need to be adjusted.
`Note that the near-end crosstalk is independent of the input rise time when
`the rise time is short compared to the line delay (long-line case) and is de-
`pendent on the rise time when the rise time is long compared to the line
`length (short-line case). For this subject matter, the definition of a long line
`is when the electrical delay of the line is at least onevhalf the signal rise time
`(or fall time). Moreover, the near-end magnitude is independent of length
`for the long-line case, while the far end always depends on rise time and
`length.
`It should be noted that the formulas in Figure 3.4 assume that the termina—
`tion resistors on the victim line are matched to the transmission line, which
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`
`
`IROSSTALK
`
`% V(2)
`
`SIMULATING CHOSSTALK USING EQUIVALENT CIRCUIT MODELS
`
`51
`
`Land)
`La“)
`
`JW
`
`FIGURE 3.6 Equivalent circuit model of two coupled lines.
`
`3.5. SIMULATING CROSSTALK USING EQUIVALENT CIRCUIT
`MODELS
`
`Equivalent circuit models are the most general method of simulating crosstalk.
`Figure 3.6 depicts an N -segment equivalent circuit model of two coupled lines
`as modeled in SPICE, where N is the number of sections required such that
`the model will behave as a continuous transmission line and not as a series of
`
`lumped inductors, capacitors, and resistors. As mentioned in Chapter 2, the
`number of segments, N , in a transmission line model depends on the fastest
`edge rate used in the simulation. A g od rule of thumb is that the propagation
`delay of a single segment should be
`ss than or equal to one-tenth of the rise
`time (see Chapter 2 for a full exPlanation).
`The mutual inductance is typically modeled in SPICE-type simulators with
`a coupling factor K:
`
`K =
`
`L12
`
`VLIILZZ
`
`(3.12)
`
`Where L12 is the mutual inductance between lines 1 and 2, and £11 and L22
`are the self—inductances of lines 1 and 2, respectively.
`
`Example 3.4: Creating a Coupled Transmission Line Model. Assume that
`a pair of coupled transmission lines is 5 in. long and a digital signal with a
`rise time of 100 ps is to be simulated. Given the following inductance and
`capacitance matrices, calculate the characteristic impedance, the total propa~
`
`137 V
`
`. It can
`hatches
`
`' Termi-
`: 3 .2. If
`rosstalk
`
`53V
`
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`

`CROSSWALK
`
`WSSTALK-M
`
`
`
`
`
`FIGURE 3.7 Equivalent circuit model used to derive the impedance and velocity
`variations for odd- and even-mode switching patterns.
`
`lczg
`
`
`
`
`
`
`I:
`1*
`V2
`‘
`
`
`
`FIGURE 3.8 Simplified circuit for determining the equivalent odd-mode inductance.
`
`
`
`Since the signals for odd-mode switching are always opposite, it is necessary
`to substitute 11 = ~I2 and VI = -V2 into (3.13) and (3.14). This yields
`
`
`
`
`
`
`
`
`
`d1]
`__
`1rI‘_L°dr +L'"
`d1
`
`
`an1
`elm-11) _
`d:
`_(L°—L’") d:
`
`(3(4)
`d!
`
`(3.15)
`
`(3.16)
`
`FIGURE” S
`
`Similarly. the a
`3.9. Applying
`.g
`.‘f —
`C'- = C. - Q
`
`11
`
`L.
`
`Again substit
`
`lheuefore. ti:
`
`Therefore, the equivalent inductance seen by line 1 in a pair of coupled trans~
`mission lines propagating in odd mode is
`
`Leda = L11 _Lm = L11"L12 (3.17)
`
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`BSTALK
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`mossmLK-INDUCED FLIGHT TIME AND SIGNAL INTEGRITY vanmnous
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`59
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`subtracted and the mutual capacitance must be added to calculate the odd-
`;node characteristics.
`
`These characteristics of even- and odd—mode propagation are due to the
`assumption that the signals are propagating only in TEM (transverse electro-
`magnetic) mode, which means that the electric and magnetic fields are always
`orthogonal to each other. As a result of the TEM assumption, the product
`of L and C remain constant for homogeneous systems (where the fields are
`contained within a single dielectric). Thus, in a multiconductor homogeneous
`system, such as a stripljne array, if L is increased by the mutual inductance,
`C must be decreased by the mutual capacitance such that LC remains con—
`stant. Subsequently, a stripline or buried microstrip which is embedded in a
`:omogeneous dielectric should not exhibit velocity variations due to differ—
`cat switching modes. It will, however, exhibit pattern~dependent impedance
`differences.
`
`in a nonhomogeneous system (where the electric fields will fringe through
`more than one dielectric material) such as an array of microstrip lines, LC
`is not held constant for different propagation modes because the electromag-
`netic fields are traveling partially in air and partially in the dielectric ma—
`serial of the board. In a microstrip system the effective dielectric constant
`:5- a weighted average between air and the dielectric material of the board.
`Because the field patterns change with different propagation modes, the ef-
`‘-.ec\‘we fixekecvr'xc constant \u'\\\ change. depending on \‘txe {xekd densities coin-
`:tined within the board dielectric material and the air. Thus the LC product
`mill be mode dependent in a nonhomogeneous system. The LC product will,
`however, remain constant for a given mode. Subsequently, a microstrip will
`exhibit both a velocity and impedance change, due to different switching patw
`:erns.
`
`POINTS TO REMEMBER
`
`,3
`
`o Odd-mode impedance will always be lower than the singlewline case.
`a Even-mode impedance will always be higher than the single-line case.
`o There are no velocity variations due to crosstalk in a stripline.
`o Crosstalk will induce velocity variations in a microstrip.
`
`
`
`3.6.2. Simulating Traces in a Multiconductor System Using a
`Single-Line Equivalent Model
`
`Two coupled conductors can be modeled as one conductor by determining the
`efiective odd— or even~tuode impedance and propagation delay of the trans-
`mission line pair and substituting these parameters into a single-line model.
`This technique can be expanded to determine the effective crosstalk-induced
`
`Ie Point
`
`veloc—
`36. Al-
`shows
`etween
`and ve-
`*osstalk
`lads di-
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`degree
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`rip, the
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`Figure
`.ual ca-
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`wing in
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`nust be
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`64
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`CHOSSTALK
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`impedance was calculated with no consideration of the effect of adjacent traces
`(65 and 50 [2). This is usually how impedance calculations are made and it
`is how board vendors test (they uSually measure an isolated trace on a test
`coupon). Notice that at small spacing, the single~line impedance is lower than
`the target. This is because the adjacent traces increase the self-capacitance of
`the trace and effectively lower its impedance even when they are not active.
`When they are switching, the full odd- or even—mode impedance is realized.
`When designing high-trace-density boards, it is important to account for this
`effect.
`
`The trace dimensions used to calculate the curves in Figure 3.14:: and 3.14!)
`were chosen to approximate real-world values for both 50- and 65-9 trace val—
`ues (both are common in the industry). Notice that the high-impedance traces
`exhibit significantly more impedance variation than do the lower-impedance
`traces because the reference planesgre much farther in relation to the signal
`spacing. The mutual parasitics for
`ese cross sections are plotted in Figure
`3.14.tl:ote that the mutual parasitics drop off exponentially with spacing. Also
`at the values of the mutual terms are smaller for the lower impedance
`note
`trace. The reader should note that these plots are for a simple two-conductor
`system. Significantly more variation can be expected when the target line is
`coupled to multiple aggressor nets.
`
`
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`'a-rero
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`POINTS
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`(15)
`FIGURE 3.14 Mutual inductance and capacitance for (a) stripline in Figure 313::
`and (b) microstrip in Figure 3.131).
`
`5
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`5:132 to edge marl: mIIe
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