Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 1 of 17 PageID #: 135
`Case 2:20-cv-00048—JRG Document 1—3 Filed 02/21/20 Page 1 of 17 PageID #: 135
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`EXHIBIT C
`EXHIBIT C
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 2 of 17 PageID #: 136
`
`USOO7566964B2
`
`(12) United States Patent
`Kang et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,566,964 B2
`Jul. 28, 2009
`
`(54) ALUMINUM PAD POWER BUS AND SIGNAL
`ROUTING FOR INTEGRATED CIRCUIT
`DEVICES UTILIZING COPPER
`TECHNOLOGY INTERCONNECT
`STRUCTURES
`
`(75) Inventors: Seung H. Kang, Macungie, PA (US);
`Roland P. Krebs, Allentown, PA (US);
`Kurt George Steiner, Fogelsville, PA
`(US); Michael C. Ayukawa, Zionsville,
`PA (US); Sailesh Mansinh Merchant
`-- . .
`s
`Breinigsville, PA (US)
`(73) Assignee: Agere Systems Inc., Allentown, PA (US)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/675,258
`
`(22) Filed:
`(65)
`
`Sep. 30, 2003
`Prior Publication Data
`
`US 2004/O2O1101A1
`
`Oct. 14, 2004
`
`Related U.S. Application Data
`(60) Provisional application No. 60/462,504, filed on Apr.
`10, 2003.
`
`- w
`
`9, 1992 Hamai
`5,148,263 A
`5,436,412 A * 7/1995 Ahmad et al. ............... 174,265
`5,719,448 A
`2f1998 Ichikawa
`6,018,187 A *
`1/2000 Theil et al. .................. 257/.458
`6,107,185. A * 8/2000 Lukanc ......
`... 438,631
`6,204,165 B1
`3/2001 Ghoshal
`6,225,207 B1
`5/2001 Parikh
`6,229,221 B1* 5/2001 Kloen et al. ................ 257,784
`6,232,662 B1* 5/2001 Saran ......................... 257/750
`6,261,944 B1
`7/2001 Mehta et al.
`6,331.482 B1* 12/2001 Honeycutt et al. .......... 438,642
`6,348,731 B1* 2/2002 Ashley et al. ............... 257/751
`(i. R i.
`al. .............. i..
`6.410,435 B1* 6/2002 Ryan .........
`... 438.687
`6,448,650 B1* 9/2002 Saran etal
`... 257/758
`6,451,681 B1
`9/2002 Greer ......................... 438.601
`6,455,943 B1* 9/2002 Sheu et al. .................. 257/758
`6,555.459 B1 * 4/2003 Tokushige et al. .......... 438. 612
`6,614,091 B1* 9/2003 Downey et al. ............. 257/499
`6,649,993 B2 * 1 1/2003 Theil ................
`... 257.458
`6,713,381 B2 * 3/2004 Barret al. ................... 438,622
`6,717.270 B1 * 4/2004 Downey et al. ............. 257/758
`6,740,985 B1* 5/2004 Zhao .......................... 257,784
`6,798,073 B2 * 9/2004 Lin et al. .................... 257/778
`6,930,379 B2* 8/2005 Seshan ...
`... 257,691
`6,979,896 B2 * 12/2005 Seshan ...
`... 257,691
`
`Ol Cal. .....
`
`- - -
`
`
`
`(51) Int. C.
`(2006.01)
`HOIL 23/52
`(52) U.S. Cl. ....................... 257/691; 257/668; 257/701;
`257/750; 257/765; 257/E21.591
`(58) Field of Classification Search ......... 257/750 752,
`257/758 759, 760 762, 773, 668, 691, 701,
`See application file for complete search his376 An integrated circuit device structure and a process for fab
`ricating the structure wherein the power bus interconnect
`References Cited
`structure is formed in the aluminum pad or contact layer. An
`interconnect structure for interconnecting underlying levels
`U.S. PATENT DOCUMENTS
`of interconnect can also be formed in the aluminum pad layer.
`
`(Continued)
`Primary Examiner Wai-Sing Louie
`(57)
`ABSTRACT
`
`(56)
`
`4,060,828 A
`4,840,923 A
`
`11, 1977 Satonaka
`6/1989 Flagello et al.
`
`7 Claims, 9 Drawing Sheets
`
`220 -
`
`232 230
`s
`
`229
`s
`
`224-
`
`22
`
`234
`
`228-
`
`245
`&
`
`238
`
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`sa:
`Sasaas-222
`
`226-2S
`
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`280
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`
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`
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`
`298
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`
`r294
`292
`w easy
`296
`
`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 3 of 17 PageID #: 137
`
`US 7,566,964 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`2001/0036716 A1* 1 1/2001 Chittipeddiet al. ......... 438,584
`2002/0038903 A1* 4/2002 Tsau .......................... 257/.532
`2002fOO68441 A1
`6, 2002 Lin
`
`8, 2002 Lin et al.
`2002/0109232 A1
`ck
`2003/0218259 A1* 11/2003 Chesire et al. .............. 257/786
`
`* cited by examiner
`
`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 4 of 17 PageID #: 138
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`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 1 of 9
`
`US 7,566,964 B2
`
`18- I
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`(PRIOR ART)
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`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 5 of 17 PageID #: 139
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`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 2 of 9
`
`US 7,566,964 B2
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`(PRIOR ART)
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`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 6 of 17 PageID #: 140
`
`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 3 of 9
`
`US 7,566,964 B2
`
`
`
`FIG 4A
`(PRIOR ART)
`
`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 7 of 17 PageID #: 141
`
`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 4 of 9
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`FIG 4B
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 8 of 17 PageID #: 142
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 9 of 17 PageID #: 143
`
`U.S. Patent
`
`J. 28, 2009
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 10 of 17 PageID #: 144
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`U.S. Patent
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 11 of 17 PageID #: 145
`
`U.S. Patent
`
`Jul. 28, 2009
`
`Sheet 8 of 9
`
`US 7,566,964 B2
`
`
`
`FIG. 12
`(PRIOR ART)
`
`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 12 of 17 PageID #: 146
`
`U.S. Patent
`
`, 2009
`Jul. 28
`
`Sheet 9 Of 9
`
`US 7,566,964 B2
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`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 13 of 17 PageID #: 147
`
`US 7,566,964 B2
`
`1.
`ALUMINUM PAD POWER BUS AND SIGNAL
`ROUTING FOR INTEGRATED CIRCUIT
`DEVICES UTILIZING COPPER
`TECHNOLOGY INTERCONNECT
`STRUCTURES
`
`This patent application claims the benefit of the provisional
`patent application filed on Apr. 10, 2003, assigned application
`Ser. No. 60/462,504 and entitled Aluminum Pad PowerBus in
`a Copper Technology.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`2
`The damascene process is one technique for forming cop
`per interconnect structures for integrated circuit devices.
`Typically, the copper damascene process integrally forms
`both the conductive vertical via portion and the conductive
`horizontal interconnect portion (referred to as a metal runner)
`of an interconnect or metallization layer. To form a copper
`damascene structure, a hole or window is formed in a dielec
`tric layer, followed by formation of an overlying trench for the
`metal runner. A subsequent metal deposition step fills both the
`opening and the trench, forming a complete metal layer com
`prising a Substantially vertical conductive via and a Substan
`tially horizontal conductive runner. A final chemical/me
`chanical polishing step planarizes the deposited metal with
`respect to the adjacent surface of the dielectric layer.
`An example of a prior art dual damascene process is illus
`trated in the cross-sectional views of FIGS. 1A-1C during
`various stages of fabrication. As depicted in FIG. 1A, a dielec
`tric layer 10 is deposited or formed on a lower level intercon
`nect 12. A photoresist layer 16, formed over the dielectric
`layer 10, is patterned and etched according to conventional
`techniques to forman opening 18 therein. Ananisotropic etch
`process etches a via hole or window 20 in the dielectric layer
`10 through the opening 18. The photoresist layer 16 is
`removed and replaced by a photoresist layer 30 (see FIG. 1B)
`that is then patterned and etched to form a trench pattern 32.
`An anisotropic etch process forms a trench 34 (extending
`perpendicular to the plane of the paper) and simultaneously
`extends the opening 18 to an upper surface 36 of the lower
`level interconnect 12. The hole or window 20 can be formed
`to stop on the upper surface 36 and expose the lower level
`interconnect 12 (as shown in FIG. 1B) or alternatively can be
`over-etched to extend partially into the lower level intercon
`nect 12.
`As illustrated in FIG. 1C, the hole 20 and trench 34 are
`simultaneously filled with a suitable conductive material 40,
`Such as copper. According to standard process techniques, a
`copper seed layer is first deposited, followed by copper elec
`troplating to fill the hole 20 and the trench34. The material 40
`thus forms a conductive trench 42 and a conductive via 44 in
`contact with the lower level interconnect 12. Additionally, if
`the material 40 comprises copper, a barrier layer, Such as a
`tantalum layer and/or a tantalum-nitride layer (or other
`refractory materials and their nitrides) is deposited in the hole
`20 and the trench 34, prior to copper deposition. The barrier
`layer or layers prevents the diffusion of copper into the sur
`rounding material of the dielectric layer 10. Finally, after
`deposition, the surface of the dielectric layer 10 is planarizes
`to remove excess metal 40 from a field region 48 using tech
`niques, such as chemical/mechanical polishing (CMP), that
`are well known in the art.
`A second example of prior art dual damascene structure for
`integrated circuit devices is shown in FIGS. 2A-2C As
`depicted in FIG. 2A, multiple material layers are formed on a
`lower level interconnect 58, including a first etch stop layer
`60, a first dielectric layer 62, a second etch stop layer 64, a
`second dielectric layer 66, and an etch mask 68. The etch
`mask 68 is patterned and etched to form an opening 70
`therein. Using the etch mask pattern, an anisotropic first etch
`process forms a via opening 72 in the second dielectric layer
`66, extending downwardly through the second etch stop layer
`64 to the first etch stop layer 60. The etch process is termi
`nated when the etchant reaches the etch stop layer 60. The
`etch mask 68 is removed, an etch mask 78 (see FIG. 2B) is
`positioned over the second dielectric layer 66 and masked to
`forman opening 79, which is larger laterally than the opening
`70. A second anisotropic etch process etches a trench 80 in the
`second dielectric layer 66. Simultaneously, the via opening
`
`15
`
`Integrated circuits (or chips) typically comprise a silicon
`Substrate and semiconductor devices, such as transistors,
`formed from doped regions within the substrate. Interconnect
`structures, formed in parallel-like layers overlying the semi
`conductor Substrate, provide electrical connection between
`devices to form electrical circuits. Typically, several (e.g.,
`6-9) interconnect layers (each referred to as an'M' or metal
`lization layer) are required to interconnect the devices in a
`typical integrated circuit. The top interconnect layer com
`prises a plurality of pads that serve as attachment points for
`conductive elements (e.g., bond wires or solder balls) for
`interconnecting the integrated circuit devices to off-chip
`external contacts, such as pins or leads of a package structure.
`A conventional interconnect system comprises a plurality
`of substantially vertical conductive vias or plugs and Substan
`tially horizontal conductive interconnect layers, with a
`dielectric layer disposed between two vertically adjacent
`interconnect layers. Upper level conductive vias interconnect
`two vertically adjacent interconnect layers. Conductive Vias
`in the first or lowest level interconnect an underlying semi
`conductor device region to an overlying interconnect layer.
`The interconnect structures are formed by employing conven
`tional metal deposition, photolithographic masking, pattern
`ing and etching techniques.
`As integrated circuit devices and interconnect structures
`shrink, and as the devices carry higher frequency analog
`signals and higher data rate digital signals, the interconnect
`structures can disadvantageously add delays to the signal
`propagation time. Also, the increasing complexity of the
`devices and the added functionality they provide may require
`a greater number of interconnect structures or levels. But the
`conventional interconnect metallization material, e.g., alumi
`num, severely limits signal speed. Also, the contact resistance
`between the aluminum interconnect structure and device sili
`con regions contributes significantly to the total circuit resis
`tance, especially as the number of circuit devices and inter
`connect structures increases. Finally, as interconnect line
`widths shrink, it is increasingly difficult to deposit conductive
`material in openings or windows to form high aspect ratio
`(i.e., the ratio of the opening depth to the opening diameter)
`conductive Vias.
`Given the known disadvantages of aluminum interconnect
`structures, copper is becoming the interconnect material of
`choice. Copper is a better conductor than aluminum (with a
`resistance of 1.7 micro-ohm cm compared to 3.1 micro-ohm
`cm for aluminum), is less Susceptible to electromigration (a
`phenomenon whereby the aluminum interconnect structure
`thins and can eventually separate due to the electric field and
`thermal gradients formed by current flow through the alumi
`num interconnect), can be deposited at lower temperatures
`(thereby avoiding deleterious effects on previously formed
`dopant profiles) and is Suitable for use in high aspect ratio
`applications.
`
`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`

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`US 7,566,964 B2
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`3
`72 is extended downwardly by etching through the etch stop
`layer 60, to contact with the underlying lower level intercon
`nect 58. According to this technique the first etchant has a
`greater selectivity to the etch stop layer 60 than the second
`etchant. To complete the damascene process, the mask 78 is
`removed and the trench 80 and via opening 72 are simulta
`neously filled with a suitable conductive metal (see FIG. 2C)
`forming a conductive runner 88 and a conductive via 90 in
`contact with the lower level interconnect 58. The excess con
`ductive material is removed from a field region surface 92 of
`the second dielectric layer 66, using techniques such as CMP.
`as known in the art.
`In addition to carrying signals between the semiconductor
`elements, the interconnect structure, whether fabricated from
`aluminum or copper, is also required to Supply power to the
`various device elements through a power bus structure. In
`most integrated circuits the power bus is formed as an addi
`tional interconnect layer, including vertical conductive Vias
`and a horizontal interconnect layer. Typically the power bus
`forms the top level interconnect structure. Disadvanta
`geously, the additional power bus interconnect layer
`increases the number of mask steps, mask layers and process
`steps, all contributing to an increased fabrication cost. Fur
`ther, these additional process steps can lower the device yield
`as they present opportunities for the occurrence of processing
`defects.
`Since the power bus conducts a relatively high current, as
`compared with the signal interconnect structures, the power
`bus interconnect layer generally has a greater width, thick
`ness and pitch than the signal interconnect layers. The power
`bus is also a source of noise and parasitic capacitance that can
`disrupt performance of proximate devices and interconnect
`structures. To limit these effects, the power bus may be iso
`lated from other device structures, with the isolating struc
`tures consuming valuable device area.
`
`4
`fabrication of an interconnect structure, including a power
`bus, according to the teachings of the present invention.
`FIG. 12 is a top view of a prior art interconnect structure for
`an integrated circuit device.
`FIG. 13 is a top view of an interconnect structure con
`structed according to the teachings of the present invention.
`In accordance with common practice, the various
`described device features are not drawn to scale, but are
`drawn to emphasize specific features relevant to the inven
`tion. Reference characters denote like elements throughout
`the figures and text.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`Before describing in detail the particular aluminum pad
`power bus or signal routing technology for integrated circuit
`devices in accordance with the present invention, it should be
`observed that the present invention resides primarily in a
`novel and non-obvious combination of elements and method
`steps. Accordingly, these elements and steps have been rep
`resented by conventional elements and steps in the drawings,
`showing only those specific details that are pertinent to the
`present invention so as not to obscure the description with
`structural details that will be readily apparent to those skilled
`in the art having the benefit of the description herein.
`After fabrication, the integrated circuit is attached to a
`package structure that includes a chip attach region and a
`plurality of externally-disposed package leads through which
`the integrated circuit is connected to external components.
`Since the package leads cannot be connected directly to the
`thin fragile interconnect structures, the chip's final or upper
`metallization layer, referred to as an aluminum pad layer or a
`bond pad layer, comprises a plurality of bond or contact pads
`for connection to the package leads via a conductive lead or
`wire (typically formed from gold or its alloys) connected
`between a bond pad and an interior disposed contact of the
`package lead.
`The bond pads are formed by depositing a metal barrier
`layer, typically tantalum-nitride, tantalum or titanium nitride,
`followed by an aluminum layer on an upper Surface of the
`integrated circuit. The aluminum layer undergoes conven
`tional masking, patterning, and etching steps to define the
`aluminum bond pads. In one embodiment, an antireflective
`coating layer is disposed over the aluminum layer to reduce
`aluminum reflections during the photolithographic process. A
`material of the antireflective coating layer comprises tita
`nium-nitride or silicon oxynitride. The bond pads are con
`nected to one or more underlying interconnect structures or
`circuit elements through underlying conductive Vias. For
`those devices in which the interconnect structures are formed
`from copper, Such as by the damascene process described
`above, the bond pads are conventionally formed of aluminum,
`as it is known that the gold wires adhere poorly to a copper
`bond pad.
`FIG. 3 illustrates a device package 100 comprising pack
`age leads 102. An integrated circuit 104 is affixed within a die
`attach area 106. Bond pads 110 are formed on an upper
`surface 112 of the integrated circuit 104, and connected to the
`package leads 102 by gold wires 114. Generally, the bond
`pads 110 vary between about 40-80 microns and 50-150
`microns in length and width, respectively. Although square
`bond pads are common, use of rectangular bond pads is also
`known in the prior art.
`In another known package structure, referred to as flip-chip
`or bump bonding, the bond wires 114 of FIG.3 are replaced
`with deposited solder bumps 120 formed on the bond pads
`110. See FIG. 4A. Connection to a package 122 of FIG. 4B is
`
`5
`
`10
`
`15
`
`25
`
`30
`
`35
`
`BRIEF SUMMARY OF THE INVENTION
`
`An integrated circuit device comprises a multilevel inter
`connect metallization system formed over a semiconductor
`Substrate layer, wherein the metallization system includes a
`bond pad level and one or more levels of interconnect under
`lying the bond pad level. The bond pad level comprises a
`plurality of contact pads each configured for connection
`external to the device and an interconnect configured to trans
`fer power from one or more of the pads to one or more of the
`underlying levels of interconnect.
`
`40
`
`45
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`50
`
`The present invention can be more easily understood and
`the advantages and uses thereof more readily apparent, when
`considered in view of the following detailed description when
`read in conjunction with the following figures wherein:
`FIGS. 1A-1C and 2A-2C illustrate, in a cross-sectional
`55
`views taken along a common plane, a prior art dual dama
`Scene Structure.
`FIG. 3 is a perspective cut-away view of a package for an
`integrated circuit device constructed according to the teach
`ings of the present invention.
`FIGS. 4A and 4B illustrate prior art flip-chip integrated
`circuit device structures.
`FIG. 5 illustrates, in a cross-sectional view taken along a
`common plane, a prior art interconnect structure including a
`power bus.
`65
`FIGS. 6-11 are cross-sectional views taken along a com
`mon plane, illustrating sequential processing steps in the
`
`60
`
`

`

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`US 7,566,964 B2
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`5
`accomplished by flipping the integrated circuit 104 and Sol
`dering the bumps 120 to receiving pads 124 on the package
`122, that in turn connect to a corresponding package lead. In
`the example of FIG.4B the package leads comprise a ball 126
`in the form of a ball grid array, as is known in the art.
`The metallization layer in which the bond pads 110 are
`formed is required whether the package leads 102 are con
`nected to the integrated circuit 104 by bond wires 114 or
`solder bumps 120. According to the teachings of the present
`invention, the aluminum pad layer comprises both bond or
`contact pads and power bus or signal routing interconnect
`structures through which power is distributed to the elements
`of the integrated circuit device or through which signals are
`routed in the integrated circuit. Since the aluminum pad layer
`is always required to form the bond pads 110, no additional
`process steps, mask steps or metallization levels are added to
`the fabrication process by the present invention. To the con
`trary, one metallization level may be deleted. The invention is
`particularly Suitable for use with copper technologies (i.e.,
`damascene interconnect structures) since dual passivation
`stacks are conventionally formed over the copper intercon
`nect structures prior to deposition of the aluminum for the
`bond pads. Thus the first dual passivation Stack forms an
`effective insulating dielectric between the underlying top
`level interconnect structures and the overlying power bus
`formed in the aluminum pad layer.
`FIG. 5 illustrates a cross-sectional view of a conventional
`prior art interconnect metallization structure for an integrated
`circuit device, showing only the upper metallization levels 5
`and 6 of a six level metal interconnect structure. In this
`example the interconnect structure comprises a copper dual
`damascene interconnect structure. Those skilled in the art
`recognize that the teachings of the present invention can be
`applied to integrated circuit devices having other than six
`levels or interconnect structures.
`According to the dual damascene process, a level 5 con
`ductive via 130 and level 5 conductive runners 132 and 134
`are simultaneously formed within a via opening and trenches
`previously formed in dielectric layers 135 and 136, respec
`tively. The conductive via 130 and level 5 conductive runners
`132 and 134 can be separated by an etch stop layer 137 that
`facilitates separate formation of the via opening and the
`trenches according to conventional dual damascene process
`ing. However, the etch stop layer 137 is not required for
`functionality of the dual damascene elements. The conduc
`tive via 130 is connected to an underlying interconnect struc
`ture or circuit element not shown in FIG. 5. A dielectric
`barrier layer 140 (exemplary materials include silicon nitride,
`silicon carbide or combinations thereof) overlies the dielec
`tric layer 136 and the exposed upper surface of the level 5
`conductive runners 132 and 134. The dielectric barrier layer
`140 acts as an etch stop for fabrication of the next-level
`conductive via and serves as a diffusion barrier to prevent
`surface interdiffusion of copper from the conductive runners
`132 and 134 into the dielectric layer 136. An additional bar
`rier layer 141 surrounds the various copper features to prevent
`lateral copper diffusion into the dielectric material.
`Level 6 conductive vias 142, formed in a dielectric layer
`144, are in electrical contact with the underlying level 5
`conductive runners 132 and 134. A dielectric barrier layer
`145, serving the same purpose as the dielectric barrier layer
`140, overlies the dielectric layer 144. A power bus 146 is
`formed in an oxide layer 148 overlying the dielectric layer
`144. According to the dual damascene process described
`above, the conductive vias 142 and the power bus 146 are
`formed simultaneously in previously formed via openings
`and trenches. Note the larger cross-sectional area required for
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`10
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`15
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`60
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`65
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`6
`the power bus 146 compared with the level 5 conductive
`runners 132 and 134. This is preferred as the power bus 146
`carries higher currents than the low-current signals carried by
`the conductive runners 132 and 134.
`A first passivation stack 149, comprising a silicon nitride
`layer 150, an oxide layer 152 and a silicon nitride layer 154 is
`formed overlying the power bus 146. The first passivation
`stack 149 forms the first layer of the dual passivation scheme
`referred to above. Openings are defined in the first passivation
`stack 149 by conventional lithographic and plasma etching
`processes to expose the underlying copper of the power bus
`146. A conductive barrier layer 155, comprising, for example,
`tantalum, titanium nitride or tantalum nitride, is formed over
`regions of the powerbus 146 exposed through the openings in
`the first passivation stack 149. The conductive barrier layer
`155 prevents the intermixing of copper from the power bus
`146 and aluminum from the aluminum pads. An aluminum
`layer (more conventionally an aluminum-copper alloy) is
`blanket deposited over the barrier layer 155, then masked,
`patterned and etched to forman aluminum pad 156 within the
`opening and further in contact with the underlying power bus
`146 through the conductive barrier layer 155.
`After formation of the aluminum pad 156, the integrated
`circuit device is again passivated by a second passivation
`stack 158, comprising an oxide layer 160 and an overlying
`silicon nitride layer 161.
`As described above, the aluminum pads serve as connec
`tion points between the underlying copper interconnect struc
`tures and the bonds wires 114 of FIG. 3 or the metal bumps
`120 of FIG. 4. It is also known in the art that additional
`under-bond or under-ball/bump metallurgy layers and/or
`materials may be required above and/or below the aluminum
`pad 156 to ensure adequate adhesion with the gold bond wire
`or the solder ball. When the assembly is complete and the
`packaged chip is inserted into an operative circuit, the alumi
`num pad 156 carries power to the elements of the integrated
`circuit device through the power bus 146.
`The thickness of the various layers illustrated in FIG. 5
`(which is not to Scale) is conventional in the art, and the
`techniques for forming the various material layers are also
`well known.
`As FIG. 5 illustrates only a region of the interconnect
`structure, at other locations of the integrated circuit device
`(not shown), aluminum pads similar to the aluminum pad 156
`are connected to underlying conductive runners or conductive
`vias for carrying signals from the package leads to the under
`lying structure or for Supplying signals from the underlying
`structure to the package leads.
`FIG. 6, showing only the uppermost interconnect level of a
`damascene interconnect structure, begins a series of cross
`sectional views depicting the process steps for forming an
`interconnect metallization structure for an integrated circuit
`device according to the teachings of the present invention.
`The conductive via 130 is formed in the dielectric layer 135
`and connected to an underlying interconnect structure or cir
`cuit element not shown in FIG. 6. Conductive runners 132 and
`134 are formed in a dielectric layer 162. In one embodiment
`the dielectric layer 162 comprises silicon dioxide. The mate
`rial of the various dielectric layers shown in FIGS. 6-11 can
`comprise any of the following, and other suitable materials
`known in the art: fluro-silicate glass (FSG), oxides, fluorine
`doped TEOS, (tetraethyl orthosilicate), low dielectric con
`stant materials, and organo-silicate glass (OSG). Also, the
`material of the various barrier layers shown and described can
`comprise silicon carbide, silicon nitride, phosphorous-doped
`oxide and other materials known in the art.
`
`

`

`Case 2:20-cv-00048-JRG Document 1-3 Filed 02/21/20 Page 16 of 17 PageID #: 150
`
`US 7,566,964 B2
`
`7
`As shown in FIG. 7, the first passivation stack 149 (com
`prising the silicon nitride layer 150, the oxide layer 152 and
`the silicon nitride layer 154) is formed overlying the conduc
`tive runners 132 and 134 and the dielectric layer 162. Open
`ings 163 and 165 are defined and formed by conventional
`lithographic and dielectric etching techniques through the
`first passivation stack 149.
`A conductive barrier layer 166 is formed over the exposed
`surface. The barrier layer 166, which typically comprises
`tantalum-nitride, serves as a glue layer between the underly
`ing material and the aluminum to be formed thereover. The
`tantalum-nitride also reduces the known electromigration
`effects encountered in aluminum interconnect structures and
`provides a diffusion barrier between the overlying aluminum
`and the underlying copper.
`An aluminum-copper alloy layer 168 (or in certain
`embodiments, an aluminum-silicon-copper alloy) is blanket
`deposited as shown in FIG. 8, filling the openings 163 and
`165. An aluminum pad 170 is formed within the opening 163
`by patterning, masking and etching steps performed on the
`aluminum layer 168. See FIG. 9. A conductive via 172 is
`formed in the opening 165 in conductive contact with the
`runner 134.
`The same masking, patterning and etching steps employed
`to form the aluminum pad 170 also form a power bus 174 in
`the aluminum layer 168. Also, during the step of forming the
`power bus 174, signal routing interconnects are formed in the
`aluminum-copper alloy layer 168. The signal interconnects
`are not shown in FIG.9 as they are located in other regions of
`the substrate not illustrated in FIG. 9.
`An overlying passivation Stack 180 comprises an oxide
`layer 182 and a silicon nitride layer 184 formed as illustrated
`in FIG. 10. Openings are formed by known techniques in the
`passivation stack 180 to access the aluminum pad 170 (and
`other opening not shown in FIG.10 or 11 are formed to access
`the signal routing interconnects). See FIG. 11 for the final
`structure. The integrated circuit device is now ready for
`attachment to a package and wire bonding or bump bonding
`of the aluminum pad 170 to the package leads.
`The formation of the power bus 174 in the aluminum pad
`40
`layer as taught by the present invention eliminates one met
`allization layer (i.e., a copper layer when the teachings of the
`present invention are applied to a copper damascene process)
`and the attendant process steps and mask requirements. The
`prior art embodiment of FIG. 5 includes a metallization layer,
`i.e., comprising the conductive vias 142, that is absent in the
`structure according to the present invention as shown in FIG.
`11.
`Current integrated circuits are fabricated with aluminum
`pads having a thickness of about 1 micron or greater. This
`thickness is sufficient for carrying the power current and thus
`formation of the power bus 174 in the aluminum pad layer is
`feasible and easily adapted to present fabrication process
`steps. The mask created for patterning the aluminum pads
`according to the prior art can be modified to include patterns
`for the power bus interconnect structures at little extra
`expense.
`FIG. 12 is an exemplary top view of a region of a prior art
`integrated circuit illustrating certain interconnect structures
`on and below a surface of the region. Aluminum pads 190 and
`192 are connected to underlying (i.e., one level below) met
`allization level c