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`Case 2:21-cv-00076—JRG Document 1-5 Filed 03/05/21 Page 1 of 12 PageID #: 73
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`EXHIBIT E
`EXHIBIT E
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`ease221—cv—ooo7a—JRG Document 1—5 HllllllllllllllllllflalllllIlllllllllllllHIllllilllsllllflllllHllHllHlll
`Case 2:21-cv-00076-JRG Document 1-5 Filed 03/05/21 Page 2 of 12 PageID #: 74
`USOO6628171B1
`
`(12) United States Patent
`US 6,628,171 B1
`(10) Patent N0.:
`Chou et al.
`(45) Date of Patent:
`*Sep. 30, 2003
`
`(54)
`
`(75)
`
`METHOD, ARCHITECTURE AND CIRCUIT
`FOR CONTROLLING AND/OR OPERATING
`AN OSCILLATOR
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Inventors: Richard Chou, Palo Alto, CA (US);
`Pidugu L. Narayana, Sunnyvale, CA
`(US); Paul H. Scott, San Jose, CA
`(US)
`
`(73)
`
`Assignee: Cypress Semiconductor Corp., San
`Jose, CA (US)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`4,787,097 A * 11/1988 RiZZO ......................... 327/156
`5,406,592 A *
`4/1995 Baumert
`.......
`327/114
`
`6/1997 Kusakabe ................... 331/1 A
`5,635,875 A
`6,028,727 A
`2/2000 Vishakhadata et a1.
`....... 360/51
`6,078,633 A
`6/2000 Shiotsu et al.
`.............. 375/374
`6,140,880 A
`10/2000 Moyal et al.
`............... 331/1 A
`6,141,394 A
`10/2000 Linebarger et a1.
`......... 375/376
`6,163,186 A
`12/2000 Kurita ........................ 327/157
`6,177,843 B1 *
`1/2001 Chou et al.
`..... 331/25
`
`..................... 331/15
`6,369,660 B1 *
`4/2002 Wei et al.
`
`* cited by examiner
`
`This patent is subject to a terminal dis-
`claimer.
`
`Primary Examiner—Arnold Kinkead
`(74) Attorney, Agent, or Firm—Christopher P. Maiorana,
`RC.
`
`(21)
`
`(22)
`
`(63)
`
`(51)
`(52)
`
`(58)
`
`Appl. N0.: 09/767,989
`
`Filed:
`
`Jan. 23, 2001
`
`Related US. Application Data
`
`Continuation of application No. 09/320,057, filed on May
`26, 1999, now Pat. No. 6,177,843.
`
`Int. C1.7 .................................................. H03L 7/00
`US. Cl.
`......................... 331/1 A; 331/17, 327/156;
`327/159, 375/376
`Field of Search ................... 331/17, 1 A; 327/156,
`327/159, 375/376
`
`(57)
`
`ABSTRACT
`
`An apparatus comprising an oscillator circuit and a logic
`circuit. The oscillator circuit may be configured to present an
`output signal having a frequency in response to (i) a refer-
`ence signal, (ii) a control signal and (iii) the output signal.
`The logic circuit may be configured to present the control
`signal
`in response to (i) the output signal and (ii) the
`reference signal. In one example,
`the logic circuit may
`disable the oscillator When the output signal oscillates
`outside a predetermined range.
`
`18 Claims, 6 Drawing Sheets
`
`FREQUENCY
`DETECTOR
`
`117
`vco_our
`
` LTVCONDN
`F8
`128
`
`108
`
`DIVIDER
`
`
`
`
`
`
`
`DIVIDER
`
`113
`
`

`

`Case 2:21-cv-00076-JRG Document 1-5 Filed 03/05/21 Page 3 of 12 PageID #: 75
`Case 2:21-cv-OOO76-JRG Document 1-5 Filed 03/05/21 Page 3 of 12 PageID #: 75
`
`US. Patent
`
`Sep. 30, 2003
`
`Sheet 1 0f 6
`
`US 6,628,171 B1
`
`15
`
`10\
`
`24
`PHASE
`REFCLK-
`OSCILLATOR
` CHARGE PUMP/
`
`30
`FREQUENCY
`
`FmTER $200 OUT (v00)
`
`
`DETECTOR
`
`
`
`DIVIDER
`
`
`(CONVENTIONAL)
`
`FIG. 1
`
`DISABLE/FREEZE THE VCO CTR
`
`
`200
`
`REFCTR'S BIT<5>
`
`
`
`UPDATE TH
`
`
`INTERNAL LOGIC TRAP SIGNAL
`
`FIG. 5
`
`
`
`
` | MAX VCO FREQ BASED ON C ll
`
`I
`
`
`212\}I
`f210
`
`I\
`
`
`
`I||||
`
`III I
`
`MIN VCO FREQ WHEN VCON=0v
`
`F I G _ 6
`
`LOGIC TRAPS MIN AND MAX PROGRAM THRESHOLDS
`
`

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`Case 2:21-cv-00076-JRG Document 1-5 Filed 03/05/21 Page 9 of 12 PageID #: 81
`Case 2:21-cv-OOO76-JRG Document 1—5 Filed 03/05/21 Page 9 of 12 PageID #: 81
`
`US 6,628,171 B1
`
`1
`
`METHOD, ARCHITECTURE AND CIRCUIT
`FOR CONTROLLING AND/OR OPERATING
`AN OSCILLATOR
`
`This is a continuation of US. Ser. No. 09/320,057, filed
`May 26, 1999, now US. Pat. No. 6,177,843.
`
`FIELD OF THE INVENTION
`
`The present invention relates to a oscillators generally
`and, more particularly, to a method, architecture, and circuit
`for controlling and/or operating an oscillator.
`
`BACKGROUND OF THE INVENTION
`
`Referring to FIG. 1, an example of a conventional phase
`locked loop circuit 10 is shown. The circuit 10 generally
`comprises phase frequency detector 12, a charge pump/filter
`14, a clamp 15, an oscillator 16 and a divider 18. The circuit
`10 is used to multiply a reference signal REFCLK having a
`fixed frequency, received at an input 24, by some multiple
`set by the divider 18. The phase frequency detector 12 is
`coupled to the oscillator 16 through the charge pump/filter
`14. The divider circuit 18 has an input 28 that receives a
`feedback of the signal VCOiOUT presented at an output 29
`of the oscillator 16. The divider 18 presents a signal to the
`input 30 of the phase frequency detector 12. The phase
`frequency detector 12 is capable of indicating both phase
`error and frequency error. Errors coupled through the charge
`pump/filter 14 cause the VCO 16 to change the frequency of
`the signal VCOiOUT to minimize the error. VCO fre-
`quency errors may be managed by the circuit 10. The
`nominal frequency of operation of the signal VCOiOUT
`will be the frequency of the reference signal REFCLK
`multiplied by the divider ratio. A typical phase frequency
`detector 12, as used in the circuit 10, cannot tolerate irregu-
`lar input data streams that may be found in a serial data
`input. As a result, the circuit 10 may not be an adequate
`solution for the VCO frequency error problem. The circuit
`10 uses an analog clamp 15, which is difficult to optimize
`across a wide range of frequencies at the output. Also, the
`voltages presented by the clamp 15 are difficult to control.
`
`SUMMARY OF THE INVENTION
`
`The present invention concerns an apparatus comprising
`an oscillator circuit and a logic circuit. The oscillator circuit
`may be configured to present an output signal having a
`frequency in response to (i) a reference signal, (ii) a control
`signal and (iii) the output signal. The logic circuit may be
`configured to present the control signal in response to (i) the
`output signal and (ii) the reference signal. In one example,
`the logic circuit may disable the oscillator when the output
`signal oscillates outside a predetermined range.
`The objects, features and advantages of the present inven-
`tion include providing a circuit, architecture and/or method
`for controlling and/or operating an oscillator that may (i)
`prevent a runaway condition, (ii) use logic to sample the
`frequency difference between two clocks to compare with
`programmed thresholds to generate a control sign al, (iii)
`provide a circuit with an adjustable granularity and/or (iv)
`may provide an auto-clearing mechanism.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other objects, features and advantages of the
`present
`invention will be apparent from the following
`detailed description and the appended claims and drawings
`in which:
`
`2
`FIG. 1 is a block diagram of a conventional oscillator;
`FIG. 2 is a block diagram of a preferred embodiment of
`the present invention;
`FIG. 3 is a circuit diagram of the logic trap of FIG. 2;
`FIG. 4 is a circuit diagram of the counter of FIG. 2;
`FIG. 5 is a waveform illustrating the operation of the logic
`trap;
`FIG. 6 is a waveform illustrating the function of the logic
`trap;
`FIGS. 7A and 7B are simulations of various waveforms of
`
`the present invention; and
`FIGS. 8A and 8B are simulations of various waveforms of
`
`5
`
`10
`
`15
`
`the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Referring to FIG. 2, a block diagram of a circuit 100 is
`shown in accordance with a preferred embodiment of the
`present invention. The circuit 100 generally comprises an
`oscillator block (or circuit) 101, a divider block (or circuit)
`108, a logic trap block (or circuit) 110 and a divider block
`(or circuit) 111. The oscillator circuit 101 generally com-
`prises a phase frequency detector (PFD) 102, a charge
`pump/filter block (or circuit) 104 and an oscillator 106. In
`one example, the oscillator 101 may be implemented as a
`phase-locked loop (PLL). The oscillator 106 may be imple-
`mented as a voltage controlled oscillator (VCO). The oscil-
`lator 106 generally presents a signal (e.g., VCOiOUT) at an
`output 117 in response to a signal (e.g., a VCO control
`voltage VCON) received at an input 112. The charge pump/
`filter circuit 104 generally presents the signal VCON at an
`output 114 in response to a signal received at an input 116.
`The phase frequency detector 102 generally presents a signal
`at an output 118 in response to a signal received at an input
`120, a signal (e.g., FB) received at an input 122 and a signal.
`(e.g., LTVCONDN) received at an input 124. The signal
`received at the input 120 may be a reference signal having
`a particular frequency (e.g., REFCLK). The divider circuit
`108 generally has an input 126 that may receive the signal
`VCOiOUT and may present the signal FB at an output 128.
`The signal FB may be presented to the input 122 of the phase
`frequency detector 102 as well as to an input 130 of the logic
`trap 110. The logic trap 110 may also comprise an output 132
`that may present the signal LTVCONDN to the input 124 of
`the phase frequency detector 102, an input 134 that may
`receive the signal REFCLK and a input 115 that may receive
`a signal (e.g., RCQ<5>) from the divider 111. The divider
`111 may present the signal RCQ<5> in response to the signal
`REFCLK received at an input 113.
`The logic trap 110 generally samples the frequency dif-
`ference between the signal FB and the signal REFCLK. The
`frequency difference is generally compared to a number of
`programmed thresholds to generate the control signal LTV-
`CONDN that is generally presented to the input 124 of the
`phase detector 102. As a result, the signal LTVCONDN may
`prevent the VCO 106 from “running” away by maintaining
`the frequency of oscillation of the signal VCOiOUT within
`a number of predefined criteria that may avoid the runaway
`condition. Additionally, digital divide counters internal to
`the logic trap 110 are kept within a predefined criteria by
`controlling the signal LTVCONDN (to be described in more
`detail in connection with FIGS. 3 and 4). In one example, the
`logic trap 110 may use a 6-bit VCO counter, which may
`provide a tunable granularity of approximately 6 MHZ in a
`frequency ratio range from 0.06—2. However, additional
`
`

`

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`Case 2:21-cv-OOO76-JRG Document 1—5 Filed 03/05/21 Page 10 of 12 PageID #: 82
`
`US 6,628,171 B1
`
`3
`bit-width counters may be implemented accordingly to meet
`the design criteria of a particular implementation.
`Additionally,
`the logic trap 110 may provide an auto-
`clearing mechanism (e.g., a reset of the VCO 106 may be
`provided in the event the VCO begins to runaway).
`Referring to FIG. 3, a circuit diagram illustrating an
`example of the logic trap 110 is shown. The logic trap 110
`generally comprises a flip-flop 142, a flip-flop 144, a flip-
`fiop 146, a flip-flop 148, a decoder 150, a decoder 152, a gate
`154, an inverter 156, an inverter 158, an inverter 159, a delay
`block (or circuit) 160, a latch block (or circuit) 162, a latch
`block (or circuit) 164 and a counter block (or circuit) 166.
`The flip-flops 142, 144, 146 and 148 may be implemented,
`in one example, as D-type flip-flops. In another example, the
`flip-flops 142, 144, 146 and 148 may be implemented as
`T-type flip-flops. In one example,
`the decoder 150,
`the
`decoder 152 and the gate 154 may be implemented as NOR
`gates. In one example, the latch circuits 162 and 164 may be
`implemented as set-reset (SR) latches.
`The flip-flop 142 and the flip-flop 148 may each receive
`a signal (e.g., PLLiACTIVE) at a control input (e.g., CD).
`The flip-flops 144 and 146 generally receive a signal (e.g.,
`CLEARLTVCOB) at a control input (e. g., CD). The flip-flop
`142 generally receives the signal REFCLK at a clock input
`(e.g., CP) and the signal RCQ<5> at a D input. In one
`example, the signal RCQ<5>, may be one bit of the six bit
`signal RCQ<5:0> generated by the divider 111. An output Q
`of the flip-flop 142 is generally presented to the inverter 156,
`which may present the signal CLEARLTVCO that may be
`used to reset the circuit 100. The inverter 158 generally
`presents a complement (e.g., CLEARLTVCOB) of the sig-
`nal CLEARLTVCO. The decoder 150 generally receives the
`six bits (e.g., <0:5>) of the signal LTVBYTE and presents a
`signal to the D input of the flip-flop 144. Aclock input of the
`flip-flop 144 generally receives the signal FB (that may be
`a byte clock). The flip-flop 144 generally presents a signal at
`the output Q that may be presented to the set input (e.g., S)
`of the SR latch 162. The flip-flop 146 may have a similar
`configuration as the flip-flop 144. Specifically, the flip-flop
`146 may have a D input that may receive a signal from the
`decoder 152, a clock input that may receive the signal FE,
`and a Q output that may present a signal to the set input of
`the set-reset latch 164. The delay 160 generally presents a
`signal to the reset input (e.g., R) of the SR latches 162 and
`164 in response to the signal CLEARTVCO.
`In one
`example, the delay 160 may be a programmable delay.
`The QN output of the latch 162 and the Q output of the
`latch 164 are generally presented to the gate 154. The gate
`154 generally presents a signal (e.g., INTLTVCONDNB) to
`the D input of the flip-flop 148. The flip-flop 148 generally
`comprises (i) a clock input
`that may receive the signal
`CLEARTVCO, (ii) a control input that may receive the
`signal PLLiACTIVE, and/or (iii) a Q output that may
`present a signal
`to the inverter 159. The inverter 159
`generally presents the signal LTVCONDN. The signal LTV-
`CONDN is generally an active high signal. However, an
`additional number of inverters at the Q output of the flip-flop
`148 may be implemented to provide an active low signal
`LTVCONDN.
`
`The counter 166 generally has an input 141 that may
`receive the signal CLEARTVCOB, an input 143 that may
`receive the signal FB, an output that may present the signal
`LTVBYTE<520> and a complement signal LTVBYTEB
`<5:0>.
`
`Referring to FIG. 4, a diagram of the counter 166 is
`shown. The VCO counter 166 generally comprises a number
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`the flip-flops
`In one example,
`of flip-flops 17041—17011.
`17041—17011 may be implemented as D-type flip-flops. In
`another example, the flip-flops 17041—17011 may be imple-
`mented as T-type flip-flops. The flip-flop 170a generally
`presents the first bit (e.g., <0>) of the signal. Similarly, the
`flip-flop 170b generally presents the second bit (e.g., <1>),
`the flip-flop 170C generally presents the third bit (e.g., <2>),
`the flip-flop 170d generally presents the fourth bit (e.g.,
`<3>), the flip-flop 1706 generally presents the fifth bit (e.g.,
`<4>) and the flip-flip 17011 generally presents the sixth bit
`(e.g., <5>) of the signal LTVBYTE<520>. The clock input of
`the flip-flop 170a generally receives the signal FB. The
`clock input of each of the successive flip-flops 170b—17011
`generally receives the QN output of the previous flip-flop.
`For example, the clock input of the flip-flop 170b generally
`receives the QN output (e.g., LTVBYTEB<0>) as a clock
`input. Each of the flip-flops 170b—17011 generally receives
`the signal CLEARLTVCOB at the control input.
`Referring to FIG. 5, a timing diagram illustrating the
`operation of the logic trap is shown. The waveform 200
`generally represents the signal RCQ<5>. When the signal
`RCQ<5> has a negative transition 202, the VCO counter 166
`is generally disabled, or frozen, until a positive transition
`204 of the signal RCQ<5>. After the positive transition 204,
`the VCO counter 166 begins to operate, and remains in
`operation, until the next subsequent negative transition 206
`of the signal RCQ<5>. A box 208 is shown around the
`positive transition 204 and the negative transition 206 of the
`signal RCQ<5>, which is shown in more detail in connec-
`tion with FIG. 6. In general, a logic trap 110 is updated on
`each negative transition (e.g., 202 and 206) of the signal
`RCQ<5>.
`Referring to FIG. 6, a more detailed diagram of the
`portion of the signal RCQ<5> inside the box 208 is shown.
`Aminimum and maximum operating range of the VCO 106
`is generally illustrated between a vertical line 210 and a
`vertical line 212.
`
`A minimum and maximum operating range of the logic
`trap 110 is generally illustrated between a vertical line 220
`and a vertical line 222. In general, if the operating frequency
`of the VCO 106 moves outside the range defined by the
`vertical lines 220 and 222,
`the logic trap 110 generally
`disables the phase frequency la detector 102 which in turn
`discharges the signal VCON until the VCO 106 continues to
`operate within the frequency window defined by the vertical
`line 220 and 222.
`
`The logic trap 110 generally compares the signal
`REFCLK, which may be derived from an external oscillator,
`with the signal VCOiOUT. The logic trap 110 may deter-
`mine if the VCO 106 is running so fast that the signal
`VCOiOUT cannot toggle, which may prevent the oscillator
`101 from ever reducing the voltage of the signal VCON.
`Such a condition may be referred to as a runaway condition.
`During power up, if the VCO control voltage VCON starts
`at VCC, the VCO 106 is generally configured to run as fast
`as possible, which is generally faster than the VCO 106 can
`toggle consistently. This may generate the signal VCOi
`OUT that is effectively running at a lower frequency. In the
`worst case, the signal VCOiOUT will not toggle at all (e. g.,
`frequency=0) which tells the PFD 102 and the charge
`pump/filter 104 that the loop is running too slow, when the
`loop may be running too fast. The PFD 102 and the charge
`pump/filter 104 may then try to increase the VCO control
`voltage VCON incorrectly, thinking that the loop is running
`too fast. Such a condition generally keeps the oscillator 101
`in the runaway state indefinitely. The signal FB will likewise
`be running at a lower than expected frequency since it is
`clocked by the signal VCOiOUT.
`
`

`

`Case 2:21-cv-00076-JRG Document 1-5 Filed 03/05/21 Page 11 of 12 PageID #: 83
`Case 2:21-cv-OOO76-JRG Document 1—5 Filed 03/05/21 Page 11 of 12 PageID #: 83
`
`US 6,628,171 B1
`
`5
`The logic trap 110 anticipates the runaway condition by
`comparing the signal REFCLK and the signal FB. Under
`normal
`locked conditions,
`the signal REFCLK and the
`signal FB will run at the same rate. The logic trap 110 may
`have two general states of operation. In a first state (e.g.,
`STATEl), a potential runaway condition may occur when
`the frequency of the signal FB will be much smaller than the
`frequency of the signal REFCLK. During such a state, the
`logic trap 110 generally forces the PFD 102 and the charge
`pump/filter 104 to continually PUMP DOWN (e.g., lower)
`the VCO control voltage VCON by activating the signal
`LTVCONDN presented to the input 124. The corresponding
`frequency of the signal VCOiOUT is illustrated as the
`leftmost vertical line 220 in FIG. 6. The frequency at the
`vertical line 220 must generally be less than the lowest
`frequency the VCO generates when the signal VCON is at
`0V (illustrated by the dashed vertical line 210 in FIG. 6).
`A second state (e.g., STATE2) may occur when (i) the
`frequency of the signal FB runs much faster than the
`frequency of the signal REFCLK and (ii) the signal FB is
`still
`toggling consistently. The logic trap 110 may then
`PUMP DOWN the VCO control voltage VCON by activat-
`ing the signal LTVCONDN. The corresponding frequency
`of the signal VCOiOUT is illustrated as the vertical line
`222 in FIG. 6. The signal VCOiOUT generally needs to
`overshoot the PLL lock frequency in order to work properly.
`The PLL lock frequency is determined by the loop damping
`factor C and is illustrated by the dashed vertical line 212 in
`FIG. 6.
`
`The divider 111 may be implemented as a large ripple
`counter. In one example,
`the divider 111 may provide a
`divide by 64 to produce the signal RCQ<5>. The counter
`166 may divide the signal FB in a similar fashion. RCQ<5>
`will generally activate the logic trap 110 every 32 pulses of
`the signal REFCLK, then deactivate the logic trap 110 for
`the next 32 pulses of the signal REFCLK, and then repeat the
`cycle counter 166. This may be accomplished since the
`flip-flops 144 and 146 may be reset/set by the signals.
`CLEARLTVCO/CLEARLTVCOB which may be activated
`when the RCQ<5> is in a
`low state. The signal
`LTVCONDN, which may be, in one example, an active high
`signal, may drive the PFD 102. The signal LTVCONDN
`may be a registered version of the signal.
`INTLTV-
`CONDNB (which is active low) and may be clocked from
`the signal CLEARTVCO (e.g., whenever logic trap 110 is
`deactivated).
`the following is an
`Starting with a deactivated state,
`example of a sequence of events describing the operation of
`the logic trap 110. However, other particular transitions may
`be implemented accordingly to meet the design criteria of a
`particular implementation. When the signal RCQ<5>=0 is
`clocked, the counter 166 is set to a first value (e.g., 3F). The
`signal CLEARTVCO may force the signal
`INTLTV-
`CONDNB active thru the delay 160, the latch 162, the latch
`164 and the gate 154.
`After the signal RCQ<5>=1 is clocked, the counter 166
`and the flip-flops 144, 146 and 148 may no longer reset.
`Again, the signal INTLTVCONDNB generally starts off in
`an active state.
`
`The counter 166 starts counting up after each cycle of the
`signal FB starting from 3F, (e.g., 3F-00-01-02- .
`.
`. 3E-3F-
`00- .
`.
`. ) as long as the signal RCQ<5> has remained high,
`which generally lasts for 32 cycles of the signal REFiCLK.
`State. $1 is 00 and state $2 is 3E.
`
`If the signal FB clocks less than twice after 32 cycles of
`the signal REFCLK,
`the signal INTLTVCONDNB will
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`remain active, generally indicating that the VCO 106 is
`toggling slower than the minimum threshold indicated; by
`line 220 in FIG. 6.
`
`If the signal FB clocks 2 or more times, but less than 65
`times, after 32 cycles of the signal REFCLK, the state SI
`(00) would be decoded and latched after the second clock of
`the signal FE and will generally remain latched. This may
`set the signal INTLTVCONDNB to an inactive state since
`the inputs to the gate 154 are both low. This generally
`indicates that the VCO 106 is toggling at a correct rate
`indicated by the region between the lines 220 and 222 in
`FIG. 6.
`
`If the signal FB clocks more than 65 times after 32 cycles
`of the signal REFCLK, the state SZ (3E) would be decoded
`and latched after the 65th clock of the signal FE and remain
`latched. This generally sets the signal INTLTVCONDNB to
`an active state. This condition generally indicates that the
`VCO 106 is toggling at faster rate than the rate indicated by
`the line 222 in FIG. 6.
`
`After the signal RCQ<5>=0 is clocked, the logic trap 110
`is generally inactive and the signal INTLTVCONDNB is
`propagated to the PFD 102 and is generally held for 32
`cycles of the signal REFCLK. If the signal LTVCONDN is
`active, the PFD 102 will generally pump down the signal
`VCON for 32 REFCLK cycles. The method may repeat
`from the step where the signal RCQ<5>=1 is clocked. If the
`signal VCOiOUT is not within the specified frequency
`limits of FIG. 6, the signal LTVCONDN will remain active.
`The logic trap 110 will generally determine whether to
`inactivate the signal LTVCONDN every 64 REFCLK
`cycles.
`FIGS. 7a and 7b illustrate the logic trap 110 activating and
`staying inactive below, and above the lower frequency limit
`respectively. FIGS. 8a and 8b illustrate the logic trap 110
`staying inactive and activating below and above the upper
`frequency limit respectively.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof, it will be understood by those skilled in the art that
`various changes in form and details may be made without
`departing from the spirit and scope of the invention.
`What is claimed is:
`
`1. A circuit comprising:
`an oscillator circuit having (i) first, second and third input
`terminals and (ii) an output terminal coupled to the
`second input terminal; and
`a logic circuit configured to present a control signal to a
`phase frequency detector, the logic circuit having (i)
`input terminals coupled to the first and second input
`terminals of said oscillator circuit, respectively, (ii) a
`counter circuit coupled to the first and second input
`terminals of said oscillator circuit input terminals, and
`(iii) a first decoder circuit coupled to the counter circuit
`through a first plurality of terminals and having a first
`output terminal coupled to the third input terminal of
`said oscillator circuit.
`
`2. The circuit according to claim 1, wherein said oscillator
`circuit comprises:
`a detector circuit having (i) input terminals coupled to the
`first and second input
`terminals of said oscillator
`circuit, respectively, and (ii) an output terminal; and
`a filter circuit coupled to the detector circuit output
`terminal and having an output terminal; and
`a controlled oscillator circuit having an input terminal
`coupled to the filter circuit output terminal and having
`the oscillator circuit output terminal.
`
`

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`Case 2:21-cv-00076-JRG Document 1-5 Filed 03/05/21 Page 12 of 12 PageID #: 84
`Case 2:21-cv-OOO76-JRG Document 1—5 Filed 03/05/21 Page 12 of 12 PageID #: 84
`
`US 6,628,171 B1
`
`7
`3. The circuit according to claim 2, wherein said detector
`circuit comprises the third input terminal.
`4. The circuit according to claim 2, wherein the detector
`circuit comprises the phase frequency detector circuit.
`5. The circuit according to claim 1, wherein the logic
`circuit further comprises:
`terminals
`input
`a second decoder circuit having (i)
`coupled to the counter circuit through a second plural-
`ity of terminals and (ii) a second output terminal; and
`an output circuit having (i) input terminals coupled to the
`first and second output terminals of the first and second
`decoder circuits, respectively, and (ii) an output termi-
`nal coupled to the third input terminal of the oscillator
`circuit.
`
`6. The circuit according to claim 5, wherein said output
`circuit further comprises:
`a first latch circuit coupled between the first decoder
`circuit and the output terminal of the output circuit; and
`a second latch circuit coupled between the second decoder
`circuit and the output terminal of the output circuit.
`7. A method for generating an output signal having a
`frequency, comprising the steps of:
`(A) generating a feedback signal corresponding to the
`output signal;
`(B) comparing a reference signal to the feedback signal to
`sample a frequency difference between said reference
`signal and said output signal;
`(C) determining a time corresponding to a frequency of
`one of the reference signal and the feedback signal;
`(D) counting a number of cycles of another of the refer-
`ence signal and the feedback signal during the time to
`indicate whether said frequency difference is below a
`first predetermined threshold, above a second predeter-
`mined threshold, or between said first and second
`predetermined thresholds;
`(E) generating a control signal corresponding to the
`number of cycles; and
`(F) adjusting the frequency of the output signal when the
`frequency difference is less than the first predetermined
`threshold or above the second predetermined threshold.
`8. The method according to claim 7, wherein step (A)
`comprises dividing the frequency of the output signal by an
`integer.
`9. The method according to claim 7, further comprising
`the steps of:
`comparing a phase of the reference signal to a phase of the
`feedback signal; and
`generating a control voltage in response to the step of
`comparing a phase.
`10. The method according to claim 7, wherein step (E)
`comprising the sub-steps of:
`generating a first logic state of the control signal when
`said number of cycles is less than a first predetermined
`number; and
`generating a second logic state of the control signal when
`said number of cycles is between the first predeter-
`mined number and a second predetermined number
`greater than said first predetermined number.
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`11. The method according to claim 10, further comprising
`the step of:
`generating the first logic state of the control signal when
`said number of cycles is greater than the second pre-
`determined number of said cycles.
`12. A circuit comprising:
`an oscillator circuit having (i) first, second and third input
`terminals and (ii) an output terminal coupled to the
`second input terminal; and
`a logic circuit configured to present a first control signal
`to a phase frequency detector, the logic circuit com-
`prising (i) a plurality of flip-flops, (ii) input terminals
`coupled to the first and second input terminals of said
`oscillator circuit, respectively, and (iii) an output ter-
`minal coupled to the third input terminal of said oscil-
`lator circuit.
`
`13. The circuit according to claim 12, wherein said logic
`circuit comprises:
`a first flip-flop configured to receive a second control
`signal, said first flip-flop coupled to the first
`input
`terminal of said logic circuit; and
`a second flip-flop configured to receive a third control
`signal, said second flip-flop coupled to the second input
`terminal of said logic circuit.
`14. The circuit according to claim 13, wherein said logic
`circuit further comprises:
`a third flip-flop configured to receive a fourth control
`signal,
`therein said third flip-flop is coupled to the
`second input terminal of said logic circuit, and said
`fourth control signal is related to said third control
`signal.
`15. The circuit according to claim 13, wherein said logic
`circuit further comprises:
`a counter circuit (i) having input terminals coupled to (A)
`an output terminal of said first flip-flop and (B) the
`second input
`terminal f said oscillator circuit,
`(ii)
`configured to count a number of cycles corresponding
`to a difference between an output signal of said oscil-
`lator circuit and a reference signal, and (iii) providing
`a multibit signal corresponding to said number of
`cycles; and
`a decoder circuit receiving said multibit signal and having
`an output terminal coupled to an input terminal of said
`third flip-flop.
`16. The circuit according to claim 14, wherein said logic
`circuit further comprises:
`a delay circuit having and input coupled to an output of
`said first flip-flop, and
`an output circuit having (i) input terminals coupled to an
`output from each of said delay circuit, said second
`flip-flop and said third flip-flop, and (ii) an output
`terminal coupled to said output terminal of said logic
`circuit.
`
`17. The circuit according to claim 12, wherein said
`oscillator circuit comprises said phase frequency detector.
`18. The circuit according to claim 1, wherein said oscil-
`lator circuit comprises said phase frequency detector.
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